From: Zhenzhong Duan <zhenzhong.duan@intel.com>
To: qemu-devel@nongnu.org
Cc: alex.williamson@redhat.com, clg@redhat.com,
eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com,
jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,
joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com,
kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com,
Zhenzhong Duan <zhenzhong.duan@intel.com>,
Yi Sun <yi.y.sun@linux.intel.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: [PATCH v4 13/17] intel_iommu: piotlb invalidation should notify unmap
Date: Mon, 30 Sep 2024 17:26:27 +0800 [thread overview]
Message-ID: <20240930092631.2997543-14-zhenzhong.duan@intel.com> (raw)
In-Reply-To: <20240930092631.2997543-1-zhenzhong.duan@intel.com>
This is used by some emulated devices which caches address
translation result. When piotlb invalidation issued in guest,
those caches should be refreshed.
For device that does not implement ATS capability or disable
it but still caches the translation result, it is better to
implement ATS cap or enable it if there is need to cache the
translation result.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
---
hw/i386/intel_iommu.c | 35 ++++++++++++++++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 5ea59167b3..91d7b1abfa 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2908,7 +2908,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,
continue;
}
- if (!s->scalable_modern) {
+ if (!s->scalable_modern || !vtd_as_has_map_notifier(vtd_as)) {
vtd_address_space_sync(vtd_as);
}
}
@@ -2920,6 +2920,9 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
bool ih)
{
VTDIOTLBPageInvInfo info;
+ VTDAddressSpace *vtd_as;
+ VTDContextEntry ce;
+ hwaddr size = (1 << am) * VTD_PAGE_SIZE;
info.domain_id = domain_id;
info.pasid = pasid;
@@ -2930,6 +2933,36 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
g_hash_table_foreach_remove(s->iotlb,
vtd_hash_remove_by_page_piotlb, &info);
vtd_iommu_unlock(s);
+
+ QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) {
+ if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
+ vtd_as->devfn, &ce) &&
+ domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) {
+ uint32_t rid2pasid = VTD_CE_GET_RID2PASID(&ce);
+ IOMMUTLBEvent event;
+
+ if ((vtd_as->pasid != PCI_NO_PASID || pasid != rid2pasid) &&
+ vtd_as->pasid != pasid) {
+ continue;
+ }
+
+ /*
+ * Page-Selective-within-PASID PASID-based-IOTLB Invalidation
+ * does not flush stage-2 entries. See spec section 6.5.2.4
+ */
+ if (!s->scalable_modern) {
+ continue;
+ }
+
+ event.type = IOMMU_NOTIFIER_UNMAP;
+ event.entry.target_as = &address_space_memory;
+ event.entry.iova = addr;
+ event.entry.perm = IOMMU_NONE;
+ event.entry.addr_mask = size - 1;
+ event.entry.translated_addr = 0;
+ memory_region_notify_iommu(&vtd_as->iommu, 0, event);
+ }
+ }
}
static bool vtd_process_piotlb_desc(IntelIOMMUState *s,
--
2.34.1
next prev parent reply other threads:[~2024-09-30 9:32 UTC|newest]
Thread overview: 67+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-30 9:26 [PATCH v4 00/17] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-09-30 9:26 ` [PATCH v4 01/17] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-09-30 9:26 ` [PATCH v4 02/17] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-09-30 9:26 ` [PATCH v4 03/17] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-10-04 5:22 ` CLEMENT MATHIEU--DRIF
2024-11-03 14:21 ` Yi Liu
2024-09-30 9:26 ` [PATCH v4 04/17] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-11-04 2:49 ` Yi Liu
2024-11-04 7:37 ` CLEMENT MATHIEU--DRIF
2024-11-04 8:45 ` Yi Liu
2024-11-04 11:46 ` Duan, Zhenzhong
2024-11-04 11:50 ` Michael S. Tsirkin
2024-11-04 11:55 ` Duan, Zhenzhong
2024-11-04 12:01 ` Michael S. Tsirkin
2024-11-04 12:03 ` Duan, Zhenzhong
2024-09-30 9:26 ` [PATCH v4 05/17] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-09-30 9:26 ` [PATCH v4 06/17] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-11-03 14:21 ` Yi Liu
2024-11-04 3:05 ` Duan, Zhenzhong
2024-11-04 7:02 ` Yi Liu
2024-09-30 9:26 ` [PATCH v4 07/17] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-11-03 14:22 ` Yi Liu
2024-09-30 9:26 ` [PATCH v4 08/17] intel_iommu: Set accessed and dirty bits during first stage translation Zhenzhong Duan
2024-11-04 2:49 ` Yi Liu
2024-11-08 3:15 ` Jason Wang
2024-09-30 9:26 ` [PATCH v4 09/17] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-11-04 2:50 ` Yi Liu
2024-11-04 3:38 ` Duan, Zhenzhong
2024-11-04 7:36 ` Yi Liu
2024-09-30 9:26 ` [PATCH v4 10/17] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-11-04 2:50 ` Yi Liu
2024-11-04 5:40 ` Duan, Zhenzhong
2024-11-04 7:05 ` Yi Liu
2024-09-30 9:26 ` [PATCH v4 11/17] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-11-04 2:50 ` Yi Liu
2024-11-04 5:47 ` Duan, Zhenzhong
2024-09-30 9:26 ` [PATCH v4 12/17] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-11-04 2:51 ` Yi Liu
2024-09-30 9:26 ` Zhenzhong Duan [this message]
2024-11-04 3:05 ` [PATCH v4 13/17] intel_iommu: piotlb invalidation should notify unmap Yi Liu
2024-11-04 8:15 ` Duan, Zhenzhong
2024-11-05 6:29 ` Yi Liu
2024-11-05 7:25 ` Duan, Zhenzhong
2024-11-08 4:39 ` Jason Wang
2024-09-30 9:26 ` [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in scalable modern mode Zhenzhong Duan
2024-11-04 3:16 ` Yi Liu
2024-11-04 3:19 ` Duan, Zhenzhong
2024-11-04 7:25 ` Yi Liu
2024-11-08 4:41 ` Jason Wang
2024-11-08 5:30 ` Duan, Zhenzhong
2024-11-11 1:24 ` Jason Wang
2024-11-11 2:58 ` Duan, Zhenzhong
2024-11-11 3:03 ` Jason Wang
2024-09-30 9:26 ` [PATCH v4 15/17] intel_iommu: Introduce a property x-fls for " Zhenzhong Duan
2024-11-04 4:25 ` Yi Liu
2024-11-04 6:25 ` Duan, Zhenzhong
2024-11-04 7:23 ` Yi Liu
2024-11-05 3:11 ` Duan, Zhenzhong
2024-11-05 5:56 ` Yi Liu
2024-11-05 6:03 ` Duan, Zhenzhong
2024-11-05 6:26 ` Yi Liu
2024-09-30 9:26 ` [PATCH v4 16/17] intel_iommu: Introduce a property to control FS1GP cap bit setting Zhenzhong Duan
2024-11-04 7:00 ` Yi Liu
2024-11-08 4:45 ` Jason Wang
2024-09-30 9:26 ` [PATCH v4 17/17] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-09-30 9:52 ` Duan, Zhenzhong
2024-10-25 6:32 ` [PATCH v4 00/17] intel_iommu: Enable stage-1 translation for emulated device Duan, Zhenzhong
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