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From: Klaus Jensen <its@irrelevant.dk>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Keith Busch <kbusch@kernel.org>,
	Klaus Jensen <k.jensen@samsung.com>,
	Klaus Jensen <its@irrelevant.dk>,
	Jesper Devantier <foss@defmacro.it>,
	qemu-block@nongnu.org
Subject: [PULL 1/5] hw/nvme: report id controller metadata sgl support
Date: Tue,  1 Oct 2024 09:04:13 +0200	[thread overview]
Message-ID: <20241001070418.28737-2-its@irrelevant.dk> (raw)
In-Reply-To: <20241001070418.28737-1-its@irrelevant.dk>

From: Keith Busch <kbusch@kernel.org>

The controller already supports this decoding, so just set the
ID_CTRL.SGLS field accordingly.

Signed-off-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Klaus Jensen <k.jensen@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
 hw/nvme/ctrl.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 2589e1968ea6..d5ea9ad653f2 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -8536,7 +8536,8 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
 
     id->ocfs = cpu_to_le16(NVME_OCFS_COPY_FORMAT_0 | NVME_OCFS_COPY_FORMAT_1 |
                             NVME_OCFS_COPY_FORMAT_2 | NVME_OCFS_COPY_FORMAT_3);
-    id->sgls = cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN);
+    id->sgls = cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN |
+                           NVME_CTRL_SGLS_MPTR_SGL);
 
     nvme_init_subnqn(n);
 
-- 
2.45.2



  reply	other threads:[~2024-10-01 14:15 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-01  7:04 [PULL 0/5] nvme queue Klaus Jensen
2024-10-01  7:04 ` Klaus Jensen [this message]
2024-10-01  7:04 ` [PULL 2/5] hw/nvme: clear masked events from the aer queue Klaus Jensen
2024-10-01  7:04 ` [PULL 3/5] hw/nvme: support CTRATT.MEM Klaus Jensen
2024-10-01  7:04 ` [PULL 4/5] hw/nvme: add knob for CTRATT.MEM Klaus Jensen
2024-10-01  7:04 ` [PULL 5/5] hw/nvme: add atomic write support Klaus Jensen
2024-10-01 12:09 ` [PULL 0/5] nvme queue Peter Maydell

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