* [PULL v3 00/35] riscv-to-apply queue
@ 2024-10-02 5:50 Alistair Francis
2024-10-02 5:50 ` [PULL v3 01/35] target/riscv: Add a property to set vl to ceil(AVL/2) Alistair Francis
` (35 more replies)
0 siblings, 36 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Alistair Francis
The following changes since commit 718780d20470c66a3a36d036b29148d5809dc855:
Merge tag 'pull-nvme-20241001' of https://gitlab.com/birkelund/qemu into staging (2024-10-01 11:34:07 +0100)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241002
for you to fetch changes up to 74b493244d0624afed22606e76fc7fca62777401:
bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files (2024-10-02 15:11:52 +1000)
----------------------------------------------------------------
RISC-V PR for 9.2
* Add a property to set vl to ceil(AVL/2)
* Enable numamem testing for RISC-V
* Consider MISA bit choice in implied rule
* Fix the za64rs priv spec requirements
* Enable Bit Manip for OpenTitan Ibex CPU
* Fix the group bit setting of AIA with KVM
* Stop timer with infinite timecmp
* Add 'fcsr' register to QEMU log as a part of F extension
* Fix riscv64 build on musl libc
* Add preliminary textra trigger CSR functions
* RISC-V bsd-user support
* Respect firmware ELF entry point
* Add Svvptc extension support
* Fix masking of rv32 physical address
* Fix linking problem with semihosting disabled
* Fix IMSIC interrupt state updates
----------------------------------------------------------------
Alexandre Ghiti (1):
target: riscv: Add Svvptc extension support
Alistair Francis (1):
target: riscv: Enable Bit Manip for OpenTitan Ibex CPU
Alvin Chang (2):
target/riscv: Preliminary textra trigger CSR writting support
target/riscv: Add textra matching condition for the triggers
Andrew Jones (3):
target/riscv/kvm: Fix the group bit setting of AIA
target/riscv: Stop timer with infinite timecmp
target/riscv32: Fix masking of physical address
Daniel Henrique Barboza (1):
target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule
Haibo Xu (3):
tests/acpi: Add empty ACPI SRAT data file for RISC-V
tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V
tests/acpi: Add expected ACPI SRAT AML file for RISC-V
Jason Chien (1):
target/riscv: Add a property to set vl to ceil(AVL/2)
Maria Klauchek (1):
target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension
Mark Corbin (15):
bsd-user: Implement RISC-V CPU initialization and main loop
bsd-user: Add RISC-V CPU execution loop and syscall handling
bsd-user: Implement RISC-V CPU register cloning and reset functions
bsd-user: Implement RISC-V TLS register setup
bsd-user: Add RISC-V ELF definitions and hardware capability detection
bsd-user: Define RISC-V register structures and register copying
bsd-user: Add RISC-V signal trampoline setup function
bsd-user: Implement RISC-V sysarch system call emulation
bsd-user: Add RISC-V thread setup and initialization support
bsd-user: Define RISC-V VM parameters and helper functions
bsd-user: Define RISC-V system call structures and constants
bsd-user: Define RISC-V signal handling structures and constants
bsd-user: Implement RISC-V signal trampoline setup functions
bsd-user: Implement 'get_mcontext' for RISC-V
bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV
Milan P. Stanić (1):
util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc
Samuel Holland (1):
hw/riscv: Respect firmware ELF entry point
Thomas Huth (1):
target/riscv/cpu_helper: Fix linking problem with semihosting disabled
Tomasz Jeznach (1):
hw/intc: riscv-imsic: Fix interrupt state updates.
Vladimir Isaev (1):
target/riscv: fix za64rs enabling
Warner Losh (2):
bsd-user: Add generic RISC-V64 target definitions
bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files
configs/targets/riscv64-bsd-user.mak | 4 +
bsd-user/riscv/target.h | 20 ++++
bsd-user/riscv/target_arch.h | 27 +++++
bsd-user/riscv/target_arch_cpu.h | 148 ++++++++++++++++++++++++++
bsd-user/riscv/target_arch_elf.h | 42 ++++++++
bsd-user/riscv/target_arch_reg.h | 88 ++++++++++++++++
bsd-user/riscv/target_arch_signal.h | 75 +++++++++++++
bsd-user/riscv/target_arch_sigtramp.h | 41 +++++++
bsd-user/riscv/target_arch_sysarch.h | 41 +++++++
bsd-user/riscv/target_arch_thread.h | 47 +++++++++
bsd-user/riscv/target_arch_vmparam.h | 53 ++++++++++
bsd-user/riscv/target_syscall.h | 38 +++++++
include/hw/riscv/boot.h | 4 +-
target/riscv/cpu_bits.h | 10 ++
target/riscv/cpu_cfg.h | 2 +
target/riscv/debug.h | 3 +
bsd-user/riscv/signal.c | 170 ++++++++++++++++++++++++++++++
bsd-user/riscv/target_arch_cpu.c | 29 +++++
hw/intc/riscv_imsic.c | 50 +++++----
hw/riscv/boot.c | 11 +-
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/opentitan.c | 3 +-
hw/riscv/shakti_c.c | 13 ++-
hw/riscv/sifive_u.c | 4 +-
hw/riscv/spike.c | 5 +-
hw/riscv/virt.c | 4 +-
target/riscv/cpu.c | 16 ++-
target/riscv/cpu_helper.c | 8 +-
target/riscv/debug.c | 114 ++++++++++++++++++--
target/riscv/kvm/kvm-cpu.c | 4 +-
target/riscv/tcg/tcg-cpu.c | 13 ++-
target/riscv/time_helper.c | 1 +
target/riscv/vector_helper.c | 2 +
tests/qtest/bios-tables-test.c | 28 +++++
util/cpuinfo-riscv.c | 1 +
target/riscv/Kconfig | 4 +-
tests/data/acpi/riscv64/virt/SRAT.numamem | Bin 0 -> 108 bytes
37 files changed, 1068 insertions(+), 57 deletions(-)
create mode 100644 configs/targets/riscv64-bsd-user.mak
create mode 100644 bsd-user/riscv/target.h
create mode 100644 bsd-user/riscv/target_arch.h
create mode 100644 bsd-user/riscv/target_arch_cpu.h
create mode 100644 bsd-user/riscv/target_arch_elf.h
create mode 100644 bsd-user/riscv/target_arch_reg.h
create mode 100644 bsd-user/riscv/target_arch_signal.h
create mode 100644 bsd-user/riscv/target_arch_sigtramp.h
create mode 100644 bsd-user/riscv/target_arch_sysarch.h
create mode 100644 bsd-user/riscv/target_arch_thread.h
create mode 100644 bsd-user/riscv/target_arch_vmparam.h
create mode 100644 bsd-user/riscv/target_syscall.h
create mode 100644 bsd-user/riscv/signal.c
create mode 100644 bsd-user/riscv/target_arch_cpu.c
create mode 100644 tests/data/acpi/riscv64/virt/SRAT.numamem
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PULL v3 01/35] target/riscv: Add a property to set vl to ceil(AVL/2)
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 02/35] tests/acpi: Add empty ACPI SRAT data file for RISC-V Alistair Francis
` (34 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Jason Chien, Frank Chang, Alistair Francis
From: Jason Chien <jason.chien@sifive.com>
RVV spec allows implementations to set vl with values within
[ceil(AVL/2),VLMAX] when VLMAX < AVL < 2*VLMAX. This commit adds a
property "rvv_vl_half_avl" to enable setting vl = ceil(AVL/2). This
behavior helps identify compiler issues and bugs.
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20240722175004.23666-1-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu.c | 1 +
target/riscv/vector_helper.c | 2 ++
3 files changed, 4 insertions(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 8b272fb826..96fe26d4ea 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -127,6 +127,7 @@ struct RISCVCPUConfig {
bool ext_smepmp;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
+ bool rvv_vl_half_avl;
uint32_t mvendorid;
uint64_t marchid;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4bda754b01..cc5552500a 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2661,6 +2661,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
+ DEFINE_PROP_BOOL("rvv_vl_half_avl", RISCVCPU, cfg.rvv_vl_half_avl, false),
/*
* write_misa() is marked as experimental for now so mark
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 10a52ceb5b..072bd444b1 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -75,6 +75,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);
if (s1 <= vlmax) {
vl = s1;
+ } else if (s1 < 2 * vlmax && cpu->cfg.rvv_vl_half_avl) {
+ vl = (s1 + 1) >> 1;
} else {
vl = vlmax;
}
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 02/35] tests/acpi: Add empty ACPI SRAT data file for RISC-V
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
2024-10-02 5:50 ` [PULL v3 01/35] target/riscv: Add a property to set vl to ceil(AVL/2) Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 03/35] tests/qtest/bios-tables-test.c: Enable numamem testing " Alistair Francis
` (33 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Haibo Xu, Sunil V L, Alistair Francis
From: Haibo Xu <haibo1.xu@intel.com>
As per process documented (steps 1-3) in bios-tables-test.c, add
empty AML data file for RISC-V ACPI SRAT table and add the entry
in bios-tables-test-allowed-diff.h.
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <0e30216273f2f59916bc651350578d8e8bc3a75f.1723172696.git.haibo1.xu@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
tests/data/acpi/riscv64/virt/SRAT.numamem | 0
2 files changed, 1 insertion(+)
create mode 100644 tests/data/acpi/riscv64/virt/SRAT.numamem
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..a3e01d2eb7 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/riscv64/virt/SRAT.numamem",
diff --git a/tests/data/acpi/riscv64/virt/SRAT.numamem b/tests/data/acpi/riscv64/virt/SRAT.numamem
new file mode 100644
index 0000000000..e69de29bb2
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 03/35] tests/qtest/bios-tables-test.c: Enable numamem testing for RISC-V
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
2024-10-02 5:50 ` [PULL v3 01/35] target/riscv: Add a property to set vl to ceil(AVL/2) Alistair Francis
2024-10-02 5:50 ` [PULL v3 02/35] tests/acpi: Add empty ACPI SRAT data file for RISC-V Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 04/35] tests/acpi: Add expected ACPI SRAT AML file " Alistair Francis
` (32 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Haibo Xu, Sunil V L, Alistair Francis
From: Haibo Xu <haibo1.xu@intel.com>
Add ACPI SRAT table test case for RISC-V when NUMA was enabled.
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <a6f7e1a4b20ff7eb199e94ca0c8aa2e6794ce5b2.1723172696.git.haibo1.xu@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tests/qtest/bios-tables-test.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 36e5c0adde..e79f3a03df 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1706,6 +1706,32 @@ static void test_acpi_microvm_ioapic2_tcg(void)
free_test_data(&data);
}
+static void test_acpi_riscv64_virt_tcg_numamem(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .arch = "riscv64",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-riscv-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-riscv-vars.fd",
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.riscv64.iso.qcow2",
+ .ram_start = 0x80000000ULL,
+ .scan_len = 128ULL * 1024 * 1024,
+ };
+
+ data.variant = ".numamem";
+ /*
+ * RHCT will have ISA string encoded. To reduce the effort
+ * of updating expected AML file for any new default ISA extension,
+ * use the profile rva22s64.
+ */
+ test_acpi_one(" -cpu rva22s64"
+ " -object memory-backend-ram,id=ram0,size=128M"
+ " -numa node,memdev=ram0",
+ &data);
+ free_test_data(&data);
+}
+
static void test_acpi_aarch64_virt_tcg_numamem(void)
{
test_data data = {
@@ -2466,6 +2492,8 @@ int main(int argc, char *argv[])
} else if (strcmp(arch, "riscv64") == 0) {
if (has_tcg && qtest_has_device("virtio-blk-pci")) {
qtest_add_func("acpi/virt", test_acpi_riscv64_virt_tcg);
+ qtest_add_func("acpi/virt/numamem",
+ test_acpi_riscv64_virt_tcg_numamem);
}
}
ret = g_test_run();
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 04/35] tests/acpi: Add expected ACPI SRAT AML file for RISC-V
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (2 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 03/35] tests/qtest/bios-tables-test.c: Enable numamem testing " Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 05/35] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule Alistair Francis
` (31 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Haibo Xu, Sunil V L, Alistair Francis
From: Haibo Xu <haibo1.xu@intel.com>
As per the step 5 in the process documented in bios-tables-test.c,
generate the expected ACPI SRAT AML data file for RISC-V using the
rebuild-expected-aml.sh script and update the
bios-tables-test-allowed-diff.h.
This is a new file being added for the first time. Hence, iASL diff
output is not added.
Signed-off-by: Haibo Xu <haibo1.xu@intel.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <a667480203b35508038176c8ce4722370294cc57.1723172696.git.haibo1.xu@intel.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
tests/data/acpi/riscv64/virt/SRAT.numamem | Bin 0 -> 108 bytes
2 files changed, 1 deletion(-)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index a3e01d2eb7..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/riscv64/virt/SRAT.numamem",
diff --git a/tests/data/acpi/riscv64/virt/SRAT.numamem b/tests/data/acpi/riscv64/virt/SRAT.numamem
index e69de29bb2..2b6467364b 100644
Binary files a/tests/data/acpi/riscv64/virt/SRAT.numamem and b/tests/data/acpi/riscv64/virt/SRAT.numamem differ
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 05/35] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (3 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 04/35] tests/acpi: Add expected ACPI SRAT AML file " Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 06/35] target/riscv: fix za64rs enabling Alistair Francis
` (30 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Daniel Henrique Barboza, Frank Chang,
Alistair Francis
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Gitlab issue [1] reports a misleading error when trying to run a 'rv64'
cpu with 'zfinx' and without 'f':
$ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false
qemu-system-riscv64: Zfinx cannot be supported together with F extension
The user explicitly disabled F and the error message mentions a conflict
with Zfinx and F.
The problem isn't the error reporting, but the logic used when applying
the implied ZFA rule that enables RVF unconditionally, without honoring
user choice (i.e. keep F disabled).
Change cpu_enable_implied_rule() to check if the user deliberately
disabled a MISA bit. In this case we shouldn't either re-enable the bit
nor apply any implied rules related to it.
After this change the error message now shows:
$ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false
qemu-system-riscv64: Zfa extension requires F extension
Disabling 'zfa':
$ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false,zfa=false
qemu-system-riscv64: D extension requires F extension
And finally after disabling 'd':
$ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false,zfa=false,d=false
(OpenSBI boots ...)
[1] https://gitlab.com/qemu-project/qemu/-/issues/2486
Cc: Frank Chang <frank.chang@sifive.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2486
Fixes: 047da861f9 ("target/riscv: Introduce extension implied rule helpers")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240824173338.316666-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index b8814ab753..dea8ab7a43 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -778,11 +778,18 @@ static void cpu_enable_implied_rule(RISCVCPU *cpu,
if (!enabled) {
/* Enable the implied MISAs. */
if (rule->implied_misa_exts) {
- riscv_cpu_set_misa_ext(env,
- env->misa_ext | rule->implied_misa_exts);
-
for (i = 0; misa_bits[i] != 0; i++) {
if (rule->implied_misa_exts & misa_bits[i]) {
+ /*
+ * If the user disabled the misa_bit do not re-enable it
+ * and do not apply any implied rules related to it.
+ */
+ if (cpu_misa_ext_is_user_set(misa_bits[i]) &&
+ !(env->misa_ext & misa_bits[i])) {
+ continue;
+ }
+
+ riscv_cpu_set_misa_ext(env, env->misa_ext | misa_bits[i]);
ir = g_hash_table_lookup(misa_ext_implied_rules,
GUINT_TO_POINTER(misa_bits[i]));
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 06/35] target/riscv: fix za64rs enabling
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (4 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 05/35] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 07/35] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU Alistair Francis
` (29 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Vladimir Isaev, Alistair Francis,
Daniel Henrique Barboza
From: Vladimir Isaev <vladimir.isaev@syntacore.com>
za64rs requires priv 1.12 when enabled by priv 1.11.
This fixes annoying warning:
warning: disabling za64rs extension for hart 0x00000000 because privilege spec version does not match
on priv 1.11 CPUs.
Fixes: 68c9e54beae8 ("target/riscv: do not enable all named features by default")
Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240823063431.17474-1-vladimir.isaev@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cc5552500a..0f8189bcf0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -115,7 +115,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
ISA_EXT_DATA_ENTRY(zimop, PRIV_VERSION_1_13_0, ext_zimop),
ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
- ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_11),
+ ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_13_0, ext_zabha),
ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 07/35] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (5 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 06/35] target/riscv: fix za64rs enabling Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 08/35] target/riscv/kvm: Fix the group bit setting of AIA Alistair Francis
` (28 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Alistair Francis, Daniel Henrique Barboza
From: Alistair Francis <alistair23@gmail.com>
The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc
and Zbs bit-manipulation sub-extensions ratified in
v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable
them in QEMU as well.
1: https://github.com/lowRISC/opentitan/pull/9748
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240823003231.3522113-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0f8189bcf0..a1ca12077f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -680,6 +680,11 @@ static void rv32_ibex_cpu_init(Object *obj)
cpu->cfg.ext_zicsr = true;
cpu->cfg.pmp = true;
cpu->cfg.ext_smepmp = true;
+
+ cpu->cfg.ext_zba = true;
+ cpu->cfg.ext_zbb = true;
+ cpu->cfg.ext_zbc = true;
+ cpu->cfg.ext_zbs = true;
}
static void rv32_imafcu_nommu_cpu_init(Object *obj)
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 08/35] target/riscv/kvm: Fix the group bit setting of AIA
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (6 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 07/35] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 09/35] target/riscv: Stop timer with infinite timecmp Alistair Francis
` (27 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Andrew Jones, Daniel Henrique Barboza,
Alistair Francis
From: Andrew Jones <ajones@ventanamicro.com>
Just as the hart bit setting of the AIA should be calculated as
ceil(log2(max_hart_id + 1)) the group bit setting should be
calculated as ceil(log2(max_group_id + 1)). The hart bits are
implemented by passing max_hart_id to find_last_bit() and adding
one to the result. Do the same for the group bit setting.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240821075040.498945-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/kvm/kvm-cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index f6e3156b8d..341af901c5 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -1695,6 +1695,7 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
uint64_t max_hart_per_socket = 0;
uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr;
uint64_t socket_bits, hart_bits, guest_bits;
+ uint64_t max_group_id;
aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false);
@@ -1742,7 +1743,8 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
if (socket_count > 1) {
- socket_bits = find_last_bit(&socket_count, BITS_PER_LONG) + 1;
+ max_group_id = socket_count - 1;
+ socket_bits = find_last_bit(&max_group_id, BITS_PER_LONG) + 1;
ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS,
&socket_bits, true, NULL);
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 09/35] target/riscv: Stop timer with infinite timecmp
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (7 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 08/35] target/riscv/kvm: Fix the group bit setting of AIA Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 10/35] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension Alistair Francis
` (26 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Andrew Jones, Alistair Francis
From: Andrew Jones <ajones@ventanamicro.com>
While the spec doesn't state it, setting timecmp to UINT64_MAX is
another way to stop a timer, as it's considered setting the next
timer event to occur at infinity. And, even if the time CSR does
eventually reach UINT64_MAX, the very next tick will bring it back to
zero, once again less than timecmp. For this reason
riscv_timer_write_timecmp() special cases UINT64_MAX. However, if a
previously set timecmp has not yet expired, then setting timecmp to
UINT64_MAX to disable / stop it would not work, as the special case
left the previous QEMU timer active, which would then still deliver
an interrupt at that previous timecmp time. Ensure the stopped timer
will not still deliver an interrupt by also deleting the QEMU timer
in the UINT64_MAX special case.
Fixes: ae0edf2188b3 ("target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240829084002.1805006-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/time_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
index 8d245bed3a..bc0d9a0c4c 100644
--- a/target/riscv/time_helper.c
+++ b/target/riscv/time_helper.c
@@ -92,6 +92,7 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
* equals UINT64_MAX.
*/
if (timecmp == UINT64_MAX) {
+ timer_del(timer);
return;
}
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 10/35] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (8 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 09/35] target/riscv: Stop timer with infinite timecmp Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 11/35] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc Alistair Francis
` (25 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Maria Klauchek, Daniel Henrique Barboza,
Alistair Francis
From: Maria Klauchek <m.klauchek@syntacore.com>
FCSR is a part of F extension. Print it to log if FPU option is enabled.
Signed-off-by: Maria Klauchek <m.klauchek@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240902103433.18424-1-m.klauchek@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a1ca12077f..89bc3955ee 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -823,6 +823,12 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
if (flags & CPU_DUMP_FPU) {
+ target_ulong val = 0;
+ RISCVException res = riscv_csrrw_debug(env, CSR_FCSR, &val, 0, 0);
+ if (res == RISCV_EXCP_NONE) {
+ qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
+ csr_ops[CSR_FCSR].name, val);
+ }
for (i = 0; i < 32; i++) {
qemu_fprintf(f, " %-8s %016" PRIx64,
riscv_fpr_regnames[i], env->fpr[i]);
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 11/35] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (9 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 10/35] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 12/35] target/riscv: Preliminary textra trigger CSR writting support Alistair Francis
` (24 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Milan P. Stanić, Alistair Francis
From: Milan P. Stanić <mps@arvanta.net>
build fails on musl libc (alpine linux) with this error:
../util/cpuinfo-riscv.c: In function 'cpuinfo_init':
../util/cpuinfo-riscv.c:63:21: error: '__NR_riscv_hwprobe' undeclared (first use in this function); did you mean 'riscv_hwprobe'?
63 | if (syscall(__NR_riscv_hwprobe, &pair, 1, 0, NULL, 0) == 0
| ^~~~~~~~~~~~~~~~~~
| riscv_hwprobe
../util/cpuinfo-riscv.c:63:21: note: each undeclared identifier is reported only once for each function it appears in
ninja: subcommand failed
add '#include "asm/unistd.h"' to util/cpuinfo-riscv.c fixes build
Signed-off-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240905150702.2484-1-mps@arvanta.net>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
util/cpuinfo-riscv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/util/cpuinfo-riscv.c b/util/cpuinfo-riscv.c
index 497ce12680..8cacc67645 100644
--- a/util/cpuinfo-riscv.c
+++ b/util/cpuinfo-riscv.c
@@ -9,6 +9,7 @@
#ifdef CONFIG_ASM_HWPROBE_H
#include <asm/hwprobe.h>
#include <sys/syscall.h>
+#include <asm/unistd.h>
#endif
unsigned cpuinfo;
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 12/35] target/riscv: Preliminary textra trigger CSR writting support
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (10 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 11/35] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 13/35] target/riscv: Add textra matching condition for the triggers Alistair Francis
` (23 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Alvin Chang, Alistair Francis
From: Alvin Chang <alvinga@andestech.com>
This commit allows program to write textra trigger CSR for type 2, 3, 6
triggers. In this preliminary patch, the textra.MHVALUE and the
textra.MHSELECT fields are allowed to be configured. Other fields, such
as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to
zero for now.
For textra.MHSELECT field, the only legal values are 0 (ignore) and 4
(mcontext). Writing 1~3 into textra.MHSELECT will be changed to 0, and
writing 5~7 into textra.MHSELECT will be changed to 4. This behavior is
aligned to RISC-V SPIKE simulator.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240826024657.262553-2-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 10 ++++++
target/riscv/debug.c | 69 +++++++++++++++++++++++++++++++++++++----
2 files changed, 73 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 32b068f18a..7e3f629356 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -947,6 +947,16 @@ typedef enum RISCVException {
#define JVT_BASE (~0x3F)
/* Debug Sdtrig CSR masks */
+#define TEXTRA32_MHVALUE 0xFC000000
+#define TEXTRA32_MHSELECT 0x03800000
+#define TEXTRA32_SBYTEMASK 0x000C0000
+#define TEXTRA32_SVALUE 0x0003FFFC
+#define TEXTRA32_SSELECT 0x00000003
+#define TEXTRA64_MHVALUE 0xFFF8000000000000ULL
+#define TEXTRA64_MHSELECT 0x0007000000000000ULL
+#define TEXTRA64_SBYTEMASK 0x000000F000000000ULL
+#define TEXTRA64_SVALUE 0x00000003FFFFFFFCULL
+#define TEXTRA64_SSELECT 0x0000000000000003ULL
#define MCONTEXT32 0x0000003F
#define MCONTEXT64 0x0000000000001FFFULL
#define MCONTEXT32_HCONTEXT 0x0000007F
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 0b5099ff9a..d6b4a06144 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -217,6 +217,66 @@ static inline void warn_always_zero_bit(target_ulong val, target_ulong mask,
}
}
+static target_ulong textra_validate(CPURISCVState *env, target_ulong tdata3)
+{
+ target_ulong mhvalue, mhselect;
+ target_ulong mhselect_new;
+ target_ulong textra;
+ const uint32_t mhselect_no_rvh[8] = { 0, 0, 0, 0, 4, 4, 4, 4 };
+
+ switch (riscv_cpu_mxl(env)) {
+ case MXL_RV32:
+ mhvalue = get_field(tdata3, TEXTRA32_MHVALUE);
+ mhselect = get_field(tdata3, TEXTRA32_MHSELECT);
+ /* Validate unimplemented (always zero) bits */
+ warn_always_zero_bit(tdata3, (target_ulong)TEXTRA32_SBYTEMASK,
+ "sbytemask");
+ warn_always_zero_bit(tdata3, (target_ulong)TEXTRA32_SVALUE,
+ "svalue");
+ warn_always_zero_bit(tdata3, (target_ulong)TEXTRA32_SSELECT,
+ "sselect");
+ break;
+ case MXL_RV64:
+ case MXL_RV128:
+ mhvalue = get_field(tdata3, TEXTRA64_MHVALUE);
+ mhselect = get_field(tdata3, TEXTRA64_MHSELECT);
+ /* Validate unimplemented (always zero) bits */
+ warn_always_zero_bit(tdata3, (target_ulong)TEXTRA64_SBYTEMASK,
+ "sbytemask");
+ warn_always_zero_bit(tdata3, (target_ulong)TEXTRA64_SVALUE,
+ "svalue");
+ warn_always_zero_bit(tdata3, (target_ulong)TEXTRA64_SSELECT,
+ "sselect");
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ /* Validate mhselect. */
+ mhselect_new = mhselect_no_rvh[mhselect];
+ if (mhselect != mhselect_new) {
+ qemu_log_mask(LOG_UNIMP, "mhselect only supports 0 or 4 for now\n");
+ }
+
+ /* Write legal values into textra */
+ textra = 0;
+ switch (riscv_cpu_mxl(env)) {
+ case MXL_RV32:
+ textra = set_field(textra, TEXTRA32_MHVALUE, mhvalue);
+ textra = set_field(textra, TEXTRA32_MHSELECT, mhselect_new);
+ break;
+ case MXL_RV64:
+ case MXL_RV128:
+ textra = set_field(textra, TEXTRA64_MHVALUE, mhvalue);
+ textra = set_field(textra, TEXTRA64_MHSELECT, mhselect_new);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ return textra;
+}
+
static void do_trigger_action(CPURISCVState *env, target_ulong trigger_index)
{
trigger_action_t action = get_trigger_action(env, trigger_index);
@@ -441,8 +501,7 @@ static void type2_reg_write(CPURISCVState *env, target_ulong index,
}
break;
case TDATA3:
- qemu_log_mask(LOG_UNIMP,
- "tdata3 is not supported for type 2 trigger\n");
+ env->tdata3[index] = textra_validate(env, val);
break;
default:
g_assert_not_reached();
@@ -558,8 +617,7 @@ static void type6_reg_write(CPURISCVState *env, target_ulong index,
}
break;
case TDATA3:
- qemu_log_mask(LOG_UNIMP,
- "tdata3 is not supported for type 6 trigger\n");
+ env->tdata3[index] = textra_validate(env, val);
break;
default:
g_assert_not_reached();
@@ -741,8 +799,7 @@ static void itrigger_reg_write(CPURISCVState *env, target_ulong index,
"tdata2 is not supported for icount trigger\n");
break;
case TDATA3:
- qemu_log_mask(LOG_UNIMP,
- "tdata3 is not supported for icount trigger\n");
+ env->tdata3[index] = textra_validate(env, val);
break;
default:
g_assert_not_reached();
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 13/35] target/riscv: Add textra matching condition for the triggers
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (11 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 12/35] target/riscv: Preliminary textra trigger CSR writting support Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 14/35] hw/riscv: Respect firmware ELF entry point Alistair Francis
` (22 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Alvin Chang, Alistair Francis
From: Alvin Chang <alvinga@andestech.com>
According to RISC-V Debug specification, the optional textra32 and
textra64 trigger CSRs can be used to configure additional matching
conditions for the triggers. For example, if the textra.MHSELECT field
is set to 4 (mcontext), this trigger will only match or fire if the low
bits of mcontext/hcontext equal textra.MHVALUE field.
This commit adds the aforementioned matching condition as common trigger
matching conditions. Currently, the only legal values of textra.MHSELECT
are 0 (ignore) and 4 (mcontext). When textra.MHSELECT is 0, we pass the
checking. When textra.MHSELECT is 4, we compare textra.MHVALUE with
mcontext CSR. The remaining fields, such as textra.SBYTEMASK,
textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus,
we skip checking them here.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240826024657.262553-3-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/debug.h | 3 +++
target/riscv/debug.c | 45 +++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index c347863578..f76b8f944a 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -131,6 +131,9 @@ enum {
#define ITRIGGER_VU BIT(25)
#define ITRIGGER_VS BIT(26)
+#define MHSELECT_IGNORE 0
+#define MHSELECT_MCONTEXT 4
+
bool tdata_available(CPURISCVState *env, int tdata_index);
target_ulong tselect_csr_read(CPURISCVState *env);
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index d6b4a06144..c79b51af30 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -364,11 +364,54 @@ static bool trigger_priv_match(CPURISCVState *env, trigger_type_t type,
return false;
}
+static bool trigger_textra_match(CPURISCVState *env, trigger_type_t type,
+ int trigger_index)
+{
+ target_ulong textra = env->tdata3[trigger_index];
+ target_ulong mhvalue, mhselect;
+
+ if (type < TRIGGER_TYPE_AD_MATCH || type > TRIGGER_TYPE_AD_MATCH6) {
+ /* textra checking is only applicable when type is 2, 3, 4, 5, or 6 */
+ return true;
+ }
+
+ switch (riscv_cpu_mxl(env)) {
+ case MXL_RV32:
+ mhvalue = get_field(textra, TEXTRA32_MHVALUE);
+ mhselect = get_field(textra, TEXTRA32_MHSELECT);
+ break;
+ case MXL_RV64:
+ case MXL_RV128:
+ mhvalue = get_field(textra, TEXTRA64_MHVALUE);
+ mhselect = get_field(textra, TEXTRA64_MHSELECT);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ /* Check mhvalue and mhselect. */
+ switch (mhselect) {
+ case MHSELECT_IGNORE:
+ break;
+ case MHSELECT_MCONTEXT:
+ /* Match if the low bits of mcontext/hcontext equal mhvalue. */
+ if (mhvalue != env->mcontext) {
+ return false;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return true;
+}
+
/* Common matching conditions for all types of the triggers. */
static bool trigger_common_match(CPURISCVState *env, trigger_type_t type,
int trigger_index)
{
- return trigger_priv_match(env, type, trigger_index);
+ return trigger_priv_match(env, type, trigger_index) &&
+ trigger_textra_match(env, type, trigger_index);
}
/* type 2 trigger */
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 14/35] hw/riscv: Respect firmware ELF entry point
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (12 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 13/35] target/riscv: Add textra matching condition for the triggers Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 15/35] target: riscv: Add Svvptc extension support Alistair Francis
` (21 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Samuel Holland, Alistair Francis
From: Samuel Holland <samuel.holland@sifive.com>
When riscv_load_firmware() loads an ELF, the ELF segment addresses are
used, not the passed-in firmware_load_addr. The machine models assume
the firmware entry point is what they provided for firmware_load_addr,
and use that address to generate the boot ROM, so if the ELF is linked
at any other address, the boot ROM will jump to empty memory.
Pass back the ELF entry point to use when generating the boot ROM, so
the boot ROM can jump to firmware loaded anywhere in RAM. For example,
on the virt machine, this allows using an OpenSBI fw_dynamic.elf built
with FW_TEXT_START values other than 0x80000000.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240817002651.3209701-1-samuel.holland@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/boot.h | 4 ++--
hw/riscv/boot.c | 11 ++++++-----
hw/riscv/microchip_pfsoc.c | 2 +-
hw/riscv/opentitan.c | 3 ++-
hw/riscv/shakti_c.c | 13 ++++++-------
hw/riscv/sifive_u.c | 4 ++--
hw/riscv/spike.c | 5 +++--
hw/riscv/virt.c | 4 ++--
8 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index a2e4ae9cb0..18bfe9f7bf 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -35,13 +35,13 @@ target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
target_ulong firmware_end_addr);
target_ulong riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
- hwaddr firmware_load_addr,
+ hwaddr *firmware_load_addr,
symbol_fn_t sym_cb);
const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
char *riscv_find_firmware(const char *firmware_filename,
const char *default_machine_firmware);
target_ulong riscv_load_firmware(const char *firmware_filename,
- hwaddr firmware_load_addr,
+ hwaddr *firmware_load_addr,
symbol_fn_t sym_cb);
target_ulong riscv_load_kernel(MachineState *machine,
RISCVHartArrayState *harts,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 47281ca853..9115ecd91f 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -128,11 +128,11 @@ char *riscv_find_firmware(const char *firmware_filename,
target_ulong riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
- hwaddr firmware_load_addr,
+ hwaddr *firmware_load_addr,
symbol_fn_t sym_cb)
{
char *firmware_filename;
- target_ulong firmware_end_addr = firmware_load_addr;
+ target_ulong firmware_end_addr = *firmware_load_addr;
firmware_filename = riscv_find_firmware(machine->firmware,
default_machine_firmware);
@@ -148,7 +148,7 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
}
target_ulong riscv_load_firmware(const char *firmware_filename,
- hwaddr firmware_load_addr,
+ hwaddr *firmware_load_addr,
symbol_fn_t sym_cb)
{
uint64_t firmware_entry, firmware_end;
@@ -159,15 +159,16 @@ target_ulong riscv_load_firmware(const char *firmware_filename,
if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
&firmware_entry, NULL, &firmware_end, NULL,
0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
+ *firmware_load_addr = firmware_entry;
return firmware_end;
}
firmware_size = load_image_targphys_as(firmware_filename,
- firmware_load_addr,
+ *firmware_load_addr,
current_machine->ram_size, NULL);
if (firmware_size > 0) {
- return firmware_load_addr + firmware_size;
+ return *firmware_load_addr + firmware_size;
}
error_report("could not load firmware '%s'", firmware_filename);
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 7725dfbde5..f9a3b43d2e 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -613,7 +613,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
/* Load the firmware */
firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
- firmware_load_addr, NULL);
+ &firmware_load_addr, NULL);
if (kernel_as_payload) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 436503f1ba..e2830e9dc2 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -98,7 +98,8 @@ static void opentitan_machine_init(MachineState *machine)
memmap[IBEX_DEV_RAM].base, machine->ram);
if (machine->firmware) {
- riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
+ hwaddr firmware_load_addr = memmap[IBEX_DEV_RAM].base;
+ riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL);
}
if (machine->kernel_filename) {
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 3888034c2b..2dccc1eff2 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -45,6 +45,7 @@ static void shakti_c_machine_state_init(MachineState *mstate)
{
ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
MemoryRegion *system_memory = get_system_memory();
+ hwaddr firmware_load_addr = shakti_c_memmap[SHAKTI_C_RAM].base;
/* Initialize SoC */
object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
@@ -56,16 +57,14 @@ static void shakti_c_machine_state_init(MachineState *mstate)
shakti_c_memmap[SHAKTI_C_RAM].base,
mstate->ram);
+ if (mstate->firmware) {
+ riscv_load_firmware(mstate->firmware, &firmware_load_addr, NULL);
+ }
+
/* ROM reset vector */
- riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
- shakti_c_memmap[SHAKTI_C_RAM].base,
+ riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus, firmware_load_addr,
shakti_c_memmap[SHAKTI_C_ROM].base,
shakti_c_memmap[SHAKTI_C_ROM].size, 0, 0);
- if (mstate->firmware) {
- riscv_load_firmware(mstate->firmware,
- shakti_c_memmap[SHAKTI_C_RAM].base,
- NULL);
- }
}
static void shakti_c_machine_instance_init(Object *obj)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index af5f923f54..35a689309d 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -515,7 +515,7 @@ static void sifive_u_machine_init(MachineState *machine)
SiFiveUState *s = RISCV_U_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
- target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
+ hwaddr start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
target_ulong firmware_end_addr, kernel_start_addr;
const char *firmware_name;
uint32_t start_addr_hi32 = 0x00000000;
@@ -589,7 +589,7 @@ static void sifive_u_machine_init(MachineState *machine)
firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
- start_addr, NULL);
+ &start_addr, NULL);
if (machine->kernel_filename) {
kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 64074395bc..fceb91d946 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -198,6 +198,7 @@ static void spike_board_init(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base;
+ hwaddr firmware_load_addr = memmap[SPIKE_DRAM].base;
target_ulong kernel_start_addr;
char *firmware_name;
uint32_t fdt_load_addr;
@@ -290,7 +291,7 @@ static void spike_board_init(MachineState *machine)
/* Load firmware */
if (firmware_name) {
firmware_end_addr = riscv_load_firmware(firmware_name,
- memmap[SPIKE_DRAM].base,
+ &firmware_load_addr,
htif_symbol_callback);
g_free(firmware_name);
}
@@ -320,7 +321,7 @@ static void spike_board_init(MachineState *machine)
riscv_load_fdt(fdt_load_addr, machine->fdt);
/* load the reset vector */
- riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base,
+ riscv_setup_rom_reset_vec(machine, &s->soc[0], firmware_load_addr,
memmap[SPIKE_MROM].base,
memmap[SPIKE_MROM].size, kernel_entry,
fdt_load_addr);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index cef41c150a..3c0dca86f1 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1335,7 +1335,7 @@ static void virt_machine_done(Notifier *notifier, void *data)
machine_done);
const MemMapEntry *memmap = virt_memmap;
MachineState *machine = MACHINE(s);
- target_ulong start_addr = memmap[VIRT_DRAM].base;
+ hwaddr start_addr = memmap[VIRT_DRAM].base;
target_ulong firmware_end_addr, kernel_start_addr;
const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
uint64_t fdt_load_addr;
@@ -1367,7 +1367,7 @@ static void virt_machine_done(Notifier *notifier, void *data)
}
firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
- start_addr, NULL);
+ &start_addr, NULL);
pflash_blk0 = pflash_cfi01_get_blk(s->flash[0]);
if (pflash_blk0) {
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 15/35] target: riscv: Add Svvptc extension support
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (13 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 14/35] hw/riscv: Respect firmware ELF entry point Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 16/35] target/riscv32: Fix masking of physical address Alistair Francis
` (20 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Alexandre Ghiti, Alistair Francis
From: Alexandre Ghiti <alexghiti@rivosinc.com>
The Svvptc extension describes a uarch that does not cache invalid TLB
entries: that's the case for qemu so there is nothing particular to
implement other than the introduction of this extension.
Since qemu already exposes Svvptc behaviour, let's enable it by default
since it allows to drastically reduce the number of sfence.vma emitted
by S-mode.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240828083651.203861-1-alexghiti@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/cpu.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 96fe26d4ea..355afedfd3 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -81,6 +81,7 @@ struct RISCVCPUConfig {
bool ext_svinval;
bool ext_svnapot;
bool ext_svpbmt;
+ bool ext_svvptc;
bool ext_zdinx;
bool ext_zaamo;
bool ext_zacas;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 89bc3955ee..658bdb4ae1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -197,6 +197,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
@@ -1494,6 +1495,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
+ MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, true),
MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true),
MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true),
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 16/35] target/riscv32: Fix masking of physical address
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (14 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 15/35] target: riscv: Add Svvptc extension support Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 17/35] target/riscv/cpu_helper: Fix linking problem with semihosting disabled Alistair Francis
` (19 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Andrew Jones, Alistair Francis, Richard Henderson
From: Andrew Jones <ajones@ventanamicro.com>
C doesn't extend the sign bit for unsigned types since there isn't a
sign bit to extend. This means a promotion of a u32 to a u64 results
in the upper 32 bits of the u64 being zero. If that result is then
used as a mask on another u64 the upper 32 bits will be cleared. rv32
physical addresses may be up to 34 bits wide, so we don't want to
clear the high bits while page aligning the address. The fix is to
use hwaddr for the mask, which, even on rv32, is 64-bits wide.
Fixes: af3fc195e3c8 ("target/riscv: Change the TLB page size depends on PMP entries.")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240909083241.43836-2-ajones@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 395a1d9140..4b2c72780c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1323,7 +1323,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
int ret = TRANSLATE_FAIL;
int mode = mmuidx_priv(mmu_idx);
/* default TLB page size */
- target_ulong tlb_size = TARGET_PAGE_SIZE;
+ hwaddr tlb_size = TARGET_PAGE_SIZE;
env->guest_phys_fault_addr = 0;
@@ -1375,7 +1375,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU,
"%s PMP address=" HWADDR_FMT_plx " ret %d prot"
- " %d tlb_size " TARGET_FMT_lu "\n",
+ " %d tlb_size %" HWADDR_PRIu "\n",
__func__, pa, ret, prot_pmp, tlb_size);
prot &= prot_pmp;
@@ -1409,7 +1409,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU,
"%s PMP address=" HWADDR_FMT_plx " ret %d prot"
- " %d tlb_size " TARGET_FMT_lu "\n",
+ " %d tlb_size %" HWADDR_PRIu "\n",
__func__, pa, ret, prot_pmp, tlb_size);
prot &= prot_pmp;
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 17/35] target/riscv/cpu_helper: Fix linking problem with semihosting disabled
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (15 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 16/35] target/riscv32: Fix masking of physical address Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 18/35] hw/intc: riscv-imsic: Fix interrupt state updates Alistair Francis
` (18 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Thomas Huth, Alistair Francis
From: Thomas Huth <thuth@redhat.com>
If QEMU has been configured with "--without-default-devices", the build
is currently failing with:
/usr/bin/ld: libqemu-riscv32-softmmu.a.p/target_riscv_cpu_helper.c.o:
in function `riscv_cpu_do_interrupt':
.../qemu/target/riscv/cpu_helper.c:1678:(.text+0x2214): undefined
reference to `do_common_semihosting'
We always want semihosting to be enabled if TCG is available, so change
the "imply" statements in the Kconfig file to "select", and make sure to
avoid calling into do_common_semihosting() if TCG is not available.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240906094858.718105-1-thuth@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 2 ++
target/riscv/Kconfig | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 4b2c72780c..a935377b4a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1674,10 +1674,12 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (!async) {
/* set tval to badaddr for traps with address information */
switch (cause) {
+#ifdef CONFIG_TCG
case RISCV_EXCP_SEMIHOST:
do_common_semihosting(cs);
env->pc += 4;
return;
+#endif
case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
case RISCV_EXCP_LOAD_ADDR_MIS:
diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig
index c332616d36..11bc09b414 100644
--- a/target/riscv/Kconfig
+++ b/target/riscv/Kconfig
@@ -1,9 +1,9 @@
config RISCV32
bool
- imply ARM_COMPATIBLE_SEMIHOSTING if TCG
+ select ARM_COMPATIBLE_SEMIHOSTING if TCG
select DEVICE_TREE # needed by boot.c
config RISCV64
bool
- imply ARM_COMPATIBLE_SEMIHOSTING if TCG
+ select ARM_COMPATIBLE_SEMIHOSTING if TCG
select DEVICE_TREE # needed by boot.c
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 18/35] hw/intc: riscv-imsic: Fix interrupt state updates.
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (16 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 17/35] target/riscv/cpu_helper: Fix linking problem with semihosting disabled Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 19/35] bsd-user: Implement RISC-V CPU initialization and main loop Alistair Francis
` (17 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Tomasz Jeznach, Alistair Francis
From: Tomasz Jeznach <tjeznach@rivosinc.com>
The IMSIC state variable eistate[] is modified by CSR instructions
within a range dedicated to the local CPU and by MMIO writes from any CPU.
Access to eistate from MMIO accessors is protected by the BQL, but
read-modify-write (RMW) sequences from CSRRW do not acquire the BQL,
making the RMW sequence vulnerable to a race condition with MMIO access
from a remote CPU.
This race can manifest as missing IPI or MSI in multi-CPU systems, eg:
[ 43.008092] watchdog: BUG: soft lockup - CPU#2 stuck for 27s! [kworker/u19:1:52]
[ 43.011723] CPU: 2 UID: 0 PID: 52 Comm: kworker/u19:1 Not tainted 6.11.0-rc6
[ 43.013070] Workqueue: events_unbound deferred_probe_work_func
[ 43.018776] [<ffffffff800b4a86>] smp_call_function_many_cond+0x190/0x5c2
[ 43.019205] [<ffffffff800b4f28>] on_each_cpu_cond_mask+0x20/0x32
[ 43.019447] [<ffffffff8001069a>] __flush_tlb_range+0xf2/0x190
[ 43.019683] [<ffffffff80010914>] flush_tlb_kernel_range+0x20/0x28
The interrupt line raise/lower sequence was changed to prevent a race
between the evaluation of the eistate and the execution of the qemu_irq
raise/lower, ensuring that the interrupt line is not incorrectly
deactivated based on a stale topei check result. To avoid holding BQL
all modifications of eistate are converted to atomic operations.
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <a7604e4d61068ca4d384ae2a1377e1521d4d0235.1725651699.git.tjeznach@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/riscv_imsic.c | 50 +++++++++++++++++++++++++++----------------
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
index b90f0d731d..9ef65d4012 100644
--- a/hw/intc/riscv_imsic.c
+++ b/hw/intc/riscv_imsic.c
@@ -55,7 +55,7 @@ static uint32_t riscv_imsic_topei(RISCVIMSICState *imsic, uint32_t page)
(imsic->eithreshold[page] <= imsic->num_irqs)) ?
imsic->eithreshold[page] : imsic->num_irqs;
for (i = 1; i < max_irq; i++) {
- if ((imsic->eistate[base + i] & IMSIC_EISTATE_ENPEND) ==
+ if ((qatomic_read(&imsic->eistate[base + i]) & IMSIC_EISTATE_ENPEND) ==
IMSIC_EISTATE_ENPEND) {
return (i << IMSIC_TOPEI_IID_SHIFT) | i;
}
@@ -66,10 +66,24 @@ static uint32_t riscv_imsic_topei(RISCVIMSICState *imsic, uint32_t page)
static void riscv_imsic_update(RISCVIMSICState *imsic, uint32_t page)
{
+ uint32_t base = page * imsic->num_irqs;
+
+ /*
+ * Lower the interrupt line if necessary, then evaluate the current
+ * IMSIC state.
+ * This sequence ensures that any race between evaluating the eistate and
+ * updating the interrupt line will not result in an incorrectly
+ * deactivated connected CPU IRQ line.
+ * If multiple interrupts are pending, this sequence functions identically
+ * to qemu_irq_pulse.
+ */
+
+ if (qatomic_fetch_and(&imsic->eistate[base], ~IMSIC_EISTATE_ENPEND)) {
+ qemu_irq_lower(imsic->external_irqs[page]);
+ }
if (imsic->eidelivery[page] && riscv_imsic_topei(imsic, page)) {
qemu_irq_raise(imsic->external_irqs[page]);
- } else {
- qemu_irq_lower(imsic->external_irqs[page]);
+ qatomic_or(&imsic->eistate[base], IMSIC_EISTATE_ENPEND);
}
}
@@ -125,12 +139,11 @@ static int riscv_imsic_topei_rmw(RISCVIMSICState *imsic, uint32_t page,
topei >>= IMSIC_TOPEI_IID_SHIFT;
base = page * imsic->num_irqs;
if (topei) {
- imsic->eistate[base + topei] &= ~IMSIC_EISTATE_PENDING;
+ qatomic_and(&imsic->eistate[base + topei], ~IMSIC_EISTATE_PENDING);
}
-
- riscv_imsic_update(imsic, page);
}
+ riscv_imsic_update(imsic, page);
return 0;
}
@@ -139,7 +152,7 @@ static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic,
uint32_t num, bool pend, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
- uint32_t i, base;
+ uint32_t i, base, prev;
target_ulong mask;
uint32_t state = (pend) ? IMSIC_EISTATE_PENDING : IMSIC_EISTATE_ENABLED;
@@ -157,10 +170,6 @@ static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic,
if (val) {
*val = 0;
- for (i = 0; i < xlen; i++) {
- mask = (target_ulong)1 << i;
- *val |= (imsic->eistate[base + i] & state) ? mask : 0;
- }
}
for (i = 0; i < xlen; i++) {
@@ -172,10 +181,15 @@ static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic,
mask = (target_ulong)1 << i;
if (wr_mask & mask) {
if (new_val & mask) {
- imsic->eistate[base + i] |= state;
+ prev = qatomic_fetch_or(&imsic->eistate[base + i], state);
} else {
- imsic->eistate[base + i] &= ~state;
+ prev = qatomic_fetch_and(&imsic->eistate[base + i], ~state);
}
+ } else {
+ prev = qatomic_read(&imsic->eistate[base + i]);
+ }
+ if (val && (prev & state)) {
+ *val |= mask;
}
}
@@ -302,14 +316,14 @@ static void riscv_imsic_write(void *opaque, hwaddr addr, uint64_t value,
page = addr >> IMSIC_MMIO_PAGE_SHIFT;
if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) == IMSIC_MMIO_PAGE_LE) {
if (value && (value < imsic->num_irqs)) {
- imsic->eistate[(page * imsic->num_irqs) + value] |=
- IMSIC_EISTATE_PENDING;
+ qatomic_or(&imsic->eistate[(page * imsic->num_irqs) + value],
+ IMSIC_EISTATE_PENDING);
+
+ /* Update CPU external interrupt status */
+ riscv_imsic_update(imsic, page);
}
}
- /* Update CPU external interrupt status */
- riscv_imsic_update(imsic, page);
-
return;
err:
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 19/35] bsd-user: Implement RISC-V CPU initialization and main loop
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (17 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 18/35] hw/intc: riscv-imsic: Fix interrupt state updates Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 20/35] bsd-user: Add RISC-V CPU execution loop and syscall handling Alistair Francis
` (16 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Jessica Clarke,
Richard Henderson, Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Added the initial implementation for RISC-V CPU initialization and main
loop. This includes setting up the general-purpose registers and
program counter based on the provided target architecture definitions.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-2-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target_arch_cpu.h | 40 ++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_cpu.h
diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h
new file mode 100644
index 0000000000..f8d85e01ad
--- /dev/null
+++ b/bsd-user/riscv/target_arch_cpu.h
@@ -0,0 +1,40 @@
+/*
+ * RISC-V CPU init and loop
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_CPU_H
+#define TARGET_ARCH_CPU_H
+
+#include "target_arch.h"
+#include "signal-common.h"
+
+#define TARGET_DEFAULT_CPU_MODEL "max"
+
+static inline void target_cpu_init(CPURISCVState *env,
+ struct target_pt_regs *regs)
+{
+ int i;
+
+ for (i = 1; i < 32; i++) {
+ env->gpr[i] = regs->regs[i];
+ }
+
+ env->pc = regs->sepc;
+}
+
+#endif /* TARGET_ARCH_CPU_H */
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 20/35] bsd-user: Add RISC-V CPU execution loop and syscall handling
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (18 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 19/35] bsd-user: Implement RISC-V CPU initialization and main loop Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 21/35] bsd-user: Implement RISC-V CPU register cloning and reset functions Alistair Francis
` (15 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Jessica Clarke, Kyle Evans,
Richard Henderson, Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Implemented the RISC-V CPU execution loop, including handling various
exceptions and system calls. The loop continuously executes CPU
instructions,processes exceptions, and handles system calls by invoking
FreeBSD syscall handlers.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-3-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target_arch_cpu.h | 94 ++++++++++++++++++++++++++++++++
1 file changed, 94 insertions(+)
diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h
index f8d85e01ad..9c31d9dc4c 100644
--- a/bsd-user/riscv/target_arch_cpu.h
+++ b/bsd-user/riscv/target_arch_cpu.h
@@ -37,4 +37,98 @@ static inline void target_cpu_init(CPURISCVState *env,
env->pc = regs->sepc;
}
+static inline void target_cpu_loop(CPURISCVState *env)
+{
+ CPUState *cs = env_cpu(env);
+ int trapnr;
+ abi_long ret;
+ unsigned int syscall_num;
+ int32_t signo, code;
+
+ for (;;) {
+ cpu_exec_start(cs);
+ trapnr = cpu_exec(cs);
+ cpu_exec_end(cs);
+ process_queued_cpu_work(cs);
+
+ signo = 0;
+
+ switch (trapnr) {
+ case EXCP_INTERRUPT:
+ /* just indicate that signals should be handled asap */
+ break;
+ case EXCP_ATOMIC:
+ cpu_exec_step_atomic(cs);
+ break;
+ case RISCV_EXCP_U_ECALL:
+ syscall_num = env->gpr[xT0];
+ env->pc += TARGET_INSN_SIZE;
+ /* Compare to cpu_fetch_syscall_args() in riscv/riscv/trap.c */
+ if (TARGET_FREEBSD_NR___syscall == syscall_num ||
+ TARGET_FREEBSD_NR_syscall == syscall_num) {
+ ret = do_freebsd_syscall(env,
+ env->gpr[xA0],
+ env->gpr[xA1],
+ env->gpr[xA2],
+ env->gpr[xA3],
+ env->gpr[xA4],
+ env->gpr[xA5],
+ env->gpr[xA6],
+ env->gpr[xA7],
+ 0);
+ } else {
+ ret = do_freebsd_syscall(env,
+ syscall_num,
+ env->gpr[xA0],
+ env->gpr[xA1],
+ env->gpr[xA2],
+ env->gpr[xA3],
+ env->gpr[xA4],
+ env->gpr[xA5],
+ env->gpr[xA6],
+ env->gpr[xA7]
+ );
+ }
+
+ /*
+ * Compare to cpu_set_syscall_retval() in
+ * riscv/riscv/vm_machdep.c
+ */
+ if (ret >= 0) {
+ env->gpr[xA0] = ret;
+ env->gpr[xT0] = 0;
+ } else if (ret == -TARGET_ERESTART) {
+ env->pc -= TARGET_INSN_SIZE;
+ } else if (ret != -TARGET_EJUSTRETURN) {
+ env->gpr[xA0] = -ret;
+ env->gpr[xT0] = 1;
+ }
+ break;
+ case RISCV_EXCP_ILLEGAL_INST:
+ signo = TARGET_SIGILL;
+ code = TARGET_ILL_ILLOPC;
+ break;
+ case RISCV_EXCP_BREAKPOINT:
+ signo = TARGET_SIGTRAP;
+ code = TARGET_TRAP_BRKPT;
+ break;
+ case EXCP_DEBUG:
+ signo = TARGET_SIGTRAP;
+ code = TARGET_TRAP_BRKPT;
+ break;
+ default:
+ fprintf(stderr, "qemu: unhandled CPU exception "
+ "0x%x - aborting\n", trapnr);
+ cpu_dump_state(cs, stderr, 0);
+ abort();
+ }
+
+ if (signo) {
+ force_sig_fault(signo, code, env->pc);
+ }
+
+ process_pending_signals(env);
+ }
+}
+
#endif /* TARGET_ARCH_CPU_H */
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 21/35] bsd-user: Implement RISC-V CPU register cloning and reset functions
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (19 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 20/35] bsd-user: Add RISC-V CPU execution loop and syscall handling Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 22/35] bsd-user: Implement RISC-V TLS register setup Alistair Francis
` (14 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Richard Henderson,
Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-4-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target_arch_cpu.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h
index 9c31d9dc4c..a93ea3915a 100644
--- a/bsd-user/riscv/target_arch_cpu.h
+++ b/bsd-user/riscv/target_arch_cpu.h
@@ -131,4 +131,18 @@ static inline void target_cpu_loop(CPURISCVState *env)
}
}
+static inline void target_cpu_clone_regs(CPURISCVState *env, target_ulong newsp)
+{
+ if (newsp) {
+ env->gpr[xSP] = newsp;
+ }
+
+ env->gpr[xA0] = 0;
+ env->gpr[xT0] = 0;
+}
+
+static inline void target_cpu_reset(CPUArchState *env)
+{
+}
+
#endif /* TARGET_ARCH_CPU_H */
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 22/35] bsd-user: Implement RISC-V TLS register setup
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (20 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 21/35] bsd-user: Implement RISC-V CPU register cloning and reset functions Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 23/35] bsd-user: Add RISC-V ELF definitions and hardware capability detection Alistair Francis
` (13 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Richard Henderson,
Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Included the prototype for the 'target_cpu_set_tls' function in the
'target_arch.h' header file. This function is responsible for setting
the Thread Local Storage (TLS) register for RISC-V architecture.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-5-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target_arch.h | 27 +++++++++++++++++++++++++++
bsd-user/riscv/target_arch_cpu.c | 29 +++++++++++++++++++++++++++++
2 files changed, 56 insertions(+)
create mode 100644 bsd-user/riscv/target_arch.h
create mode 100644 bsd-user/riscv/target_arch_cpu.c
diff --git a/bsd-user/riscv/target_arch.h b/bsd-user/riscv/target_arch.h
new file mode 100644
index 0000000000..26ce07f343
--- /dev/null
+++ b/bsd-user/riscv/target_arch.h
@@ -0,0 +1,27 @@
+/*
+ * RISC-V specific prototypes
+ *
+ * Copyright (c) 2019 Mark Corbin <mark.corbin@embecsom.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_H
+#define TARGET_ARCH_H
+
+#include "qemu.h"
+
+void target_cpu_set_tls(CPURISCVState *env, target_ulong newtls);
+
+#endif /* TARGET_ARCH_H */
diff --git a/bsd-user/riscv/target_arch_cpu.c b/bsd-user/riscv/target_arch_cpu.c
new file mode 100644
index 0000000000..44e25d2ddf
--- /dev/null
+++ b/bsd-user/riscv/target_arch_cpu.c
@@ -0,0 +1,29 @@
+/*
+ * RISC-V CPU related code
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+
+#include "target_arch.h"
+
+#define TP_OFFSET 16
+
+/* Compare with cpu_set_user_tls() in riscv/riscv/vm_machdep.c */
+void target_cpu_set_tls(CPURISCVState *env, target_ulong newtls)
+{
+ env->gpr[xTP] = newtls + TP_OFFSET;
+}
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 23/35] bsd-user: Add RISC-V ELF definitions and hardware capability detection
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (21 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 22/35] bsd-user: Implement RISC-V TLS register setup Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 24/35] bsd-user: Define RISC-V register structures and register copying Alistair Francis
` (12 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Kyle Evans,
Richard Henderson, Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Introduced RISC-V specific ELF definitions and hardware capability
detection.
Additionally, a function to retrieve hardware capabilities
('get_elf_hwcap') is implemented, which returns the common bits set in
each CPU's ISA strings.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-6-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target_arch_elf.h | 42 ++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_elf.h
diff --git a/bsd-user/riscv/target_arch_elf.h b/bsd-user/riscv/target_arch_elf.h
new file mode 100644
index 0000000000..4eb915e61e
--- /dev/null
+++ b/bsd-user/riscv/target_arch_elf.h
@@ -0,0 +1,42 @@
+/*
+ * RISC-V ELF definitions
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_ELF_H
+#define TARGET_ARCH_ELF_H
+
+#define elf_check_arch(x) ((x) == EM_RISCV)
+#define ELF_START_MMAP 0x80000000
+#define ELF_ET_DYN_LOAD_ADDR 0x100000
+#define ELF_CLASS ELFCLASS64
+
+#define ELF_DATA ELFDATA2LSB
+#define ELF_ARCH EM_RISCV
+
+#define ELF_HWCAP get_elf_hwcap()
+static uint32_t get_elf_hwcap(void)
+{
+ RISCVCPU *cpu = RISCV_CPU(thread_cpu);
+
+ return cpu->env.misa_ext_mask;
+}
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE 4096
+
+#endif /* TARGET_ARCH_ELF_H */
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 24/35] bsd-user: Define RISC-V register structures and register copying
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (22 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 23/35] bsd-user: Add RISC-V ELF definitions and hardware capability detection Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 25/35] bsd-user: Add RISC-V signal trampoline setup function Alistair Francis
` (11 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Richard Henderson,
Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Added definitions for RISC-V register structures, including
general-purpose registers and floating-point registers, in
'target_arch_reg.h'. Implemented the 'target_copy_regs' function to
copy register values from the CPU state to the target register
structure, ensuring proper endianness handling using 'tswapreg'.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-7-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target_arch_reg.h | 88 ++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_reg.h
diff --git a/bsd-user/riscv/target_arch_reg.h b/bsd-user/riscv/target_arch_reg.h
new file mode 100644
index 0000000000..12b1c96b61
--- /dev/null
+++ b/bsd-user/riscv/target_arch_reg.h
@@ -0,0 +1,88 @@
+/*
+ * RISC-V register structures
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_REG_H
+#define TARGET_ARCH_REG_H
+
+/* Compare with riscv/include/reg.h */
+typedef struct target_reg {
+ uint64_t ra; /* return address */
+ uint64_t sp; /* stack pointer */
+ uint64_t gp; /* global pointer */
+ uint64_t tp; /* thread pointer */
+ uint64_t t[7]; /* temporaries */
+ uint64_t s[12]; /* saved registers */
+ uint64_t a[8]; /* function arguments */
+ uint64_t sepc; /* exception program counter */
+ uint64_t sstatus; /* status register */
+} target_reg_t;
+
+typedef struct target_fpreg {
+ uint64_t fp_x[32][2]; /* Floating point registers */
+ uint64_t fp_fcsr; /* Floating point control reg */
+} target_fpreg_t;
+
+#define tswapreg(ptr) tswapal(ptr)
+
+/* Compare with struct trapframe in riscv/include/frame.h */
+static inline void target_copy_regs(target_reg_t *regs,
+ const CPURISCVState *env)
+{
+
+ regs->ra = tswapreg(env->gpr[1]);
+ regs->sp = tswapreg(env->gpr[2]);
+ regs->gp = tswapreg(env->gpr[3]);
+ regs->tp = tswapreg(env->gpr[4]);
+
+ regs->t[0] = tswapreg(env->gpr[5]);
+ regs->t[1] = tswapreg(env->gpr[6]);
+ regs->t[2] = tswapreg(env->gpr[7]);
+ regs->t[3] = tswapreg(env->gpr[28]);
+ regs->t[4] = tswapreg(env->gpr[29]);
+ regs->t[5] = tswapreg(env->gpr[30]);
+ regs->t[6] = tswapreg(env->gpr[31]);
+
+ regs->s[0] = tswapreg(env->gpr[8]);
+ regs->s[1] = tswapreg(env->gpr[9]);
+ regs->s[2] = tswapreg(env->gpr[18]);
+ regs->s[3] = tswapreg(env->gpr[19]);
+ regs->s[4] = tswapreg(env->gpr[20]);
+ regs->s[5] = tswapreg(env->gpr[21]);
+ regs->s[6] = tswapreg(env->gpr[22]);
+ regs->s[7] = tswapreg(env->gpr[23]);
+ regs->s[8] = tswapreg(env->gpr[24]);
+ regs->s[9] = tswapreg(env->gpr[25]);
+ regs->s[10] = tswapreg(env->gpr[26]);
+ regs->s[11] = tswapreg(env->gpr[27]);
+
+ regs->a[0] = tswapreg(env->gpr[10]);
+ regs->a[1] = tswapreg(env->gpr[11]);
+ regs->a[2] = tswapreg(env->gpr[12]);
+ regs->a[3] = tswapreg(env->gpr[13]);
+ regs->a[4] = tswapreg(env->gpr[14]);
+ regs->a[5] = tswapreg(env->gpr[15]);
+ regs->a[6] = tswapreg(env->gpr[16]);
+ regs->a[7] = tswapreg(env->gpr[17]);
+
+ regs->sepc = tswapreg(env->pc);
+}
+
+#undef tswapreg
+
+#endif /* TARGET_ARCH_REG_H */
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 25/35] bsd-user: Add RISC-V signal trampoline setup function
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (23 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 24/35] bsd-user: Define RISC-V register structures and register copying Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 26/35] bsd-user: Implement RISC-V sysarch system call emulation Alistair Francis
` (10 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Richard Henderson,
Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Implemented the 'setup_sigtramp' function for setting up the signal
trampoline code in the RISC-V architecture.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-8-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target_arch_sigtramp.h | 41 +++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_sigtramp.h
diff --git a/bsd-user/riscv/target_arch_sigtramp.h b/bsd-user/riscv/target_arch_sigtramp.h
new file mode 100644
index 0000000000..dfe5076739
--- /dev/null
+++ b/bsd-user/riscv/target_arch_sigtramp.h
@@ -0,0 +1,41 @@
+/*
+ * RISC-V sigcode
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_SIGTRAMP_H
+#define TARGET_ARCH_SIGTRAMP_H
+
+/* Compare with sigcode() in riscv/riscv/locore.S */
+static inline abi_long setup_sigtramp(abi_ulong offset, unsigned sigf_uc,
+ unsigned sys_sigreturn)
+{
+ uint32_t sys_exit = TARGET_FREEBSD_NR_exit;
+
+ uint32_t sigtramp_code[] = {
+ /*1*/ const_le32(0x00010513), /*mv a0, sp*/
+ /*2*/ const_le32(0x00050513 + (sigf_uc << 20)), /*addi a0,a0,sigf_uc*/
+ /*3*/ const_le32(0x00000293 + (sys_sigreturn << 20)),/*li t0,sys_sigreturn*/
+ /*4*/ const_le32(0x00000073), /*ecall*/
+ /*5*/ const_le32(0x00000293 + (sys_exit << 20)), /*li t0,sys_exit*/
+ /*6*/ const_le32(0x00000073), /*ecall*/
+ /*7*/ const_le32(0xFF1FF06F) /*b -16*/
+ };
+
+ return memcpy_to_target(offset, sigtramp_code, TARGET_SZSIGCODE);
+}
+#endif /* TARGET_ARCH_SIGTRAMP_H */
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 26/35] bsd-user: Implement RISC-V sysarch system call emulation
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (24 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 25/35] bsd-user: Add RISC-V signal trampoline setup function Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 27/35] bsd-user: Add RISC-V thread setup and initialization support Alistair Francis
` (9 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Richard Henderson,
Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch'
system call for the RISC-V architecture.
Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that
the operation is not supported.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-9-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target_arch_sysarch.h | 41 ++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_sysarch.h
diff --git a/bsd-user/riscv/target_arch_sysarch.h b/bsd-user/riscv/target_arch_sysarch.h
new file mode 100644
index 0000000000..9af42331b4
--- /dev/null
+++ b/bsd-user/riscv/target_arch_sysarch.h
@@ -0,0 +1,41 @@
+/*
+ * RISC-V sysarch() system call emulation
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_SYSARCH_H
+#define TARGET_ARCH_SYSARCH_H
+
+#include "target_syscall.h"
+#include "target_arch.h"
+
+static inline abi_long do_freebsd_arch_sysarch(CPURISCVState *env, int op,
+ abi_ulong parms)
+{
+
+ return -TARGET_EOPNOTSUPP;
+}
+
+static inline void do_freebsd_arch_print_sysarch(
+ const struct syscallname *name, abi_long arg1, abi_long arg2,
+ abi_long arg3, abi_long arg4, abi_long arg5, abi_long arg6)
+{
+
+ gemu_log("UNKNOWN OP: %d, " TARGET_ABI_FMT_lx ")", (int)arg1, arg2);
+}
+
+#endif /* TARGET_ARCH_SYSARCH_H */
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 27/35] bsd-user: Add RISC-V thread setup and initialization support
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (25 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 26/35] bsd-user: Implement RISC-V sysarch system call emulation Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 28/35] bsd-user: Define RISC-V VM parameters and helper functions Alistair Francis
` (8 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Jessica Clarke, Kyle Evans,
Richard Henderson, Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Implemented functions for setting up and initializing threads in the
RISC-V architecture.
The 'target_thread_set_upcall' function sets up the stack pointer,
program counter, and function argument for new threads.
The 'target_thread_init' function initializes thread registers based on
the provided image information.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Co-authored-by: Kyle Evans <kevans@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-10-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target_arch_thread.h | 47 +++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_thread.h
diff --git a/bsd-user/riscv/target_arch_thread.h b/bsd-user/riscv/target_arch_thread.h
new file mode 100644
index 0000000000..95cd0b6ad7
--- /dev/null
+++ b/bsd-user/riscv/target_arch_thread.h
@@ -0,0 +1,47 @@
+/*
+ * RISC-V thread support
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_THREAD_H
+#define TARGET_ARCH_THREAD_H
+
+/* Compare with cpu_set_upcall() in riscv/riscv/vm_machdep.c */
+static inline void target_thread_set_upcall(CPURISCVState *regs,
+ abi_ulong entry, abi_ulong arg, abi_ulong stack_base,
+ abi_ulong stack_size)
+{
+ abi_ulong sp;
+
+ sp = ROUND_DOWN(stack_base + stack_size, 16);
+
+ regs->gpr[xSP] = sp;
+ regs->pc = entry;
+ regs->gpr[xA0] = arg;
+}
+
+/* Compare with exec_setregs() in riscv/riscv/machdep.c */
+static inline void target_thread_init(struct target_pt_regs *regs,
+ struct image_info *infop)
+{
+ regs->sepc = infop->entry;
+ regs->regs[xRA] = infop->entry;
+ regs->regs[xA0] = infop->start_stack;
+ regs->regs[xSP] = ROUND_DOWN(infop->start_stack, 16);
+}
+
+#endif /* TARGET_ARCH_THREAD_H */
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 28/35] bsd-user: Define RISC-V VM parameters and helper functions
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (26 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 27/35] bsd-user: Add RISC-V thread setup and initialization support Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 29/35] bsd-user: Define RISC-V system call structures and constants Alistair Francis
` (7 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Richard Henderson,
Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Added definitions for RISC-V VM parameters, including maximum and
default sizes for text, data, and stack, as well as address space
limits.
Implemented helper functions for retrieving and setting specific
values in the CPU state, such as stack pointer and return values.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-11-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target_arch_vmparam.h | 53 ++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_vmparam.h
diff --git a/bsd-user/riscv/target_arch_vmparam.h b/bsd-user/riscv/target_arch_vmparam.h
new file mode 100644
index 0000000000..0f2486def1
--- /dev/null
+++ b/bsd-user/riscv/target_arch_vmparam.h
@@ -0,0 +1,53 @@
+/*
+ * RISC-V VM parameters definitions
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_VMPARAM_H
+#define TARGET_ARCH_VMPARAM_H
+
+#include "cpu.h"
+
+/* Compare with riscv/include/vmparam.h */
+#define TARGET_MAXTSIZ (1 * GiB) /* max text size */
+#define TARGET_DFLDSIZ (128 * MiB) /* initial data size limit */
+#define TARGET_MAXDSIZ (1 * GiB) /* max data size */
+#define TARGET_DFLSSIZ (128 * MiB) /* initial stack size limit */
+#define TARGET_MAXSSIZ (1 * GiB) /* max stack size */
+#define TARGET_SGROWSIZ (128 * KiB) /* amount to grow stack */
+
+#define TARGET_VM_MINUSER_ADDRESS (0x0000000000000000UL)
+#define TARGET_VM_MAXUSER_ADDRESS (0x0000004000000000UL)
+
+#define TARGET_USRSTACK (TARGET_VM_MAXUSER_ADDRESS - TARGET_PAGE_SIZE)
+
+static inline abi_ulong get_sp_from_cpustate(CPURISCVState *state)
+{
+ return state->gpr[xSP];
+}
+
+static inline void set_second_rval(CPURISCVState *state, abi_ulong retval2)
+{
+ state->gpr[xA1] = retval2;
+}
+
+static inline abi_ulong get_second_rval(CPURISCVState *state)
+{
+ return state->gpr[xA1];
+}
+
+#endif /* TARGET_ARCH_VMPARAM_H */
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 29/35] bsd-user: Define RISC-V system call structures and constants
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (27 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 28/35] bsd-user: Define RISC-V VM parameters and helper functions Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 30/35] bsd-user: Add generic RISC-V64 target definitions Alistair Francis
` (6 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Jessica Clarke,
Richard Henderson, Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Introduced definitions for the RISC-V system call interface, including
the 'target_pt_regs' structure that outlines the register storage
layout during a system call.
Added constants for hardware machine identifiers.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-12-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target_syscall.h | 38 +++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 bsd-user/riscv/target_syscall.h
diff --git a/bsd-user/riscv/target_syscall.h b/bsd-user/riscv/target_syscall.h
new file mode 100644
index 0000000000..e7e5231309
--- /dev/null
+++ b/bsd-user/riscv/target_syscall.h
@@ -0,0 +1,38 @@
+/*
+ * RISC-V system call definitions
+ *
+ * Copyright (c) Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef BSD_USER_RISCV_TARGET_SYSCALL_H
+#define BSD_USER_RISCV_TARGET_SYSCALL_H
+
+/*
+ * struct target_pt_regs defines the way the registers are stored on the stack
+ * during a system call.
+ */
+
+struct target_pt_regs {
+ abi_ulong regs[32];
+ abi_ulong sepc;
+};
+
+#define UNAME_MACHINE "riscv64"
+
+#define TARGET_HW_MACHINE "riscv"
+#define TARGET_HW_MACHINE_ARCH UNAME_MACHINE
+
+#endif /* BSD_USER_RISCV_TARGET_SYSCALL_H */
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 30/35] bsd-user: Add generic RISC-V64 target definitions
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (28 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 29/35] bsd-user: Define RISC-V system call structures and constants Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 31/35] bsd-user: Define RISC-V signal handling structures and constants Alistair Francis
` (5 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Warner Losh, Ajeet Singh, Richard Henderson,
Alistair Francis
From: Warner Losh <imp@bsdimp.com>
Added a generic definition for RISC-V64 target-specific details.
Implemented the 'regpairs_aligned' function,which returns 'false'
to indicate that register pairs are not aligned in the RISC-V64 ABI.
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-13-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 bsd-user/riscv/target.h
diff --git a/bsd-user/riscv/target.h b/bsd-user/riscv/target.h
new file mode 100644
index 0000000000..036ddd185e
--- /dev/null
+++ b/bsd-user/riscv/target.h
@@ -0,0 +1,20 @@
+/*
+ * Riscv64 general target stuff that's common to all aarch details
+ *
+ * Copyright (c) 2022 M. Warner Losh <imp@bsdimp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef TARGET_H
+#define TARGET_H
+
+/*
+ * riscv64 ABI does not 'lump' the registers for 64-bit args.
+ */
+static inline bool regpairs_aligned(void *cpu_env)
+{
+ return false;
+}
+
+#endif /* TARGET_H */
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 31/35] bsd-user: Define RISC-V signal handling structures and constants
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (29 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 30/35] bsd-user: Add generic RISC-V64 target definitions Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 32/35] bsd-user: Implement RISC-V signal trampoline setup functions Alistair Francis
` (4 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Warner Losh,
Richard Henderson, Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Added definitions for RISC-V signal handling, including structures
and constants for managing signal frames and context
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-14-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/target_arch_signal.h | 75 +++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_signal.h
diff --git a/bsd-user/riscv/target_arch_signal.h b/bsd-user/riscv/target_arch_signal.h
new file mode 100644
index 0000000000..1a634b865b
--- /dev/null
+++ b/bsd-user/riscv/target_arch_signal.h
@@ -0,0 +1,75 @@
+/*
+ * RISC-V signal definitions
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_SIGNAL_H
+#define TARGET_ARCH_SIGNAL_H
+
+#include "cpu.h"
+
+
+#define TARGET_INSN_SIZE 4 /* riscv instruction size */
+
+/* Size of the signal trampoline code placed on the stack. */
+#define TARGET_SZSIGCODE ((abi_ulong)(7 * TARGET_INSN_SIZE))
+
+/* Compare with riscv/include/_limits.h */
+#define TARGET_MINSIGSTKSZ (1024 * 4)
+#define TARGET_SIGSTKSZ (TARGET_MINSIGSTKSZ + 32768)
+
+struct target_gpregs {
+ uint64_t gp_ra;
+ uint64_t gp_sp;
+ uint64_t gp_gp;
+ uint64_t gp_tp;
+ uint64_t gp_t[7];
+ uint64_t gp_s[12];
+ uint64_t gp_a[8];
+ uint64_t gp_sepc;
+ uint64_t gp_sstatus;
+};
+
+struct target_fpregs {
+ uint64_t fp_x[32][2];
+ uint64_t fp_fcsr;
+ uint32_t fp_flags;
+ uint32_t pad;
+};
+
+typedef struct target_mcontext {
+ struct target_gpregs mc_gpregs;
+ struct target_fpregs mc_fpregs;
+ uint32_t mc_flags;
+#define TARGET_MC_FP_VALID 0x01
+ uint32_t mc_pad;
+ uint64_t mc_spare[8];
+} target_mcontext_t;
+
+#define TARGET_MCONTEXT_SIZE 864
+#define TARGET_UCONTEXT_SIZE 936
+
+#include "target_os_ucontext.h"
+
+struct target_sigframe {
+ target_ucontext_t sf_uc; /* = *sf_uncontext */
+ target_siginfo_t sf_si; /* = *sf_siginfo (SA_SIGINFO case)*/
+};
+
+#define TARGET_SIGSTACK_ALIGN 16
+
+#endif /* TARGET_ARCH_SIGNAL_H */
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 32/35] bsd-user: Implement RISC-V signal trampoline setup functions
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (30 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 31/35] bsd-user: Define RISC-V signal handling structures and constants Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 33/35] bsd-user: Implement 'get_mcontext' for RISC-V Alistair Francis
` (3 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Warner Losh,
Richard Henderson, Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Added functions for setting up the RISC-V signal trampoline and signal
frame:
'set_sigtramp_args()': Configures the RISC-V CPU state with arguments
for the signal handler. It sets up the registers with the signal
number,pointers to the signal info and user context, the signal handler
address, and the signal frame pointer.
'setup_sigframe_arch()': Initializes the signal frame with the current
machine context.This function copies the context from the CPU state to
the signal frame, preparing it for the signal handler.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Co-authored-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-15-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/signal.c | 63 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 bsd-user/riscv/signal.c
diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signal.c
new file mode 100644
index 0000000000..2597fec2fd
--- /dev/null
+++ b/bsd-user/riscv/signal.c
@@ -0,0 +1,63 @@
+/*
+ * RISC-V signal definitions
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+
+#include "qemu.h"
+
+/*
+ * Compare with sendsig() in riscv/riscv/exec_machdep.c
+ * Assumes that target stack frame memory is locked.
+ */
+abi_long
+set_sigtramp_args(CPURISCVState *regs, int sig, struct target_sigframe *frame,
+ abi_ulong frame_addr, struct target_sigaction *ka)
+{
+ /*
+ * Arguments to signal handler:
+ * a0 (10) = signal number
+ * a1 (11) = siginfo pointer
+ * a2 (12) = ucontext pointer
+ * pc = signal pointer handler
+ * sp (2) = sigframe pointer
+ * ra (1) = sigtramp at base of user stack
+ */
+
+ regs->gpr[xA0] = sig;
+ regs->gpr[xA1] = frame_addr +
+ offsetof(struct target_sigframe, sf_si);
+ regs->gpr[xA2] = frame_addr +
+ offsetof(struct target_sigframe, sf_uc);
+ regs->pc = ka->_sa_handler;
+ regs->gpr[xSP] = frame_addr;
+ regs->gpr[xRA] = TARGET_PS_STRINGS - TARGET_SZSIGCODE;
+ return 0;
+}
+
+/*
+ * Compare to riscv/riscv/exec_machdep.c sendsig()
+ * Assumes that the memory is locked if frame points to user memory.
+ */
+abi_long setup_sigframe_arch(CPURISCVState *env, abi_ulong frame_addr,
+ struct target_sigframe *frame, int flags)
+{
+ target_mcontext_t *mcp = &frame->sf_uc.uc_mcontext;
+
+ get_mcontext(env, mcp, flags);
+ return 0;
+}
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 33/35] bsd-user: Implement 'get_mcontext' for RISC-V
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (31 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 32/35] bsd-user: Implement RISC-V signal trampoline setup functions Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 34/35] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Alistair Francis
` (2 subsequent siblings)
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Ajeet Singh, Warner Losh,
Richard Henderson, Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Added the 'get_mcontext' function to extract and populate
the RISC-V machine context from the CPU state.
This function is used to gather the current state of the
general-purpose registers and store it in a 'target_mcontext_'
structure.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Co-authored-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-16-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/signal.c | 53 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signal.c
index 2597fec2fd..072ad821d2 100644
--- a/bsd-user/riscv/signal.c
+++ b/bsd-user/riscv/signal.c
@@ -61,3 +61,56 @@ abi_long setup_sigframe_arch(CPURISCVState *env, abi_ulong frame_addr,
get_mcontext(env, mcp, flags);
return 0;
}
+
+/*
+ * Compare with get_mcontext() in riscv/riscv/machdep.c
+ * Assumes that the memory is locked if mcp points to user memory.
+ */
+abi_long get_mcontext(CPURISCVState *regs, target_mcontext_t *mcp,
+ int flags)
+{
+
+ mcp->mc_gpregs.gp_t[0] = tswap64(regs->gpr[5]);
+ mcp->mc_gpregs.gp_t[1] = tswap64(regs->gpr[6]);
+ mcp->mc_gpregs.gp_t[2] = tswap64(regs->gpr[7]);
+ mcp->mc_gpregs.gp_t[3] = tswap64(regs->gpr[28]);
+ mcp->mc_gpregs.gp_t[4] = tswap64(regs->gpr[29]);
+ mcp->mc_gpregs.gp_t[5] = tswap64(regs->gpr[30]);
+ mcp->mc_gpregs.gp_t[6] = tswap64(regs->gpr[31]);
+
+ mcp->mc_gpregs.gp_s[0] = tswap64(regs->gpr[8]);
+ mcp->mc_gpregs.gp_s[1] = tswap64(regs->gpr[9]);
+ mcp->mc_gpregs.gp_s[2] = tswap64(regs->gpr[18]);
+ mcp->mc_gpregs.gp_s[3] = tswap64(regs->gpr[19]);
+ mcp->mc_gpregs.gp_s[4] = tswap64(regs->gpr[20]);
+ mcp->mc_gpregs.gp_s[5] = tswap64(regs->gpr[21]);
+ mcp->mc_gpregs.gp_s[6] = tswap64(regs->gpr[22]);
+ mcp->mc_gpregs.gp_s[7] = tswap64(regs->gpr[23]);
+ mcp->mc_gpregs.gp_s[8] = tswap64(regs->gpr[24]);
+ mcp->mc_gpregs.gp_s[9] = tswap64(regs->gpr[25]);
+ mcp->mc_gpregs.gp_s[10] = tswap64(regs->gpr[26]);
+ mcp->mc_gpregs.gp_s[11] = tswap64(regs->gpr[27]);
+
+ mcp->mc_gpregs.gp_a[0] = tswap64(regs->gpr[10]);
+ mcp->mc_gpregs.gp_a[1] = tswap64(regs->gpr[11]);
+ mcp->mc_gpregs.gp_a[2] = tswap64(regs->gpr[12]);
+ mcp->mc_gpregs.gp_a[3] = tswap64(regs->gpr[13]);
+ mcp->mc_gpregs.gp_a[4] = tswap64(regs->gpr[14]);
+ mcp->mc_gpregs.gp_a[5] = tswap64(regs->gpr[15]);
+ mcp->mc_gpregs.gp_a[6] = tswap64(regs->gpr[16]);
+ mcp->mc_gpregs.gp_a[7] = tswap64(regs->gpr[17]);
+
+ if (flags & TARGET_MC_GET_CLEAR_RET) {
+ mcp->mc_gpregs.gp_a[0] = 0; /* a0 */
+ mcp->mc_gpregs.gp_a[1] = 0; /* a1 */
+ mcp->mc_gpregs.gp_t[0] = 0; /* clear syscall error */
+ }
+
+ mcp->mc_gpregs.gp_ra = tswap64(regs->gpr[1]);
+ mcp->mc_gpregs.gp_sp = tswap64(regs->gpr[2]);
+ mcp->mc_gpregs.gp_gp = tswap64(regs->gpr[3]);
+ mcp->mc_gpregs.gp_tp = tswap64(regs->gpr[4]);
+ mcp->mc_gpregs.gp_sepc = tswap64(regs->pc);
+
+ return 0;
+}
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 34/35] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (32 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 33/35] bsd-user: Implement 'get_mcontext' for RISC-V Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-02 5:50 ` [PULL v3 35/35] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Alistair Francis
2024-10-03 9:32 ` [PULL v3 00/35] riscv-to-apply queue Peter Maydell
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Mark Corbin, Warner Losh, Ajeet Singh,
Richard Henderson, Alistair Francis
From: Mark Corbin <mark@dibsco.co.uk>
Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn'
functions for RISC-V architecture,
Both functions ensure that the CPU state and user context are properly
managed.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-17-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
bsd-user/riscv/signal.c | 54 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signal.c
index 072ad821d2..10c940cd49 100644
--- a/bsd-user/riscv/signal.c
+++ b/bsd-user/riscv/signal.c
@@ -114,3 +114,57 @@ abi_long get_mcontext(CPURISCVState *regs, target_mcontext_t *mcp,
return 0;
}
+
+/* Compare with set_mcontext() in riscv/riscv/exec_machdep.c */
+abi_long set_mcontext(CPURISCVState *regs, target_mcontext_t *mcp,
+ int srflag)
+{
+
+ regs->gpr[5] = tswap64(mcp->mc_gpregs.gp_t[0]);
+ regs->gpr[6] = tswap64(mcp->mc_gpregs.gp_t[1]);
+ regs->gpr[7] = tswap64(mcp->mc_gpregs.gp_t[2]);
+ regs->gpr[28] = tswap64(mcp->mc_gpregs.gp_t[3]);
+ regs->gpr[29] = tswap64(mcp->mc_gpregs.gp_t[4]);
+ regs->gpr[30] = tswap64(mcp->mc_gpregs.gp_t[5]);
+ regs->gpr[31] = tswap64(mcp->mc_gpregs.gp_t[6]);
+
+ regs->gpr[8] = tswap64(mcp->mc_gpregs.gp_s[0]);
+ regs->gpr[9] = tswap64(mcp->mc_gpregs.gp_s[1]);
+ regs->gpr[18] = tswap64(mcp->mc_gpregs.gp_s[2]);
+ regs->gpr[19] = tswap64(mcp->mc_gpregs.gp_s[3]);
+ regs->gpr[20] = tswap64(mcp->mc_gpregs.gp_s[4]);
+ regs->gpr[21] = tswap64(mcp->mc_gpregs.gp_s[5]);
+ regs->gpr[22] = tswap64(mcp->mc_gpregs.gp_s[6]);
+ regs->gpr[23] = tswap64(mcp->mc_gpregs.gp_s[7]);
+ regs->gpr[24] = tswap64(mcp->mc_gpregs.gp_s[8]);
+ regs->gpr[25] = tswap64(mcp->mc_gpregs.gp_s[9]);
+ regs->gpr[26] = tswap64(mcp->mc_gpregs.gp_s[10]);
+ regs->gpr[27] = tswap64(mcp->mc_gpregs.gp_s[11]);
+
+ regs->gpr[10] = tswap64(mcp->mc_gpregs.gp_a[0]);
+ regs->gpr[11] = tswap64(mcp->mc_gpregs.gp_a[1]);
+ regs->gpr[12] = tswap64(mcp->mc_gpregs.gp_a[2]);
+ regs->gpr[13] = tswap64(mcp->mc_gpregs.gp_a[3]);
+ regs->gpr[14] = tswap64(mcp->mc_gpregs.gp_a[4]);
+ regs->gpr[15] = tswap64(mcp->mc_gpregs.gp_a[5]);
+ regs->gpr[16] = tswap64(mcp->mc_gpregs.gp_a[6]);
+ regs->gpr[17] = tswap64(mcp->mc_gpregs.gp_a[7]);
+
+
+ regs->gpr[1] = tswap64(mcp->mc_gpregs.gp_ra);
+ regs->gpr[2] = tswap64(mcp->mc_gpregs.gp_sp);
+ regs->gpr[3] = tswap64(mcp->mc_gpregs.gp_gp);
+ regs->gpr[4] = tswap64(mcp->mc_gpregs.gp_tp);
+ regs->pc = tswap64(mcp->mc_gpregs.gp_sepc);
+
+ return 0;
+}
+
+/* Compare with sys_sigreturn() in riscv/riscv/machdep.c */
+abi_long get_ucontext_sigreturn(CPURISCVState *regs,
+ abi_ulong target_sf, abi_ulong *target_uc)
+{
+
+ *target_uc = target_sf;
+ return 0;
+}
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PULL v3 35/35] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (33 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 34/35] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Alistair Francis
@ 2024-10-02 5:50 ` Alistair Francis
2024-10-03 9:32 ` [PULL v3 00/35] riscv-to-apply queue Peter Maydell
35 siblings, 0 replies; 37+ messages in thread
From: Alistair Francis @ 2024-10-02 5:50 UTC (permalink / raw)
To: qemu-devel
Cc: alistair23, Warner Losh, Ajeet Singh, Richard Henderson,
Alistair Francis
From: Warner Losh <imp@bsdimp.com>
Added configuration for RISC-V 64-bit target to the build system.
Signed-off-by: Warner Losh <imp@bsdimp.com>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20240916155119.14610-18-itachis@FreeBSD.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
configs/targets/riscv64-bsd-user.mak | 4 ++++
1 file changed, 4 insertions(+)
create mode 100644 configs/targets/riscv64-bsd-user.mak
diff --git a/configs/targets/riscv64-bsd-user.mak b/configs/targets/riscv64-bsd-user.mak
new file mode 100644
index 0000000000..191c2c483f
--- /dev/null
+++ b/configs/targets/riscv64-bsd-user.mak
@@ -0,0 +1,4 @@
+TARGET_ARCH=riscv64
+TARGET_BASE_ARCH=riscv
+TARGET_ABI_DIR=riscv
+TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
--
2.46.2
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PULL v3 00/35] riscv-to-apply queue
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
` (34 preceding siblings ...)
2024-10-02 5:50 ` [PULL v3 35/35] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Alistair Francis
@ 2024-10-03 9:32 ` Peter Maydell
35 siblings, 0 replies; 37+ messages in thread
From: Peter Maydell @ 2024-10-03 9:32 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel, Alistair Francis
On Wed, 2 Oct 2024 at 06:51, Alistair Francis <alistair23@gmail.com> wrote:
>
> The following changes since commit 718780d20470c66a3a36d036b29148d5809dc855:
>
> Merge tag 'pull-nvme-20241001' of https://gitlab.com/birkelund/qemu into staging (2024-10-01 11:34:07 +0100)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241002
>
> for you to fetch changes up to 74b493244d0624afed22606e76fc7fca62777401:
>
> bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files (2024-10-02 15:11:52 +1000)
>
> ----------------------------------------------------------------
> RISC-V PR for 9.2
>
> * Add a property to set vl to ceil(AVL/2)
> * Enable numamem testing for RISC-V
> * Consider MISA bit choice in implied rule
> * Fix the za64rs priv spec requirements
> * Enable Bit Manip for OpenTitan Ibex CPU
> * Fix the group bit setting of AIA with KVM
> * Stop timer with infinite timecmp
> * Add 'fcsr' register to QEMU log as a part of F extension
> * Fix riscv64 build on musl libc
> * Add preliminary textra trigger CSR functions
> * RISC-V bsd-user support
> * Respect firmware ELF entry point
> * Add Svvptc extension support
> * Fix masking of rv32 physical address
> * Fix linking problem with semihosting disabled
> * Fix IMSIC interrupt state updates
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.2
for any user-visible changes.
-- PMM
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2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
2024-10-02 5:50 ` [PULL v3 01/35] target/riscv: Add a property to set vl to ceil(AVL/2) Alistair Francis
2024-10-02 5:50 ` [PULL v3 02/35] tests/acpi: Add empty ACPI SRAT data file for RISC-V Alistair Francis
2024-10-02 5:50 ` [PULL v3 03/35] tests/qtest/bios-tables-test.c: Enable numamem testing " Alistair Francis
2024-10-02 5:50 ` [PULL v3 04/35] tests/acpi: Add expected ACPI SRAT AML file " Alistair Francis
2024-10-02 5:50 ` [PULL v3 05/35] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule Alistair Francis
2024-10-02 5:50 ` [PULL v3 06/35] target/riscv: fix za64rs enabling Alistair Francis
2024-10-02 5:50 ` [PULL v3 07/35] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU Alistair Francis
2024-10-02 5:50 ` [PULL v3 08/35] target/riscv/kvm: Fix the group bit setting of AIA Alistair Francis
2024-10-02 5:50 ` [PULL v3 09/35] target/riscv: Stop timer with infinite timecmp Alistair Francis
2024-10-02 5:50 ` [PULL v3 10/35] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension Alistair Francis
2024-10-02 5:50 ` [PULL v3 11/35] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc Alistair Francis
2024-10-02 5:50 ` [PULL v3 12/35] target/riscv: Preliminary textra trigger CSR writting support Alistair Francis
2024-10-02 5:50 ` [PULL v3 13/35] target/riscv: Add textra matching condition for the triggers Alistair Francis
2024-10-02 5:50 ` [PULL v3 14/35] hw/riscv: Respect firmware ELF entry point Alistair Francis
2024-10-02 5:50 ` [PULL v3 15/35] target: riscv: Add Svvptc extension support Alistair Francis
2024-10-02 5:50 ` [PULL v3 16/35] target/riscv32: Fix masking of physical address Alistair Francis
2024-10-02 5:50 ` [PULL v3 17/35] target/riscv/cpu_helper: Fix linking problem with semihosting disabled Alistair Francis
2024-10-02 5:50 ` [PULL v3 18/35] hw/intc: riscv-imsic: Fix interrupt state updates Alistair Francis
2024-10-02 5:50 ` [PULL v3 19/35] bsd-user: Implement RISC-V CPU initialization and main loop Alistair Francis
2024-10-02 5:50 ` [PULL v3 20/35] bsd-user: Add RISC-V CPU execution loop and syscall handling Alistair Francis
2024-10-02 5:50 ` [PULL v3 21/35] bsd-user: Implement RISC-V CPU register cloning and reset functions Alistair Francis
2024-10-02 5:50 ` [PULL v3 22/35] bsd-user: Implement RISC-V TLS register setup Alistair Francis
2024-10-02 5:50 ` [PULL v3 23/35] bsd-user: Add RISC-V ELF definitions and hardware capability detection Alistair Francis
2024-10-02 5:50 ` [PULL v3 24/35] bsd-user: Define RISC-V register structures and register copying Alistair Francis
2024-10-02 5:50 ` [PULL v3 25/35] bsd-user: Add RISC-V signal trampoline setup function Alistair Francis
2024-10-02 5:50 ` [PULL v3 26/35] bsd-user: Implement RISC-V sysarch system call emulation Alistair Francis
2024-10-02 5:50 ` [PULL v3 27/35] bsd-user: Add RISC-V thread setup and initialization support Alistair Francis
2024-10-02 5:50 ` [PULL v3 28/35] bsd-user: Define RISC-V VM parameters and helper functions Alistair Francis
2024-10-02 5:50 ` [PULL v3 29/35] bsd-user: Define RISC-V system call structures and constants Alistair Francis
2024-10-02 5:50 ` [PULL v3 30/35] bsd-user: Add generic RISC-V64 target definitions Alistair Francis
2024-10-02 5:50 ` [PULL v3 31/35] bsd-user: Define RISC-V signal handling structures and constants Alistair Francis
2024-10-02 5:50 ` [PULL v3 32/35] bsd-user: Implement RISC-V signal trampoline setup functions Alistair Francis
2024-10-02 5:50 ` [PULL v3 33/35] bsd-user: Implement 'get_mcontext' for RISC-V Alistair Francis
2024-10-02 5:50 ` [PULL v3 34/35] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Alistair Francis
2024-10-02 5:50 ` [PULL v3 35/35] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Alistair Francis
2024-10-03 9:32 ` [PULL v3 00/35] riscv-to-apply queue Peter Maydell
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