From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
Vladimir Isaev <vladimir.isaev@syntacore.com>,
Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL v3 06/35] target/riscv: fix za64rs enabling
Date: Wed, 2 Oct 2024 15:50:19 +1000 [thread overview]
Message-ID: <20241002055048.556083-7-alistair.francis@wdc.com> (raw)
In-Reply-To: <20241002055048.556083-1-alistair.francis@wdc.com>
From: Vladimir Isaev <vladimir.isaev@syntacore.com>
za64rs requires priv 1.12 when enabled by priv 1.11.
This fixes annoying warning:
warning: disabling za64rs extension for hart 0x00000000 because privilege spec version does not match
on priv 1.11 CPUs.
Fixes: 68c9e54beae8 ("target/riscv: do not enable all named features by default")
Signed-off-by: Vladimir Isaev <vladimir.isaev@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240823063431.17474-1-vladimir.isaev@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cc5552500a..0f8189bcf0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -115,7 +115,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
ISA_EXT_DATA_ENTRY(zimop, PRIV_VERSION_1_13_0, ext_zimop),
ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
- ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_11),
+ ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_13_0, ext_zabha),
ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
--
2.46.2
next prev parent reply other threads:[~2024-10-02 5:54 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-02 5:50 [PULL v3 00/35] riscv-to-apply queue Alistair Francis
2024-10-02 5:50 ` [PULL v3 01/35] target/riscv: Add a property to set vl to ceil(AVL/2) Alistair Francis
2024-10-02 5:50 ` [PULL v3 02/35] tests/acpi: Add empty ACPI SRAT data file for RISC-V Alistair Francis
2024-10-02 5:50 ` [PULL v3 03/35] tests/qtest/bios-tables-test.c: Enable numamem testing " Alistair Francis
2024-10-02 5:50 ` [PULL v3 04/35] tests/acpi: Add expected ACPI SRAT AML file " Alistair Francis
2024-10-02 5:50 ` [PULL v3 05/35] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule Alistair Francis
2024-10-02 5:50 ` Alistair Francis [this message]
2024-10-02 5:50 ` [PULL v3 07/35] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU Alistair Francis
2024-10-02 5:50 ` [PULL v3 08/35] target/riscv/kvm: Fix the group bit setting of AIA Alistair Francis
2024-10-02 5:50 ` [PULL v3 09/35] target/riscv: Stop timer with infinite timecmp Alistair Francis
2024-10-02 5:50 ` [PULL v3 10/35] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension Alistair Francis
2024-10-02 5:50 ` [PULL v3 11/35] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc Alistair Francis
2024-10-02 5:50 ` [PULL v3 12/35] target/riscv: Preliminary textra trigger CSR writting support Alistair Francis
2024-10-02 5:50 ` [PULL v3 13/35] target/riscv: Add textra matching condition for the triggers Alistair Francis
2024-10-02 5:50 ` [PULL v3 14/35] hw/riscv: Respect firmware ELF entry point Alistair Francis
2024-10-02 5:50 ` [PULL v3 15/35] target: riscv: Add Svvptc extension support Alistair Francis
2024-10-02 5:50 ` [PULL v3 16/35] target/riscv32: Fix masking of physical address Alistair Francis
2024-10-02 5:50 ` [PULL v3 17/35] target/riscv/cpu_helper: Fix linking problem with semihosting disabled Alistair Francis
2024-10-02 5:50 ` [PULL v3 18/35] hw/intc: riscv-imsic: Fix interrupt state updates Alistair Francis
2024-10-02 5:50 ` [PULL v3 19/35] bsd-user: Implement RISC-V CPU initialization and main loop Alistair Francis
2024-10-02 5:50 ` [PULL v3 20/35] bsd-user: Add RISC-V CPU execution loop and syscall handling Alistair Francis
2024-10-02 5:50 ` [PULL v3 21/35] bsd-user: Implement RISC-V CPU register cloning and reset functions Alistair Francis
2024-10-02 5:50 ` [PULL v3 22/35] bsd-user: Implement RISC-V TLS register setup Alistair Francis
2024-10-02 5:50 ` [PULL v3 23/35] bsd-user: Add RISC-V ELF definitions and hardware capability detection Alistair Francis
2024-10-02 5:50 ` [PULL v3 24/35] bsd-user: Define RISC-V register structures and register copying Alistair Francis
2024-10-02 5:50 ` [PULL v3 25/35] bsd-user: Add RISC-V signal trampoline setup function Alistair Francis
2024-10-02 5:50 ` [PULL v3 26/35] bsd-user: Implement RISC-V sysarch system call emulation Alistair Francis
2024-10-02 5:50 ` [PULL v3 27/35] bsd-user: Add RISC-V thread setup and initialization support Alistair Francis
2024-10-02 5:50 ` [PULL v3 28/35] bsd-user: Define RISC-V VM parameters and helper functions Alistair Francis
2024-10-02 5:50 ` [PULL v3 29/35] bsd-user: Define RISC-V system call structures and constants Alistair Francis
2024-10-02 5:50 ` [PULL v3 30/35] bsd-user: Add generic RISC-V64 target definitions Alistair Francis
2024-10-02 5:50 ` [PULL v3 31/35] bsd-user: Define RISC-V signal handling structures and constants Alistair Francis
2024-10-02 5:50 ` [PULL v3 32/35] bsd-user: Implement RISC-V signal trampoline setup functions Alistair Francis
2024-10-02 5:50 ` [PULL v3 33/35] bsd-user: Implement 'get_mcontext' for RISC-V Alistair Francis
2024-10-02 5:50 ` [PULL v3 34/35] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Alistair Francis
2024-10-02 5:50 ` [PULL v3 35/35] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Alistair Francis
2024-10-03 9:32 ` [PULL v3 00/35] riscv-to-apply queue Peter Maydell
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