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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: deller@kernel.org, peter.maydell@linaro.org,
	alex.bennee@linaro.org, linux-parisc@vger.kernel.org,
	qemu-arm@nongnu.org
Subject: [PATCH 14/20] target/arm: Pass MemOp to get_phys_addr_with_space_nogpc
Date: Sat,  5 Oct 2024 08:25:45 -0700	[thread overview]
Message-ID: <20241005152551.307923-15-richard.henderson@linaro.org> (raw)
In-Reply-To: <20241005152551.307923-1-richard.henderson@linaro.org>

Zero is the safe do-nothing value for callers to use.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/internals.h | 3 ++-
 target/arm/helper.c    | 4 ++--
 target/arm/ptw.c       | 2 +-
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index 2b16579fa5..a6088d551c 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1461,6 +1461,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address,
  * @env: CPUARMState
  * @address: virtual address to get physical address for
  * @access_type: 0 for read, 1 for write, 2 for execute
+ * @memop: memory operation feeding this access, or 0 for none
  * @mmu_idx: MMU index indicating required translation regime
  * @space: security space for the access
  * @result: set on translation success.
@@ -1470,7 +1471,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address,
  * a Granule Protection Check on the resulting address.
  */
 bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address,
-                                    MMUAccessType access_type,
+                                    MMUAccessType access_type, MemOp memop,
                                     ARMMMUIdx mmu_idx, ARMSecuritySpace space,
                                     GetPhysAddrResult *result,
                                     ARMMMUFaultInfo *fi)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3f77b40734..f2f329e00a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3602,8 +3602,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
      * I_MXTJT: Granule protection checks are not performed on the final address
      * of a successful translation.
      */
-    ret = get_phys_addr_with_space_nogpc(env, value, access_type, mmu_idx, ss,
-                                         &res, &fi);
+    ret = get_phys_addr_with_space_nogpc(env, value, access_type, 0,
+                                         mmu_idx, ss, &res, &fi);
 
     /*
      * ATS operations only do S1 or S1+S2 translations, so we never
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 373095a339..9af86da597 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -3559,7 +3559,7 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw,
 }
 
 bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address,
-                                    MMUAccessType access_type,
+                                    MMUAccessType access_type, MemOp memop,
                                     ARMMMUIdx mmu_idx, ARMSecuritySpace space,
                                     GetPhysAddrResult *result,
                                     ARMMMUFaultInfo *fi)
-- 
2.43.0



  parent reply	other threads:[~2024-10-05 15:27 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-05 15:25 [PATCH 00/20] accel/tcg: Introduce tlb_fill_align hook Richard Henderson
2024-10-05 15:25 ` [PATCH 01/20] accel/tcg: Assert noreturn from write-only page for atomics Richard Henderson
2024-10-05 15:25 ` [PATCH 02/20] accel/tcg: Expand tlb_fill for 3 callers Richard Henderson
2024-10-07 21:16   ` Philippe Mathieu-Daudé
2024-10-05 15:25 ` [PATCH 03/20] include/exec/memop: Move get_alignment_bits from tcg.h Richard Henderson
2024-10-07 21:17   ` Philippe Mathieu-Daudé
2024-10-05 15:25 ` [PATCH 04/20] include/exec/memop: Rename get_alignment_bits Richard Henderson
2024-10-07 21:18   ` Philippe Mathieu-Daudé
2024-10-05 15:25 ` [PATCH 05/20] include/exec/memop: Introduce memop_atomicity_bits Richard Henderson
2024-10-05 15:25 ` [PATCH 06/20] hw/core/tcg-cpu-ops: Introduce tlb_fill_align hook Richard Henderson
2024-10-05 15:25 ` [PATCH 07/20] accel/tcg: Use the " Richard Henderson
2024-10-05 15:25 ` [PATCH 08/20] target/hppa: Add MemOp argument to hppa_get_physical_address Richard Henderson
2024-10-07 21:27   ` Philippe Mathieu-Daudé
2024-10-05 15:25 ` [PATCH 09/20] target/hppa: Perform access rights before protection id check Richard Henderson
2024-10-05 15:25 ` [PATCH 10/20] target/hppa: Fix priority of T, D, and B page faults Richard Henderson
2024-10-07 21:25   ` Philippe Mathieu-Daudé
2024-10-05 15:25 ` [PATCH 11/20] target/hppa: Handle alignment faults in hppa_get_physical_address Richard Henderson
2024-10-05 15:25 ` [PATCH 12/20] target/hppa: Add hppa_cpu_tlb_fill_align Richard Henderson
2024-10-05 15:25 ` [PATCH 13/20] target/arm: Pass MemOp to get_phys_addr Richard Henderson
2024-10-07 21:21   ` Philippe Mathieu-Daudé
2024-10-05 15:25 ` Richard Henderson [this message]
2024-10-07 21:21   ` [PATCH 14/20] target/arm: Pass MemOp to get_phys_addr_with_space_nogpc Philippe Mathieu-Daudé
2024-10-05 15:25 ` [PATCH 15/20] target/arm: Pass MemOp to get_phys_addr_gpc Richard Henderson
2024-10-07 21:21   ` Philippe Mathieu-Daudé
2024-10-05 15:25 ` [PATCH 16/20] target/arm: Pass MemOp to get_phys_addr_nogpc Richard Henderson
2024-10-07 21:22   ` Philippe Mathieu-Daudé
2024-10-05 15:25 ` [PATCH 17/20] target/arm: Pass MemOp through get_phys_addr_twostage Richard Henderson
2024-10-07 21:22   ` Philippe Mathieu-Daudé
2024-10-05 15:25 ` [PATCH 18/20] target/arm: Pass MemOp to get_phys_addr_lpae Richard Henderson
2024-10-07 21:22   ` Philippe Mathieu-Daudé
2024-10-05 15:25 ` [PATCH 19/20] target/arm: Move device detection earlier in get_phys_addr_lpae Richard Henderson
2024-10-05 15:25 ` [PATCH 20/20] target/arm: Fix alignment fault priority " Richard Henderson

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