From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: [PATCH v1 3/7] target/riscv: Read pte and satp based on SXL in PTW
Date: Mon, 7 Oct 2024 11:33:56 +0800 [thread overview]
Message-ID: <20241007033400.50163-4-zhiwei_liu@linux.alibaba.com> (raw)
In-Reply-To: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com>
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Satp and PTE are always SXLEN-bit. when SXLEN is 32,
read PTE as 4 bytes, and treat satp as SATP32.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
---
target/riscv/cpu_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 077f6d77c3..773789e02e 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -851,7 +851,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
vm = get_field(env->vsatp, SATP64_MODE);
}
} else {
- if (riscv_cpu_mxl(env) == MXL_RV32) {
+ if (riscv_cpu_sxl(env) == MXL_RV32) {
base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->satp, SATP32_MODE);
} else {
@@ -972,7 +972,7 @@ restart:
return TRANSLATE_PMP_FAIL;
}
- if (riscv_cpu_mxl(env) == MXL_RV32) {
+ if (riscv_cpu_sxl(env) == MXL_RV32) {
pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
} else {
pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
--
2.43.0
next prev parent reply other threads:[~2024-10-07 3:36 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-07 3:33 [PATCH v1 0/7] target/riscv: Support SXL32 on RV64 CPU LIU Zhiwei
2024-10-07 3:33 ` [PATCH v1 1/7] target/riscv: Fix sstatus read and write LIU Zhiwei
2024-10-11 3:44 ` Alistair Francis
2024-10-07 3:33 ` [PATCH v1 2/7] target/riscv: Fix satp read and write implicitly or explicitly LIU Zhiwei
2024-10-11 3:58 ` Alistair Francis
2024-10-07 3:33 ` LIU Zhiwei [this message]
2024-10-11 3:59 ` [PATCH v1 3/7] target/riscv: Read pte and satp based on SXL in PTW Alistair Francis
2024-10-07 3:33 ` [PATCH v1 4/7] hw/riscv: Align kernel to 4MB when sxl32 is on LIU Zhiwei
2024-10-07 3:33 ` [PATCH v1 5/7] target/riscv: Enable 32-bit only registers for RV64 with sxl32 LIU Zhiwei
2024-10-11 4:00 ` Alistair Francis
2024-10-07 3:33 ` [PATCH v1 6/7] target/riscv: Reset SXL and UXL according to sxl32 LIU Zhiwei
2024-10-07 3:34 ` [PATCH v1 7/7] target/riscv: Expose sxl32 configuration in RISC-V CPU LIU Zhiwei
2024-10-11 3:56 ` Alistair Francis
2024-10-11 3:55 ` [PATCH v1 0/7] target/riscv: Support SXL32 on RV64 CPU Alistair Francis
2024-10-22 6:41 ` LIU Zhiwei
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