From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: [PATCH v1 4/7] hw/riscv: Align kernel to 4MB when sxl32 is on.
Date: Mon, 7 Oct 2024 11:33:57 +0800 [thread overview]
Message-ID: <20241007033400.50163-5-zhiwei_liu@linux.alibaba.com> (raw)
In-Reply-To: <20241007033400.50163-1-zhiwei_liu@linux.alibaba.com>
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
RISC-V always requires 4MB alignment for RV32.
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
---
hw/riscv/boot.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 1a2c1ff9e0..7ce0d8f08f 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -69,7 +69,8 @@ char *riscv_plic_hart_config_string(int hart_count)
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
target_ulong firmware_end_addr) {
- if (riscv_is_32bit(harts)) {
+ RISCVCPU *cpu = &harts->harts[0];
+ if (riscv_is_32bit(harts) || cpu->cfg.sxl32) {
return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
} else {
return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB);
--
2.43.0
next prev parent reply other threads:[~2024-10-07 3:36 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-07 3:33 [PATCH v1 0/7] target/riscv: Support SXL32 on RV64 CPU LIU Zhiwei
2024-10-07 3:33 ` [PATCH v1 1/7] target/riscv: Fix sstatus read and write LIU Zhiwei
2024-10-11 3:44 ` Alistair Francis
2024-10-07 3:33 ` [PATCH v1 2/7] target/riscv: Fix satp read and write implicitly or explicitly LIU Zhiwei
2024-10-11 3:58 ` Alistair Francis
2024-10-07 3:33 ` [PATCH v1 3/7] target/riscv: Read pte and satp based on SXL in PTW LIU Zhiwei
2024-10-11 3:59 ` Alistair Francis
2024-10-07 3:33 ` LIU Zhiwei [this message]
2024-10-07 3:33 ` [PATCH v1 5/7] target/riscv: Enable 32-bit only registers for RV64 with sxl32 LIU Zhiwei
2024-10-11 4:00 ` Alistair Francis
2024-10-07 3:33 ` [PATCH v1 6/7] target/riscv: Reset SXL and UXL according to sxl32 LIU Zhiwei
2024-10-07 3:34 ` [PATCH v1 7/7] target/riscv: Expose sxl32 configuration in RISC-V CPU LIU Zhiwei
2024-10-11 3:56 ` Alistair Francis
2024-10-11 3:55 ` [PATCH v1 0/7] target/riscv: Support SXL32 on RV64 CPU Alistair Francis
2024-10-22 6:41 ` LIU Zhiwei
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