From: Deepak Gupta <debug@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
kito.cheng@sifive.com, Deepak Gupta <debug@rivosinc.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v16 19/20] disas/riscv: enable disassembly for compressed sspush/sspopchk
Date: Tue, 8 Oct 2024 15:50:09 -0700 [thread overview]
Message-ID: <20241008225010.1861630-20-debug@rivosinc.com> (raw)
In-Reply-To: <20241008225010.1861630-1-debug@rivosinc.com>
sspush and sspopchk have equivalent compressed encoding taken from zcmop.
cmop.1 is sspush x1 while cmop.5 is sspopchk x5. Due to unusual encoding
for both rs1 and rs2 from space bitfield, this required a new codec.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 19 ++++++++++++++++++-
disas/riscv.h | 1 +
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 0f9ecd8a14..d557c0cda8 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -982,6 +982,8 @@ typedef enum {
rv_op_ssrdp = 951,
rv_op_ssamoswap_w = 952,
rv_op_ssamoswap_d = 953,
+ rv_op_c_sspush = 954,
+ rv_op_c_sspopchk = 955,
} rv_op;
/* register names */
@@ -2248,6 +2250,10 @@ const rv_opcode_data rvi_opcode_data[] = {
{ "ssrdp", rv_codec_r, rv_fmt_rd, NULL, 0, 0, 0 },
{ "ssamoswap.w", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
{ "ssamoswap.d", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 },
+ { "c.sspush", rv_codec_cmop_ss, rv_fmt_rs2, NULL, rv_op_sspush,
+ rv_op_sspush, 0 },
+ { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk,
+ rv_op_sspopchk, 0 },
};
/* CSR names */
@@ -2608,7 +2614,13 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
if (dec->cfg->ext_zcmop) {
if ((((inst >> 2) & 0b111111) == 0b100000) &&
(((inst >> 11) & 0b11) == 0b0)) {
- op = rv_c_mop_1 + ((inst >> 8) & 0b111);
+ unsigned int cmop_code = 0;
+ cmop_code = ((inst >> 8) & 0b111);
+ op = rv_c_mop_1 + cmop_code;
+ if (dec->cfg->ext_zicfiss) {
+ op = (cmop_code == 0) ? rv_op_c_sspush : op;
+ op = (cmop_code == 2) ? rv_op_c_sspopchk : op;
+ }
break;
}
}
@@ -4929,6 +4941,11 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa)
case rv_codec_lp:
dec->imm = operand_lpl(inst);
break;
+ case rv_codec_cmop_ss:
+ dec->rd = rv_ireg_zero;
+ dec->rs1 = dec->rs2 = operand_crs1(inst);
+ dec->imm = 0;
+ break;
};
}
diff --git a/disas/riscv.h b/disas/riscv.h
index 4895c5a301..6a3b371cd3 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -167,6 +167,7 @@ typedef enum {
rv_codec_r2_imm2_imm5,
rv_codec_fli,
rv_codec_lp,
+ rv_codec_cmop_ss,
} rv_codec;
/* structures */
--
2.45.0
next prev parent reply other threads:[~2024-10-08 22:54 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-08 22:49 [PATCH v16 00/20] riscv support for control flow integrity extensions Deepak Gupta
2024-10-08 22:49 ` [PATCH v16 01/20] target/riscv: expose *envcfg csr and priv to qemu-user as well Deepak Gupta
2024-10-08 22:49 ` [PATCH v16 02/20] target/riscv: Add zicfilp extension Deepak Gupta
2024-10-08 22:49 ` [PATCH v16 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-10-08 22:49 ` [PATCH v16 04/20] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-10-29 3:25 ` Alistair Francis
2024-10-08 22:49 ` [PATCH v16 05/20] target/riscv: additional code information for sw check Deepak Gupta
2024-10-08 22:49 ` [PATCH v16 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-10-08 22:49 ` [PATCH v16 07/20] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-10-08 22:49 ` [PATCH v16 08/20] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-10-08 22:49 ` [PATCH v16 09/20] target/riscv: Expose zicfilp extension as a cpu property Deepak Gupta
2024-10-08 22:50 ` [PATCH v16 10/20] target/riscv: Add zicfiss extension Deepak Gupta
2024-10-08 22:50 ` [PATCH v16 11/20] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-10-08 22:50 ` [PATCH v16 12/20] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-10-08 22:50 ` [PATCH v16 13/20] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-10-29 4:12 ` Alistair Francis
2024-10-08 22:50 ` [PATCH v16 14/20] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-10-08 22:50 ` [PATCH v16 15/20] target/riscv: update `decode_save_opc` to store extra word2 Deepak Gupta
2024-10-08 22:50 ` [PATCH v16 16/20] target/riscv: implement zicfiss instructions Deepak Gupta
2024-10-08 22:50 ` [PATCH v16 17/20] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-10-08 22:50 ` [PATCH v16 18/20] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-10-08 22:50 ` Deepak Gupta [this message]
2024-10-08 22:50 ` [PATCH v16 20/20] target/riscv: Expose zicfiss extension as a cpu property Deepak Gupta
2024-10-29 4:33 ` [PATCH v16 00/20] riscv support for control flow integrity extensions Alistair Francis
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