From: Atish Patra <atishp@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: alexei.filippov@syntacore.com, Atish Patra <atishp@rivosinc.com>,
palmer@dabbelt.com, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com,
dbarboza@ventanamicro.com, alistair.francis@wdc.com
Subject: [PATCH RFC 03/10] target/riscv: Protect the hashtable modifications with a lock
Date: Wed, 09 Oct 2024 16:09:01 -0700 [thread overview]
Message-ID: <20241009-pmu_event_machine-v1-3-dcbd7a60e3ba@rivosinc.com> (raw)
In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com>
Add a read/write lock to protect the hashtable access operations
in multi-threaded scenario.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/pmu.c | 10 +++++++++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a63a29744c26..97e408b91219 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -496,6 +496,7 @@ struct ArchCPU {
uint32_t pmu_avail_ctrs;
/* Mapping of events to counters */
GHashTable *pmu_event_ctr_map;
+ pthread_rwlock_t pmu_map_lock;
const GPtrArray *decoders;
};
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index a88c321a6cad..21377518f4e0 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -271,12 +271,15 @@ static bool riscv_pmu_htable_lookup(RISCVCPU *cpu, uint32_t key,
GHashTable *table = cpu->pmu_event_ctr_map;
gpointer val_ptr;
- val_ptr = g_hash_table_lookup(table, GUINT_TO_POINTER(key));
+ pthread_rwlock_rdlock(&cpu->pmu_map_lock);
+ gpointer val_ptr = g_hash_table_lookup(table, GUINT_TO_POINTER(key));
if (!val_ptr) {
+ pthread_rwlock_unlock(&cpu->pmu_map_lock);
return false;
}
*value = GPOINTER_TO_UINT(val_ptr);
+ pthread_rwlock_unlock(&cpu->pmu_map_lock);
return true;
}
@@ -388,9 +391,11 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
* mapping.
*/
if (!value) {
+ pthread_rwlock_wrlock(&cpu->pmu_map_lock);
g_hash_table_foreach_remove(cpu->pmu_event_ctr_map,
pmu_remove_event_map,
GUINT_TO_POINTER(ctr_idx));
+ pthread_rwlock_unlock(&cpu->pmu_map_lock);
return 0;
}
@@ -410,8 +415,10 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
/* We don't support any raw events right now */
return -1;
}
+ pthread_rwlock_wrlock(&cpu->pmu_map_lock);
g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx),
GUINT_TO_POINTER(ctr_idx));
+ pthread_rwlock_unlock(&cpu->pmu_map_lock);
return 0;
}
@@ -597,4 +604,5 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp)
}
cpu->pmu_avail_ctrs = cpu->cfg.pmu_mask;
+ pthread_rwlock_init(&cpu->pmu_map_lock, NULL);
}
--
2.34.1
next prev parent reply other threads:[~2024-10-09 23:11 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-09 23:08 [PATCH RFC 00/10] Allow platform specific PMU event encoding Atish Patra
2024-10-09 23:08 ` [PATCH RFC 01/10] target/riscv: Fix the hpmevent mask Atish Patra
2024-10-09 23:09 ` [PATCH RFC 02/10] target/riscv: Introduce helper functions for pmu hashtable lookup Atish Patra
2024-10-10 12:04 ` Alexei Filippov
2024-10-09 23:09 ` Atish Patra [this message]
2024-10-09 23:09 ` [PATCH RFC 04/10] target/riscv: Use uint64 instead of uint as key Atish Patra
2024-10-09 23:09 ` [PATCH RFC 05/10] target/riscv: Rename the PMU events Atish Patra
2024-10-10 12:10 ` Alexei Filippov
2024-10-11 20:41 ` Atish Kumar Patra
2024-10-09 23:09 ` [PATCH RFC 06/10] target/riscv: Define PMU event related structures Atish Patra
2024-10-10 12:44 ` Alexei Filippov
2024-10-11 20:45 ` Atish Kumar Patra
2024-10-21 13:44 ` Aleksei Filippov
2024-10-22 12:58 ` Atish Kumar Patra
2024-11-20 14:25 ` Aleksei Filippov
2024-11-21 19:54 ` Atish Kumar Patra
2024-11-22 11:43 ` Aleksei Filippov
2024-11-22 17:36 ` Atish Kumar Patra
2024-10-09 23:09 ` [PATCH RFC 07/10] hw/riscv/virt.c : Disassociate virt PMU events Atish Patra
2024-10-09 23:09 ` [PATCH RFC 08/10] target/riscv: Update event mapping hashtable for invalid events Atish Patra
2024-10-09 23:09 ` [PATCH RFC 09/10] target/riscv : Use the new tlb fill event functions Atish Patra
2024-10-09 23:09 ` [PATCH RFC 10/10] hw/riscv/virt.c: Generate the PMU node from the machine Atish Patra
2024-10-10 12:51 ` [PATCH RFC 00/10] Allow platform specific PMU event encoding Alexei Filippov
2024-10-11 21:07 ` Atish Kumar Patra
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241009-pmu_event_machine-v1-3-dcbd7a60e3ba@rivosinc.com \
--to=atishp@rivosinc.com \
--cc=alexei.filippov@syntacore.com \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=dbarboza@ventanamicro.com \
--cc=liwei1518@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).