From: Atish Patra <atishp@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: alexei.filippov@syntacore.com, Atish Patra <atishp@rivosinc.com>,
palmer@dabbelt.com, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com,
dbarboza@ventanamicro.com, alistair.francis@wdc.com
Subject: [PATCH RFC 04/10] target/riscv: Use uint64 instead of uint as key
Date: Wed, 09 Oct 2024 16:09:02 -0700 [thread overview]
Message-ID: <20241009-pmu_event_machine-v1-4-dcbd7a60e3ba@rivosinc.com> (raw)
In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com>
The event ID can be a upto 56 bit value when sscofpmf is implemented.
Change the event to counter hashtable to store the keys as 64 bit value
instead of uint.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/pmu.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index 21377518f4e0..2531d4f1a9c1 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -265,14 +265,14 @@ static void riscv_pmu_cycle_update_priv(CPURISCVState *env,
counter_arr[env->priv] += delta;
}
-static bool riscv_pmu_htable_lookup(RISCVCPU *cpu, uint32_t key,
+static bool riscv_pmu_htable_lookup(RISCVCPU *cpu, uint64_t key,
uint32_t *value)
{
GHashTable *table = cpu->pmu_event_ctr_map;
gpointer val_ptr;
pthread_rwlock_rdlock(&cpu->pmu_map_lock);
- gpointer val_ptr = g_hash_table_lookup(table, GUINT_TO_POINTER(key));
+ val_ptr = g_hash_table_lookup(table, &key);
if (!val_ptr) {
pthread_rwlock_unlock(&cpu->pmu_map_lock);
return false;
@@ -378,9 +378,10 @@ static int64_t pmu_icount_ticks_to_ns(int64_t value)
int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
uint32_t ctr_idx)
{
- uint32_t event_idx;
+ uint64_t event_idx;
RISCVCPU *cpu = env_archcpu(env);
uint32_t mapped_ctr_idx;
+ gint64 *eid_ptr;
if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map) {
return -1;
@@ -415,8 +416,10 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
/* We don't support any raw events right now */
return -1;
}
+ eid_ptr = g_new(gint64, 1);
+ *eid_ptr = event_idx;
pthread_rwlock_wrlock(&cpu->pmu_map_lock);
- g_hash_table_insert(cpu->pmu_event_ctr_map, GUINT_TO_POINTER(event_idx),
+ g_hash_table_insert(cpu->pmu_event_ctr_map, eid_ptr,
GUINT_TO_POINTER(ctr_idx));
pthread_rwlock_unlock(&cpu->pmu_map_lock);
@@ -597,7 +600,8 @@ void riscv_pmu_init(RISCVCPU *cpu, Error **errp)
return;
}
- cpu->pmu_event_ctr_map = g_hash_table_new(g_direct_hash, g_direct_equal);
+ cpu->pmu_event_ctr_map = g_hash_table_new_full(g_int64_hash, g_int64_equal,
+ g_free, NULL);
if (!cpu->pmu_event_ctr_map) {
error_setg(errp, "Unable to allocate PMU event hash table");
return;
--
2.34.1
next prev parent reply other threads:[~2024-10-09 23:10 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-09 23:08 [PATCH RFC 00/10] Allow platform specific PMU event encoding Atish Patra
2024-10-09 23:08 ` [PATCH RFC 01/10] target/riscv: Fix the hpmevent mask Atish Patra
2024-10-09 23:09 ` [PATCH RFC 02/10] target/riscv: Introduce helper functions for pmu hashtable lookup Atish Patra
2024-10-10 12:04 ` Alexei Filippov
2024-10-09 23:09 ` [PATCH RFC 03/10] target/riscv: Protect the hashtable modifications with a lock Atish Patra
2024-10-09 23:09 ` Atish Patra [this message]
2024-10-09 23:09 ` [PATCH RFC 05/10] target/riscv: Rename the PMU events Atish Patra
2024-10-10 12:10 ` Alexei Filippov
2024-10-11 20:41 ` Atish Kumar Patra
2024-10-09 23:09 ` [PATCH RFC 06/10] target/riscv: Define PMU event related structures Atish Patra
2024-10-10 12:44 ` Alexei Filippov
2024-10-11 20:45 ` Atish Kumar Patra
2024-10-21 13:44 ` Aleksei Filippov
2024-10-22 12:58 ` Atish Kumar Patra
2024-11-20 14:25 ` Aleksei Filippov
2024-11-21 19:54 ` Atish Kumar Patra
2024-11-22 11:43 ` Aleksei Filippov
2024-11-22 17:36 ` Atish Kumar Patra
2024-10-09 23:09 ` [PATCH RFC 07/10] hw/riscv/virt.c : Disassociate virt PMU events Atish Patra
2024-10-09 23:09 ` [PATCH RFC 08/10] target/riscv: Update event mapping hashtable for invalid events Atish Patra
2024-10-09 23:09 ` [PATCH RFC 09/10] target/riscv : Use the new tlb fill event functions Atish Patra
2024-10-09 23:09 ` [PATCH RFC 10/10] hw/riscv/virt.c: Generate the PMU node from the machine Atish Patra
2024-10-10 12:51 ` [PATCH RFC 00/10] Allow platform specific PMU event encoding Alexei Filippov
2024-10-11 21:07 ` Atish Kumar Patra
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