From: Atish Patra <atishp@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: alexei.filippov@syntacore.com, Atish Patra <atishp@rivosinc.com>,
palmer@dabbelt.com, liwei1518@gmail.com,
zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com,
dbarboza@ventanamicro.com, alistair.francis@wdc.com
Subject: [PATCH RFC 08/10] target/riscv: Update event mapping hashtable for invalid events
Date: Wed, 09 Oct 2024 16:09:06 -0700 [thread overview]
Message-ID: <20241009-pmu_event_machine-v1-8-dcbd7a60e3ba@rivosinc.com> (raw)
In-Reply-To: <20241009-pmu_event_machine-v1-0-dcbd7a60e3ba@rivosinc.com>
If the software programs an invalid hpmevent or selects a invalid
counter mapping, the hashtable entry should be updated accordingly.
Otherwise, the user may get stale value from the old mapped counter.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/pmu.c | 39 +++++++++++++++++++++------------------
1 file changed, 21 insertions(+), 18 deletions(-)
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index 3235388c66e4..24c2fe82c247 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -387,39 +387,42 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
return -1;
}
- /*
- * Expected mhpmevent value is zero for reset case. Remove the current
- * mapping.
- */
- if (!value) {
- pthread_rwlock_wrlock(&cpu->pmu_map_lock);
- g_hash_table_foreach_remove(cpu->pmu_event_ctr_map,
- pmu_remove_event_map,
- GUINT_TO_POINTER(ctr_idx));
- pthread_rwlock_unlock(&cpu->pmu_map_lock);
- return 0;
- }
-
event_idx = value & MHPMEVENT_IDX_MASK;
if (riscv_pmu_htable_lookup(cpu, event_idx, &mapped_ctr_idx)) {
return 0;
}
for (i = 0; i < env->num_pmu_events; i++) {
- if (event_idx == env->pmu_events[i].event_id) {
+ if ((event_idx == env->pmu_events[i].event_id) &&
+ (BIT(ctr_idx) & env->pmu_events[i].counter_mask)) {
valid_event = true;
break;
}
}
- if (!valid_event) {
- return -1;
+ pthread_rwlock_wrlock(&cpu->pmu_map_lock);
+ /*
+ * Remove the current mapping in the following cases:
+ * 1. mhpmevent value is zero which indicates a reset case.
+ * 2. An invalid event is programmed for mapping to a counter.
+ */
+ if (!value || !valid_event) {
+ g_hash_table_foreach_remove(cpu->pmu_event_ctr_map,
+ pmu_remove_event_map,
+ GUINT_TO_POINTER(ctr_idx));
+ pthread_rwlock_unlock(&cpu->pmu_map_lock);
+ return 0;
}
+
eid_ptr = g_new(gint64, 1);
*eid_ptr = event_idx;
- pthread_rwlock_wrlock(&cpu->pmu_map_lock);
+ /*
+ * Insert operation will replace the value if the key exists
+ * As per the documentation, it will free the passed key is freed as well.
+ * No special handling is required for replace or key management.
+ */
g_hash_table_insert(cpu->pmu_event_ctr_map, eid_ptr,
- GUINT_TO_POINTER(ctr_idx));
+ GUINT_TO_POINTER(ctr_idx));
pthread_rwlock_unlock(&cpu->pmu_map_lock);
return 0;
--
2.34.1
next prev parent reply other threads:[~2024-10-09 23:10 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-09 23:08 [PATCH RFC 00/10] Allow platform specific PMU event encoding Atish Patra
2024-10-09 23:08 ` [PATCH RFC 01/10] target/riscv: Fix the hpmevent mask Atish Patra
2024-10-09 23:09 ` [PATCH RFC 02/10] target/riscv: Introduce helper functions for pmu hashtable lookup Atish Patra
2024-10-10 12:04 ` Alexei Filippov
2024-10-09 23:09 ` [PATCH RFC 03/10] target/riscv: Protect the hashtable modifications with a lock Atish Patra
2024-10-09 23:09 ` [PATCH RFC 04/10] target/riscv: Use uint64 instead of uint as key Atish Patra
2024-10-09 23:09 ` [PATCH RFC 05/10] target/riscv: Rename the PMU events Atish Patra
2024-10-10 12:10 ` Alexei Filippov
2024-10-11 20:41 ` Atish Kumar Patra
2024-10-09 23:09 ` [PATCH RFC 06/10] target/riscv: Define PMU event related structures Atish Patra
2024-10-10 12:44 ` Alexei Filippov
2024-10-11 20:45 ` Atish Kumar Patra
2024-10-21 13:44 ` Aleksei Filippov
2024-10-22 12:58 ` Atish Kumar Patra
2024-11-20 14:25 ` Aleksei Filippov
2024-11-21 19:54 ` Atish Kumar Patra
2024-11-22 11:43 ` Aleksei Filippov
2024-11-22 17:36 ` Atish Kumar Patra
2024-10-09 23:09 ` [PATCH RFC 07/10] hw/riscv/virt.c : Disassociate virt PMU events Atish Patra
2024-10-09 23:09 ` Atish Patra [this message]
2024-10-09 23:09 ` [PATCH RFC 09/10] target/riscv : Use the new tlb fill event functions Atish Patra
2024-10-09 23:09 ` [PATCH RFC 10/10] hw/riscv/virt.c: Generate the PMU node from the machine Atish Patra
2024-10-10 12:51 ` [PATCH RFC 00/10] Allow platform specific PMU event encoding Alexei Filippov
2024-10-11 21:07 ` Atish Kumar Patra
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