[PATCH RFC 09/10] target/riscv : Use the new tlb fill event functions

[Atish Patra <atishp@rivosinc.com>]

We have TLB related event call back available now. Invoke
them from generic cpu helper code so that other machines can
implement those as well in the future. The virt machine is
the only user for now though.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/cpu_helper.c | 21 +++++++--------------
 target/riscv/pmu.c        |  2 +-
 target/riscv/pmu.h        |  2 +-
 3 files changed, 9 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0f1655a221bd..5161fc86dbfe 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1295,23 +1295,16 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 
 static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
 {
-    enum virt_pmu_event_idx pmu_event_type;
+    uint64_t event_type = ULONG_MAX;
+    CPURISCVState *env = &cpu->env;
 
-    switch (access_type) {
-    case MMU_INST_FETCH:
-        pmu_event_type = VIRT_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
-        break;
-    case MMU_DATA_LOAD:
-        pmu_event_type = VIRT_PMU_EVENT_CACHE_DTLB_READ_MISS;
-        break;
-    case MMU_DATA_STORE:
-        pmu_event_type = VIRT_PMU_EVENT_CACHE_DTLB_WRITE_MISS;
-        break;
-    default:
-        return;
+    if (env->pmu_efuncs.get_tlb_access_id) {
+        event_type = env->pmu_efuncs.get_tlb_access_id(cpu, access_type);
     }
 
-    riscv_pmu_incr_ctr(cpu, pmu_event_type);
+    if (event_type != ULONG_MAX) {
+        riscv_pmu_incr_ctr(cpu, event_type);
+    }
 }
 
 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index 24c2fe82c247..e80f0f911fa3 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -274,7 +274,7 @@ void riscv_pmu_update_fixed_ctrs(CPURISCVState *env, target_ulong newpriv,
     riscv_pmu_icount_update_priv(env, newpriv, new_virt);
 }
 
-int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum virt_pmu_event_idx event_idx)
+int riscv_pmu_incr_ctr(RISCVCPU *cpu, uint64_t event_idx)
 {
     uint32_t ctr_idx;
     int ret;
diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
index 75a22d596b69..810ac2fae797 100644
--- a/target/riscv/pmu.h
+++ b/target/riscv/pmu.h
@@ -30,7 +30,7 @@ void riscv_pmu_timer_cb(void *priv);
 void riscv_pmu_init(RISCVCPU *cpu, Error **errp);
 int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
                                uint32_t ctr_idx);
-int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum virt_pmu_event_idx event_idx);
+int riscv_pmu_incr_ctr(RISCVCPU *cpu, uint64_t event_idx);
 void riscv_pmu_generate_fdt_node(void *fdt, uint32_t cmask, char *pmu_name);
 int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value,
                           uint32_t ctr_idx);

-- 
2.34.1