* [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge
@ 2024-10-10 21:49 Philippe Mathieu-Daudé
2024-10-10 21:49 ` [PATCH v2 01/16] target/mips: Declare mips_env_is_bigendian() in 'internal.h' Philippe Mathieu-Daudé
` (15 more replies)
0 siblings, 16 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:49 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno
Since v1:
- Addressed rth review comment (adding new patches)
Get vCPU endianness from CP0::BE bit.
Propagate endianness at the board level, using QOM property.
Remove target-specific endianness knowledge from target/.
Philippe Mathieu-Daudé (16):
target/mips: Declare mips_env_is_bigendian() in 'internal.h'
target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian()
target/mips: Introduce mo_endian_env() helper
target/mips: Replace MO_TE by mo_endian_env() in get_pte()
target/mips: Convert mips16e decr_and_load/store() macros to functions
target/mips: Factor mo_endian_rev() out of MXU code
target/mips: Explode MO_TExx -> MO_TE | MO_xx
target/mips: Rename unused sysemu argument of OP_LD_ATOMIC()
target/mips: Introduce mo_endian() helper
target/mips: Replace MO_TE by mo_endian()
target/mips: Have gen_addiupc() expand $pc during translation
target/mips: Use gen_op_addr_addi() when possible
target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl()
target/mips: Expose MIPSCPU::is_big_endian property
hw/mips/cps: Set the vCPU 'cpu-big-endian' property
hw/mips: Have mips_cpu_create_with_clock() take an endianness argument
include/hw/mips/cps.h | 1 +
target/mips/cpu.h | 7 +-
target/mips/internal.h | 10 ++
target/mips/tcg/translate.h | 13 +-
hw/mips/cps.c | 4 +
hw/mips/fuloong2e.c | 2 +-
hw/mips/jazz.c | 2 +-
hw/mips/loongson3_virt.c | 2 +-
hw/mips/malta.c | 5 +-
hw/mips/mipssim.c | 2 +-
target/mips/cpu.c | 17 +-
target/mips/tcg/ldst_helper.c | 15 +-
target/mips/tcg/msa_helper.c | 2 +-
target/mips/tcg/mxu_translate.c | 18 +-
target/mips/tcg/sysemu/tlb_helper.c | 2 +-
target/mips/tcg/translate.c | 193 ++++++++++------------
target/mips/tcg/tx79_translate.c | 8 +-
target/mips/tcg/micromips_translate.c.inc | 34 ++--
target/mips/tcg/mips16e_translate.c.inc | 118 +++++++------
target/mips/tcg/nanomips_translate.c.inc | 150 +++++++----------
20 files changed, 293 insertions(+), 312 deletions(-)
--
2.45.2
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v2 01/16] target/mips: Declare mips_env_is_bigendian() in 'internal.h'
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
@ 2024-10-10 21:49 ` Philippe Mathieu-Daudé
2024-10-13 15:51 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 02/16] target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian() Philippe Mathieu-Daudé
` (14 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:49 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno
In order to re-use cpu_is_bigendian(), declare it on "internal.h"
after renaming it as mips_env_is_bigendian().
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20241004162118.84570-6-philmd@linaro.org>
---
target/mips/internal.h | 5 +++++
target/mips/tcg/ldst_helper.c | 15 +++++----------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index a9a22ea00ec..84c8e5e1ae7 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -225,6 +225,11 @@ static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
}
}
+static inline bool mips_env_is_bigendian(CPUMIPSState *env)
+{
+ return extract32(env->CP0_Config0, CP0C0_BE, 1);
+}
+
static inline void restore_pamask(CPUMIPSState *env)
{
if (env->hflags & MIPS_HFLAG_ELPA) {
diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
index 97056d00a27..f92a923d7ad 100644
--- a/target/mips/tcg/ldst_helper.c
+++ b/target/mips/tcg/ldst_helper.c
@@ -53,11 +53,6 @@ HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong))
#endif /* !CONFIG_USER_ONLY */
-static inline bool cpu_is_bigendian(CPUMIPSState *env)
-{
- return extract32(env->CP0_Config0, CP0C0_BE, 1);
-}
-
static inline target_ulong get_lmask(CPUMIPSState *env,
target_ulong value, unsigned bits)
{
@@ -65,7 +60,7 @@ static inline target_ulong get_lmask(CPUMIPSState *env,
value &= mask;
- if (!cpu_is_bigendian(env)) {
+ if (!mips_env_is_bigendian(env)) {
value ^= mask;
}
@@ -76,7 +71,7 @@ void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
int mem_idx)
{
target_ulong lmask = get_lmask(env, arg2, 32);
- int dir = cpu_is_bigendian(env) ? 1 : -1;
+ int dir = mips_env_is_bigendian(env) ? 1 : -1;
cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
@@ -100,7 +95,7 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
int mem_idx)
{
target_ulong lmask = get_lmask(env, arg2, 32);
- int dir = cpu_is_bigendian(env) ? 1 : -1;
+ int dir = mips_env_is_bigendian(env) ? 1 : -1;
cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
@@ -130,7 +125,7 @@ void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
int mem_idx)
{
target_ulong lmask = get_lmask(env, arg2, 64);
- int dir = cpu_is_bigendian(env) ? 1 : -1;
+ int dir = mips_env_is_bigendian(env) ? 1 : -1;
cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
@@ -174,7 +169,7 @@ void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
int mem_idx)
{
target_ulong lmask = get_lmask(env, arg2, 64);
- int dir = cpu_is_bigendian(env) ? 1 : -1;
+ int dir = mips_env_is_bigendian(env) ? 1 : -1;
cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 02/16] target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian()
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
2024-10-10 21:49 ` [PATCH v2 01/16] target/mips: Declare mips_env_is_bigendian() in 'internal.h' Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-13 15:52 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 03/16] target/mips: Introduce mo_endian_env() helper Philippe Mathieu-Daudé
` (13 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
Methods using the 'cpu_' prefix usually take a (Arch)CPUState
argument. Since this method takes a DisasContext argument,
rename it as disas_is_bigendian().
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/translate.h | 2 +-
target/mips/tcg/translate.c | 6 +++---
target/mips/tcg/nanomips_translate.c.inc | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 2b6646b339b..e81a8d5eb9b 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -235,7 +235,7 @@ bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn);
static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
{ return FUNC(ctx, a, __VA_ARGS__); }
-static inline bool cpu_is_bigendian(DisasContext *ctx)
+static inline bool disas_is_bigendian(DisasContext *ctx)
{
return extract32(ctx->CP0_Config0, CP0C0_BE, 1);
}
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 333469b268e..9a855e6547e 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -2010,7 +2010,7 @@ static void gen_lxl(DisasContext *ctx, TCGv reg, TCGv addr,
*/
tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB);
tcg_gen_andi_tl(t1, addr, sizem1);
- if (!cpu_is_bigendian(ctx)) {
+ if (!disas_is_bigendian(ctx)) {
tcg_gen_xori_tl(t1, t1, sizem1);
}
tcg_gen_shli_tl(t1, t1, 3);
@@ -2037,7 +2037,7 @@ static void gen_lxr(DisasContext *ctx, TCGv reg, TCGv addr,
*/
tcg_gen_qemu_ld_tl(t1, addr, mem_idx, MO_UB);
tcg_gen_andi_tl(t1, addr, sizem1);
- if (cpu_is_bigendian(ctx)) {
+ if (disas_is_bigendian(ctx)) {
tcg_gen_xori_tl(t1, t1, sizem1);
}
tcg_gen_shli_tl(t1, t1, 3);
@@ -10856,7 +10856,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
tcg_gen_br(l2);
gen_set_label(l1);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2);
- if (cpu_is_bigendian(ctx)) {
+ if (disas_is_bigendian(ctx)) {
gen_load_fpr32(ctx, fp, fs);
gen_load_fpr32h(ctx, fph, ft);
gen_store_fpr32h(ctx, fp, fd);
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index b4b746d4187..6e0df1a8c36 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -999,7 +999,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
gen_base_offset_addr(ctx, taddr, base, offset);
tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ | MO_ALIGN);
- if (cpu_is_bigendian(ctx)) {
+ if (disas_is_bigendian(ctx)) {
tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
} else {
tcg_gen_extr_i64_tl(tmp1, tmp2, tval);
@@ -1031,7 +1031,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
gen_load_gpr(tmp1, reg1);
gen_load_gpr(tmp2, reg2);
- if (cpu_is_bigendian(ctx)) {
+ if (disas_is_bigendian(ctx)) {
tcg_gen_concat_tl_i64(tval, tmp2, tmp1);
} else {
tcg_gen_concat_tl_i64(tval, tmp1, tmp2);
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 03/16] target/mips: Introduce mo_endian_env() helper
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
2024-10-10 21:49 ` [PATCH v2 01/16] target/mips: Declare mips_env_is_bigendian() in 'internal.h' Philippe Mathieu-Daudé
2024-10-10 21:50 ` [PATCH v2 02/16] target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian() Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-13 15:52 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 04/16] target/mips: Replace MO_TE by mo_endian_env() in get_pte() Philippe Mathieu-Daudé
` (12 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno
Introduce mo_endian_env() which returns the endian
MemOp corresponding to the vCPU env.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/mips/internal.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 84c8e5e1ae7..91c786cff8a 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -230,6 +230,11 @@ static inline bool mips_env_is_bigendian(CPUMIPSState *env)
return extract32(env->CP0_Config0, CP0C0_BE, 1);
}
+static inline MemOp mo_endian_env(CPUMIPSState *env)
+{
+ return mips_env_is_bigendian(env) ? MO_BE : MO_LE;
+}
+
static inline void restore_pamask(CPUMIPSState *env)
{
if (env->hflags & MIPS_HFLAG_ELPA) {
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 04/16] target/mips: Replace MO_TE by mo_endian_env() in get_pte()
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2024-10-10 21:50 ` [PATCH v2 03/16] target/mips: Introduce mo_endian_env() helper Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-13 15:53 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 05/16] target/mips: Convert mips16e decr_and_load/store() macros to functions Philippe Mathieu-Daudé
` (11 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno
Replace compile-time MO_TE evaluation by runtime mo_endian_env()
one, which expand target endianness from vCPU env.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/mips/tcg/sysemu/tlb_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index 3836137750e..e98bb959517 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -601,7 +601,7 @@ static bool get_pte(CPUMIPSState *env, uint64_t vaddr, MemOp op,
return false;
}
- oi = make_memop_idx(op | MO_TE, ptw_mmu_idx);
+ oi = make_memop_idx(op | mo_endian_env(env), ptw_mmu_idx);
if (op == MO_64) {
*pte = cpu_ldq_mmu(env, vaddr, oi, 0);
} else {
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 05/16] target/mips: Convert mips16e decr_and_load/store() macros to functions
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2024-10-10 21:50 ` [PATCH v2 04/16] target/mips: Replace MO_TE by mo_endian_env() in get_pte() Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-10 21:50 ` [PATCH v2 06/16] target/mips: Factor mo_endian_rev() out of MXU code Philippe Mathieu-Daudé
` (10 subsequent siblings)
15 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
Functions are easier to rework than macros. Besides,
there is no gain here in inlining these.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/mips16e_translate.c.inc | 101 +++++++++++++-----------
1 file changed, 53 insertions(+), 48 deletions(-)
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index 5cffe0e412d..31bc14f9ca6 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -122,11 +122,23 @@ enum {
static int xlat(int r)
{
- static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
+ static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
return map[r];
}
+static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0)
+{
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ tcg_gen_movi_tl(t2, -4);
+ gen_op_addr_add(ctx, t0, t0, t2);
+ gen_load_gpr(t1, regidx);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
+}
+
static void gen_mips16_save(DisasContext *ctx,
int xsregs, int aregs,
int do_ra, int do_s0, int do_s1,
@@ -196,46 +208,38 @@ static void gen_mips16_save(DisasContext *ctx,
gen_load_gpr(t0, 29);
-#define DECR_AND_STORE(reg) do { \
- tcg_gen_movi_tl(t2, -4); \
- gen_op_addr_add(ctx, t0, t0, t2); \
- gen_load_gpr(t1, reg); \
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | \
- ctx->default_tcg_memop_mask); \
- } while (0)
-
if (do_ra) {
- DECR_AND_STORE(31);
+ decr_and_store(ctx, 31, t0);
}
switch (xsregs) {
case 7:
- DECR_AND_STORE(30);
+ decr_and_store(ctx, 30, t0);
/* Fall through */
case 6:
- DECR_AND_STORE(23);
+ decr_and_store(ctx, 23, t0);
/* Fall through */
case 5:
- DECR_AND_STORE(22);
+ decr_and_store(ctx, 22, t0);
/* Fall through */
case 4:
- DECR_AND_STORE(21);
+ decr_and_store(ctx, 21, t0);
/* Fall through */
case 3:
- DECR_AND_STORE(20);
+ decr_and_store(ctx, 20, t0);
/* Fall through */
case 2:
- DECR_AND_STORE(19);
+ decr_and_store(ctx, 19, t0);
/* Fall through */
case 1:
- DECR_AND_STORE(18);
+ decr_and_store(ctx, 18, t0);
}
if (do_s1) {
- DECR_AND_STORE(17);
+ decr_and_store(ctx, 17, t0);
}
if (do_s0) {
- DECR_AND_STORE(16);
+ decr_and_store(ctx, 16, t0);
}
switch (aregs) {
@@ -270,23 +274,34 @@ static void gen_mips16_save(DisasContext *ctx,
}
if (astatic > 0) {
- DECR_AND_STORE(7);
+ decr_and_store(ctx, 7, t0);
if (astatic > 1) {
- DECR_AND_STORE(6);
+ decr_and_store(ctx, 6, t0);
if (astatic > 2) {
- DECR_AND_STORE(5);
+ decr_and_store(ctx, 5, t0);
if (astatic > 3) {
- DECR_AND_STORE(4);
+ decr_and_store(ctx, 4, t0);
}
}
}
}
-#undef DECR_AND_STORE
tcg_gen_movi_tl(t2, -framesize);
gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
}
+static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0)
+{
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ tcg_gen_movi_tl(t2, -4);
+ gen_op_addr_add(ctx, t0, t0, t2);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL |
+ ctx->default_tcg_memop_mask);
+ gen_store_gpr(t1, regidx);
+}
+
static void gen_mips16_restore(DisasContext *ctx,
int xsregs, int aregs,
int do_ra, int do_s0, int do_s1,
@@ -294,52 +309,43 @@ static void gen_mips16_restore(DisasContext *ctx,
{
int astatic;
TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
tcg_gen_movi_tl(t2, framesize);
gen_op_addr_add(ctx, t0, cpu_gpr[29], t2);
-#define DECR_AND_LOAD(reg) do { \
- tcg_gen_movi_tl(t2, -4); \
- gen_op_addr_add(ctx, t0, t0, t2); \
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | \
- ctx->default_tcg_memop_mask); \
- gen_store_gpr(t1, reg); \
- } while (0)
-
if (do_ra) {
- DECR_AND_LOAD(31);
+ decr_and_load(ctx, 31, t0);
}
switch (xsregs) {
case 7:
- DECR_AND_LOAD(30);
+ decr_and_load(ctx, 30, t0);
/* Fall through */
case 6:
- DECR_AND_LOAD(23);
+ decr_and_load(ctx, 23, t0);
/* Fall through */
case 5:
- DECR_AND_LOAD(22);
+ decr_and_load(ctx, 22, t0);
/* Fall through */
case 4:
- DECR_AND_LOAD(21);
+ decr_and_load(ctx, 21, t0);
/* Fall through */
case 3:
- DECR_AND_LOAD(20);
+ decr_and_load(ctx, 20, t0);
/* Fall through */
case 2:
- DECR_AND_LOAD(19);
+ decr_and_load(ctx, 19, t0);
/* Fall through */
case 1:
- DECR_AND_LOAD(18);
+ decr_and_load(ctx, 18, t0);
}
if (do_s1) {
- DECR_AND_LOAD(17);
+ decr_and_load(ctx, 17, t0);
}
if (do_s0) {
- DECR_AND_LOAD(16);
+ decr_and_load(ctx, 16, t0);
}
switch (aregs) {
@@ -374,18 +380,17 @@ static void gen_mips16_restore(DisasContext *ctx,
}
if (astatic > 0) {
- DECR_AND_LOAD(7);
+ decr_and_load(ctx, 7, t0);
if (astatic > 1) {
- DECR_AND_LOAD(6);
+ decr_and_load(ctx, 6, t0);
if (astatic > 2) {
- DECR_AND_LOAD(5);
+ decr_and_load(ctx, 5, t0);
if (astatic > 3) {
- DECR_AND_LOAD(4);
+ decr_and_load(ctx, 4, t0);
}
}
}
}
-#undef DECR_AND_LOAD
tcg_gen_movi_tl(t2, framesize);
gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 06/16] target/mips: Factor mo_endian_rev() out of MXU code
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2024-10-10 21:50 ` [PATCH v2 05/16] target/mips: Convert mips16e decr_and_load/store() macros to functions Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-13 15:59 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 07/16] target/mips: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
` (9 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
Instead of swapping the reversed target endianness
using MO_BSWAP, directly return the correct endianness.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/translate.h | 5 +++++
target/mips/tcg/mxu_translate.c | 8 ++++----
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index e81a8d5eb9b..c55f90e741b 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -240,4 +240,9 @@ static inline bool disas_is_bigendian(DisasContext *ctx)
return extract32(ctx->CP0_Config0, CP0C0_BE, 1);
}
+static inline MemOp mo_endian_rev(DisasContext *dc, bool reversed)
+{
+ return disas_is_bigendian(dc) ^ reversed ? MO_BE : MO_LE;
+}
+
#endif
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index c517258ac5a..dd512ce7a48 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -1533,7 +1533,7 @@ static void gen_mxu_s32ldxx(DisasContext *ctx, bool reversed, bool postinc)
tcg_gen_add_tl(t0, t0, t1);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,
- (MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
+ MO_SL | mo_endian_rev(ctx, reversed) |
ctx->default_tcg_memop_mask);
gen_store_mxu_gpr(t1, XRa);
@@ -1569,7 +1569,7 @@ static void gen_mxu_s32stxx(DisasContext *ctx, bool reversed, bool postinc)
gen_load_mxu_gpr(t1, XRa);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- (MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
+ MO_SL | mo_endian_rev(ctx, reversed) |
ctx->default_tcg_memop_mask);
if (postinc) {
@@ -1605,7 +1605,7 @@ static void gen_mxu_s32ldxvx(DisasContext *ctx, bool reversed,
tcg_gen_add_tl(t0, t0, t1);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,
- (MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
+ MO_SL | mo_endian_rev(ctx, reversed) |
ctx->default_tcg_memop_mask);
gen_store_mxu_gpr(t1, XRa);
@@ -1675,7 +1675,7 @@ static void gen_mxu_s32stxvx(DisasContext *ctx, bool reversed,
gen_load_mxu_gpr(t1, XRa);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- (MO_TESL ^ (reversed ? MO_BSWAP : 0)) |
+ MO_SL | mo_endian_rev(ctx, reversed) |
ctx->default_tcg_memop_mask);
if (postinc) {
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 07/16] target/mips: Explode MO_TExx -> MO_TE | MO_xx
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2024-10-10 21:50 ` [PATCH v2 06/16] target/mips: Factor mo_endian_rev() out of MXU code Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-13 16:00 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 08/16] target/mips: Rename unused sysemu argument of OP_LD_ATOMIC() Philippe Mathieu-Daudé
` (8 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno
Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/mips); \
done
manually remove superfluous parenthesis in nanoMIPS gen_save().
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/translate.c | 120 +++++++++++-----------
target/mips/tcg/tx79_translate.c | 8 +-
target/mips/tcg/micromips_translate.c.inc | 22 ++--
target/mips/tcg/mips16e_translate.c.inc | 10 +-
target/mips/tcg/nanomips_translate.c.inc | 32 +++---
5 files changed, 96 insertions(+), 96 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 9a855e6547e..c776c0fede9 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1964,9 +1964,9 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \
}
#endif
-OP_LD_ATOMIC(ll, MO_TESL);
+OP_LD_ATOMIC(ll, MO_TE | MO_SL);
#if defined(TARGET_MIPS64)
-OP_LD_ATOMIC(lld, MO_TEUQ);
+OP_LD_ATOMIC(lld, MO_TE | MO_UQ);
#endif
#undef OP_LD_ATOMIC
@@ -2073,12 +2073,12 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_LWU:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUL |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
case OPC_LD:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2090,33 +2090,33 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LDL:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxl(ctx, t1, t0, mem_idx, MO_TEUQ);
+ gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UQ);
gen_store_gpr(t1, rt);
break;
case OPC_LDR:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxr(ctx, t1, t0, mem_idx, MO_TEUQ);
+ gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UQ);
gen_store_gpr(t1, rt);
break;
case OPC_LDPC:
t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ);
gen_store_gpr(t0, rt);
break;
#endif
case OPC_LWPC:
t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL);
gen_store_gpr(t0, rt);
break;
case OPC_LWE:
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_LW:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2124,7 +2124,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_LH:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESW |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2132,7 +2132,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_LHU:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUW |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2156,7 +2156,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LWL:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxl(ctx, t1, t0, mem_idx, MO_TEUL);
+ gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UL);
tcg_gen_ext32s_tl(t1, t1);
gen_store_gpr(t1, rt);
break;
@@ -2166,7 +2166,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LWR:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxr(ctx, t1, t0, mem_idx, MO_TEUL);
+ gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UL);
tcg_gen_ext32s_tl(t1, t1);
gen_store_gpr(t1, rt);
break;
@@ -2194,7 +2194,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_SD:
- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
break;
case OPC_SDL:
@@ -2208,14 +2208,14 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_SW:
- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
break;
case OPC_SHE:
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_SH:
- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TEUW |
+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UW |
ctx->default_tcg_memop_mask);
break;
case OPC_SBE:
@@ -2281,7 +2281,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
case OPC_LWC1:
{
TCGv_i32 fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_fpr32(ctx, fp0, ft);
}
@@ -2290,14 +2290,14 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, ft);
- tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
}
break;
case OPC_LDC1:
{
TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, fp0, ft);
}
@@ -2306,7 +2306,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, ft);
- tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
}
break;
@@ -2987,14 +2987,14 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
case R6_OPC_LWPC:
offset = sextract32(ctx->opcode << 2, 0, 21);
addr = addr_add(ctx, pc, offset);
- gen_r6_ld(addr, rs, ctx->mem_idx, MO_TESL);
+ gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_SL);
break;
#if defined(TARGET_MIPS64)
case OPC_LWUPC:
check_mips_64(ctx);
offset = sextract32(ctx->opcode << 2, 0, 21);
addr = addr_add(ctx, pc, offset);
- gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUL);
+ gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UL);
break;
#endif
default:
@@ -3021,7 +3021,7 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
check_mips_64(ctx);
offset = sextract32(ctx->opcode << 3, 0, 21);
addr = addr_add(ctx, (pc & ~0x7), offset);
- gen_r6_ld(addr, rs, ctx->mem_idx, MO_TEUQ);
+ gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UQ);
break;
#endif
default:
@@ -4160,10 +4160,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
case OPC_GSLQ:
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rt);
gen_store_gpr(t0, lsq_rt1);
@@ -4172,10 +4172,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
check_cp1_enabled(ctx);
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, t1, rt);
gen_store_fpr64(ctx, t0, lsq_rt1);
@@ -4184,11 +4184,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
gen_load_gpr(t1, lsq_rt1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
break;
case OPC_GSSQC1:
@@ -4196,11 +4196,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
gen_load_fpr64(ctx, t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
gen_load_fpr64(ctx, t1, lsq_rt1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
@@ -4213,7 +4213,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt);
t1 = tcg_temp_new();
tcg_gen_ext_i32_tl(t1, fp0);
- gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUL);
+ gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL);
tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(ctx, fp0, rt);
break;
@@ -4224,7 +4224,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt);
t1 = tcg_temp_new();
tcg_gen_ext_i32_tl(t1, fp0);
- gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUL);
+ gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL);
tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(ctx, fp0, rt);
break;
@@ -4234,7 +4234,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_base_offset_addr(ctx, t0, rs, shf_offset);
t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt);
- gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TEUQ);
+ gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_fpr64(ctx, t1, rt);
break;
case OPC_GSLDRC1:
@@ -4242,7 +4242,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_base_offset_addr(ctx, t0, rs, shf_offset);
t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt);
- gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TEUQ);
+ gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_fpr64(ctx, t1, rt);
break;
#endif
@@ -4360,7 +4360,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
gen_store_gpr(t0, rt);
break;
case OPC_GSLHX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -4369,7 +4369,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -4379,7 +4379,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -4390,7 +4390,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_fpr32(ctx, fp0, rt);
break;
@@ -4400,7 +4400,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, t0, rt);
break;
@@ -4413,34 +4413,34 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
case OPC_GSSHX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UW |
ctx->default_tcg_memop_mask);
break;
case OPC_GSSWX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
break;
#if defined(TARGET_MIPS64)
case OPC_GSSDX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
case OPC_GSSWXC1:
fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, rt);
- tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
break;
#if defined(TARGET_MIPS64)
case OPC_GSSDXC1:
t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt);
- tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
@@ -10779,7 +10779,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL);
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(ctx, fp0, fd);
}
@@ -10789,7 +10789,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
check_cp1_registers(ctx, fd);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10799,7 +10799,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10808,7 +10808,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL);
}
break;
case OPC_SDXC1:
@@ -10817,7 +10817,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
}
break;
case OPC_SUXC1:
@@ -10826,7 +10826,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
}
break;
}
@@ -11476,7 +11476,7 @@ void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
gen_op_addr_add(ctx, t0, t1, t0);
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL);
gen_store_gpr(t1, rd);
}
@@ -11567,16 +11567,16 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
gen_store_gpr(t0, rd);
break;
case OPC_LHX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW);
gen_store_gpr(t0, rd);
break;
case OPC_LWX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL);
gen_store_gpr(t0, rd);
break;
#if defined(TARGET_MIPS64)
case OPC_LDX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_gpr(t0, rd);
break;
#endif
@@ -13719,7 +13719,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
}
break;
case R6_OPC_SC:
- gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
+ gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false);
break;
case R6_OPC_LL:
gen_ld(ctx, op1, rt, rs, imm);
@@ -13765,7 +13765,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
#endif
#if defined(TARGET_MIPS64)
case R6_OPC_SCD:
- gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false);
+ gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false);
break;
case R6_OPC_LLD:
gen_ld(ctx, op1, rt, rs, imm);
@@ -14448,7 +14448,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
return;
case OPC_SCE:
check_cp0_enabled(ctx);
- gen_st_cond(ctx, rt, rs, imm, MO_TESL, true);
+ gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, true);
return;
case OPC_CACHEE:
check_eva(ctx);
@@ -14912,7 +14912,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
- gen_st_cond(ctx, rt, rs, imm, MO_TESL, false);
+ gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false);
break;
case OPC_CACHE:
check_cp0_enabled(ctx);
@@ -15191,7 +15191,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
check_insn_opc_user_only(ctx, INSN_R5900);
}
check_mips_64(ctx);
- gen_st_cond(ctx, rt, rs, imm, MO_TEUQ, false);
+ gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false);
break;
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
if (ctx->insn_flags & ISA_MIPS_R6) {
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index dd6fb8a7bd7..1d290b86a98 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -340,12 +340,12 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)
tcg_gen_andi_tl(addr, addr, ~0xf);
/* Lower half */
- tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_gpr(t0, a->rt);
/* Upper half */
tcg_gen_addi_i64(addr, addr, 8);
- tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
gen_store_gpr_hi(t0, a->rt);
return true;
}
@@ -364,12 +364,12 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a)
/* Lower half */
gen_load_gpr(t0, a->rt);
- tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
/* Upper half */
tcg_gen_addi_i64(addr, addr, 8);
gen_load_gpr_hi(t0, a->rt);
- tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
return true;
}
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 75108317019..343d64a0e85 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -977,23 +977,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx);
return;
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
break;
case SWP:
gen_load_gpr(t1, rd);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
break;
#ifdef TARGET_MIPS64
@@ -1002,23 +1002,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx);
return;
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
break;
case SDP:
gen_load_gpr(t1, rd);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
@@ -2572,13 +2572,13 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st(ctx, mips32_op, rt, rs, offset);
break;
case SC:
- gen_st_cond(ctx, rt, rs, offset, MO_TESL, false);
+ gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, false);
break;
#if defined(TARGET_MIPS64)
case SCD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- gen_st_cond(ctx, rt, rs, offset, MO_TEUQ, false);
+ gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_UQ, false);
break;
#endif
case LD_EVA:
@@ -2659,7 +2659,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_SHE;
goto do_st_lr;
case SCE:
- gen_st_cond(ctx, rt, rs, offset, MO_TESL, true);
+ gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, true);
break;
case SWE:
mips32_op = OPC_SWE;
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index 31bc14f9ca6..6983636acbf 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -135,7 +135,7 @@ static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0)
tcg_gen_movi_tl(t2, -4);
gen_op_addr_add(ctx, t0, t0, t2);
gen_load_gpr(t1, regidx);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
}
@@ -184,25 +184,25 @@ static void gen_mips16_save(DisasContext *ctx,
case 4:
gen_base_offset_addr(ctx, t0, 29, 12);
gen_load_gpr(t1, 7);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
/* Fall through */
case 3:
gen_base_offset_addr(ctx, t0, 29, 8);
gen_load_gpr(t1, 6);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
/* Fall through */
case 2:
gen_base_offset_addr(ctx, t0, 29, 4);
gen_load_gpr(t1, 5);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
/* Fall through */
case 1:
gen_base_offset_addr(ctx, t0, 29, 0);
gen_load_gpr(t1, 4);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
ctx->default_tcg_memop_mask);
}
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index 6e0df1a8c36..c79c77b882d 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
TCGv tmp2 = tcg_temp_new();
gen_base_offset_addr(ctx, taddr, base, offset);
- tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ | MO_ALIGN);
+ tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TE | MO_UQ | MO_ALIGN);
if (disas_is_bigendian(ctx)) {
tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
} else {
@@ -1075,7 +1075,7 @@ static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count,
gen_base_offset_addr(ctx, va, 29, this_offset);
gen_load_gpr(t0, this_rt);
tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx,
- (MO_TEUL | ctx->default_tcg_memop_mask));
+ MO_TE | MO_UL | ctx->default_tcg_memop_mask);
counter++;
}
@@ -1095,7 +1095,7 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f);
int this_offset = u - ((counter + 1) << 2);
gen_base_offset_addr(ctx, va, 29, this_offset);
- tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
tcg_gen_ext32s_tl(t0, t0);
gen_store_gpr(t0, this_rt);
@@ -2647,13 +2647,13 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
case NM_LHX:
/*case NM_LHXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TESW | ctx->default_tcg_memop_mask);
+ MO_TE | MO_SW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_LWX:
/*case NM_LWXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TESL | ctx->default_tcg_memop_mask);
+ MO_TE | MO_SL | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_LBUX:
@@ -2663,7 +2663,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
case NM_LHUX:
/*case NM_LHUXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TEUW | ctx->default_tcg_memop_mask);
+ MO_TE | MO_UW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_SBX:
@@ -2676,14 +2676,14 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
check_nms(ctx);
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TEUW | ctx->default_tcg_memop_mask);
+ MO_TE | MO_UW | ctx->default_tcg_memop_mask);
break;
case NM_SWX:
/*case NM_SWXS:*/
check_nms(ctx);
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TEUL | ctx->default_tcg_memop_mask);
+ MO_TE | MO_UL | ctx->default_tcg_memop_mask);
break;
case NM_LWC1X:
/*case NM_LWC1XS:*/
@@ -3737,7 +3737,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
tcg_gen_movi_tl(t0, addr);
tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx,
- MO_TESL | ctx->default_tcg_memop_mask);
+ MO_TE | MO_SL | ctx->default_tcg_memop_mask);
}
break;
case NM_SWPC48:
@@ -3754,7 +3754,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TEUL | ctx->default_tcg_memop_mask);
+ MO_TE | MO_UL | ctx->default_tcg_memop_mask);
}
break;
default:
@@ -4132,13 +4132,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
switch (extract32(ctx->opcode, 11, 4)) {
case NM_UALH:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW |
MO_UNALN);
gen_store_gpr(t0, rt);
break;
case NM_UASH:
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UW |
MO_UNALN);
break;
}
@@ -4161,7 +4161,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_P_SC:
switch (ctx->opcode & 0x03) {
case NM_SC:
- gen_st_cond(ctx, rt, rs, s, MO_TESL, false);
+ gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, false);
break;
case NM_SCWP:
check_xnp(ctx);
@@ -4274,7 +4274,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
check_xnp(ctx);
check_eva(ctx);
check_cp0_enabled(ctx);
- gen_st_cond(ctx, rt, rs, s, MO_TESL, true);
+ gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, true);
break;
case NM_SCWPE:
check_xnp(ctx);
@@ -4317,7 +4317,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
switch (extract32(ctx->opcode, 11, 1)) {
case NM_LWM:
tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx,
- memop | MO_TESL);
+ memop | MO_TE | MO_SL);
gen_store_gpr(t1, this_rt);
if ((this_rt == rs) &&
(counter != (count - 1))) {
@@ -4328,7 +4328,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
this_rt = (rt == 0) ? 0 : this_rt;
gen_load_gpr(t1, this_rt);
tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx,
- memop | MO_TEUL);
+ memop | MO_TE | MO_UL);
break;
}
counter++;
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 08/16] target/mips: Rename unused sysemu argument of OP_LD_ATOMIC()
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2024-10-10 21:50 ` [PATCH v2 07/16] target/mips: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-13 16:01 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 09/16] target/mips: Introduce mo_endian() helper Philippe Mathieu-Daudé
` (7 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno
In commit 6d0cad12594 ("target/mips: Finish conversion to
tcg_gen_qemu_{ld,st}_*") we renamed the argument of the user
definition. Rename the system part for coherency. Since the
argument is ignored, prefix with 'ignored_'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index c776c0fede9..ebaefe39ed3 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1957,7 +1957,7 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
tcg_gen_st_tl(ret, tcg_env, offsetof(CPUMIPSState, llval)); \
}
#else
-#define OP_LD_ATOMIC(insn, fname) \
+#define OP_LD_ATOMIC(insn, ignored_memop) \
static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
DisasContext *ctx) \
{ \
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 09/16] target/mips: Introduce mo_endian() helper
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2024-10-10 21:50 ` [PATCH v2 08/16] target/mips: Rename unused sysemu argument of OP_LD_ATOMIC() Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-13 16:01 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 10/16] target/mips: Replace MO_TE by mo_endian() Philippe Mathieu-Daudé
` (6 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno
Introduce mo_endian() which returns the endian MemOp
corresponding to the vCPU DisasContext.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/mips/tcg/translate.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index c55f90e741b..49ff6b8cd80 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -240,6 +240,11 @@ static inline bool disas_is_bigendian(DisasContext *ctx)
return extract32(ctx->CP0_Config0, CP0C0_BE, 1);
}
+static inline MemOp mo_endian(DisasContext *dc)
+{
+ return disas_is_bigendian(dc) ? MO_BE : MO_LE;
+}
+
static inline MemOp mo_endian_rev(DisasContext *dc, bool reversed)
{
return disas_is_bigendian(dc) ^ reversed ? MO_BE : MO_LE;
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 10/16] target/mips: Replace MO_TE by mo_endian()
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2024-10-10 21:50 ` [PATCH v2 09/16] target/mips: Introduce mo_endian() helper Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-13 16:05 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 11/16] target/mips: Have gen_addiupc() expand $pc during translation Philippe Mathieu-Daudé
` (5 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno
Replace compile-time MO_TE evaluation by runtime mo_endian() one,
which expand target endianness from DisasContext.
Mechanical change using:
$ sed -i -e 's/MO_TE/mo_endian(ctx)/' \
$(git grep -l MO_TE target/mips)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/mips/tcg/msa_helper.c | 2 +-
target/mips/tcg/mxu_translate.c | 10 +-
target/mips/tcg/translate.c | 120 +++++++++++-----------
target/mips/tcg/tx79_translate.c | 8 +-
target/mips/tcg/micromips_translate.c.inc | 22 ++--
target/mips/tcg/mips16e_translate.c.inc | 12 +--
target/mips/tcg/nanomips_translate.c.inc | 32 +++---
7 files changed, 103 insertions(+), 103 deletions(-)
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index d2181763e72..0d517b80626 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -8213,7 +8213,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
#if !defined(CONFIG_USER_ONLY)
#define MEMOP_IDX(DF) \
- MemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
+ MemOpIdx oi = make_memop_idx(mo_endian(dc) | DF | MO_UNALN, \
mips_env_mmu_index(env));
#else
#define MEMOP_IDX(DF)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index dd512ce7a48..35ebb0397da 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -4803,19 +4803,19 @@ static void decode_opc_mxu__pool17(DisasContext *ctx)
switch (opcode) {
case OPC_MXU_LXW:
- gen_mxu_lxx(ctx, strd2, MO_TE | MO_UL);
+ gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UL);
break;
case OPC_MXU_LXB:
- gen_mxu_lxx(ctx, strd2, MO_TE | MO_SB);
+ gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_SB);
break;
case OPC_MXU_LXH:
- gen_mxu_lxx(ctx, strd2, MO_TE | MO_SW);
+ gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_SW);
break;
case OPC_MXU_LXBU:
- gen_mxu_lxx(ctx, strd2, MO_TE | MO_UB);
+ gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UB);
break;
case OPC_MXU_LXHU:
- gen_mxu_lxx(ctx, strd2, MO_TE | MO_UW);
+ gen_mxu_lxx(ctx, strd2, mo_endian(ctx) | MO_UW);
break;
default:
MIPS_INVAL("decode_opc_mxu");
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index ebaefe39ed3..4802a6a1d87 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1964,9 +1964,9 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \
gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); \
}
#endif
-OP_LD_ATOMIC(ll, MO_TE | MO_SL);
+OP_LD_ATOMIC(ll, mo_endian(ctx) | MO_SL);
#if defined(TARGET_MIPS64)
-OP_LD_ATOMIC(lld, MO_TE | MO_UQ);
+OP_LD_ATOMIC(lld, mo_endian(ctx) | MO_UQ);
#endif
#undef OP_LD_ATOMIC
@@ -2073,12 +2073,12 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_LWU:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
case OPC_LD:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2090,33 +2090,33 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LDL:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UQ);
+ gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t1, rt);
break;
case OPC_LDR:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UQ);
+ gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t1, rt);
break;
case OPC_LDPC:
t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t0, rt);
break;
#endif
case OPC_LWPC:
t1 = tcg_constant_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL);
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL);
gen_store_gpr(t0, rt);
break;
case OPC_LWE:
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_LW:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2124,7 +2124,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_LH:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_SW |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_SW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2132,7 +2132,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_LHU:
- tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TE | MO_UW |
+ tcg_gen_qemu_ld_tl(t0, t0, mem_idx, mo_endian(ctx) | MO_UW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -2156,7 +2156,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LWL:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxl(ctx, t1, t0, mem_idx, MO_TE | MO_UL);
+ gen_lxl(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL);
tcg_gen_ext32s_tl(t1, t1);
gen_store_gpr(t1, rt);
break;
@@ -2166,7 +2166,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
case OPC_LWR:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- gen_lxr(ctx, t1, t0, mem_idx, MO_TE | MO_UL);
+ gen_lxr(ctx, t1, t0, mem_idx, mo_endian(ctx) | MO_UL);
tcg_gen_ext32s_tl(t1, t1);
gen_store_gpr(t1, rt);
break;
@@ -2194,7 +2194,7 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
switch (opc) {
#if defined(TARGET_MIPS64)
case OPC_SD:
- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
break;
case OPC_SDL:
@@ -2208,14 +2208,14 @@ static void gen_st(DisasContext *ctx, uint32_t opc, int rt,
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_SW:
- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
break;
case OPC_SHE:
mem_idx = MIPS_HFLAG_UM;
/* fall through */
case OPC_SH:
- tcg_gen_qemu_st_tl(t1, t0, mem_idx, MO_TE | MO_UW |
+ tcg_gen_qemu_st_tl(t1, t0, mem_idx, mo_endian(ctx) | MO_UW |
ctx->default_tcg_memop_mask);
break;
case OPC_SBE:
@@ -2281,7 +2281,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
case OPC_LWC1:
{
TCGv_i32 fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_fpr32(ctx, fp0, ft);
}
@@ -2290,14 +2290,14 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, ft);
- tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
}
break;
case OPC_LDC1:
{
TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, fp0, ft);
}
@@ -2306,7 +2306,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, ft);
- tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
}
break;
@@ -2987,14 +2987,14 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
case R6_OPC_LWPC:
offset = sextract32(ctx->opcode << 2, 0, 21);
addr = addr_add(ctx, pc, offset);
- gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_SL);
+ gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_SL);
break;
#if defined(TARGET_MIPS64)
case OPC_LWUPC:
check_mips_64(ctx);
offset = sextract32(ctx->opcode << 2, 0, 21);
addr = addr_add(ctx, pc, offset);
- gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UL);
+ gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UL);
break;
#endif
default:
@@ -3021,7 +3021,7 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
check_mips_64(ctx);
offset = sextract32(ctx->opcode << 3, 0, 21);
addr = addr_add(ctx, (pc & ~0x7), offset);
- gen_r6_ld(addr, rs, ctx->mem_idx, MO_TE | MO_UQ);
+ gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
break;
#endif
default:
@@ -4160,10 +4160,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
case OPC_GSLQ:
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rt);
gen_store_gpr(t0, lsq_rt1);
@@ -4172,10 +4172,10 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
check_cp1_enabled(ctx);
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, t1, rt);
gen_store_fpr64(ctx, t0, lsq_rt1);
@@ -4184,11 +4184,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
gen_load_gpr(t1, lsq_rt1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
break;
case OPC_GSSQC1:
@@ -4196,11 +4196,11 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, rs, lsq_offset);
gen_load_fpr64(ctx, t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8);
gen_load_fpr64(ctx, t1, lsq_rt1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
@@ -4213,7 +4213,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt);
t1 = tcg_temp_new();
tcg_gen_ext_i32_tl(t1, fp0);
- gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL);
+ gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL);
tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(ctx, fp0, rt);
break;
@@ -4224,7 +4224,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_load_fpr32(ctx, fp0, rt);
t1 = tcg_temp_new();
tcg_gen_ext_i32_tl(t1, fp0);
- gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UL);
+ gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL);
tcg_gen_trunc_tl_i32(fp0, t1);
gen_store_fpr32(ctx, fp0, rt);
break;
@@ -4234,7 +4234,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_base_offset_addr(ctx, t0, rs, shf_offset);
t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt);
- gen_lxl(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_fpr64(ctx, t1, rt);
break;
case OPC_GSLDRC1:
@@ -4242,7 +4242,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
gen_base_offset_addr(ctx, t0, rs, shf_offset);
t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt);
- gen_lxr(ctx, t1, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_fpr64(ctx, t1, rt);
break;
#endif
@@ -4360,7 +4360,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
gen_store_gpr(t0, rt);
break;
case OPC_GSLHX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -4369,7 +4369,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -4379,7 +4379,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rt);
break;
@@ -4390,7 +4390,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_fpr32(ctx, fp0, rt);
break;
@@ -4400,7 +4400,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
if (rd) {
gen_op_addr_add(ctx, t0, cpu_gpr[rd], t0);
}
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_fpr64(ctx, t0, rt);
break;
@@ -4413,34 +4413,34 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
case OPC_GSSHX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UW |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UW |
ctx->default_tcg_memop_mask);
break;
case OPC_GSSWX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
break;
#if defined(TARGET_MIPS64)
case OPC_GSSDX:
t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
case OPC_GSSWXC1:
fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, rt);
- tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
break;
#if defined(TARGET_MIPS64)
case OPC_GSSDXC1:
t1 = tcg_temp_new();
gen_load_fpr64(ctx, t1, rt);
- tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
@@ -10779,7 +10779,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
tcg_gen_trunc_tl_i32(fp0, t0);
gen_store_fpr32(ctx, fp0, fd);
}
@@ -10789,7 +10789,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
check_cp1_registers(ctx, fd);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10799,7 +10799,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_fpr64(ctx, fp0, fd);
}
break;
@@ -10808,7 +10808,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i32 fp0 = tcg_temp_new_i32();
gen_load_fpr32(ctx, fp0, fs);
- tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TE | MO_UL);
+ tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL);
}
break;
case OPC_SDXC1:
@@ -10817,7 +10817,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
}
break;
case OPC_SUXC1:
@@ -10826,7 +10826,7 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32_t opc,
{
TCGv_i64 fp0 = tcg_temp_new_i64();
gen_load_fpr64(ctx, fp0, fs);
- tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
}
break;
}
@@ -11476,7 +11476,7 @@ void gen_ldxs(DisasContext *ctx, int base, int index, int rd)
gen_op_addr_add(ctx, t0, t1, t0);
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
gen_store_gpr(t1, rd);
}
@@ -11567,16 +11567,16 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t opc,
gen_store_gpr(t0, rd);
break;
case OPC_LHX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW);
gen_store_gpr(t0, rd);
break;
case OPC_LWX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SL);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL);
gen_store_gpr(t0, rd);
break;
#if defined(TARGET_MIPS64)
case OPC_LDX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t0, rd);
break;
#endif
@@ -13719,7 +13719,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
}
break;
case R6_OPC_SC:
- gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false);
+ gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false);
break;
case R6_OPC_LL:
gen_ld(ctx, op1, rt, rs, imm);
@@ -13765,7 +13765,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
#endif
#if defined(TARGET_MIPS64)
case R6_OPC_SCD:
- gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false);
+ gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false);
break;
case R6_OPC_LLD:
gen_ld(ctx, op1, rt, rs, imm);
@@ -14448,7 +14448,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
return;
case OPC_SCE:
check_cp0_enabled(ctx);
- gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, true);
+ gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, true);
return;
case OPC_CACHEE:
check_eva(ctx);
@@ -14912,7 +14912,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
- gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_SL, false);
+ gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_SL, false);
break;
case OPC_CACHE:
check_cp0_enabled(ctx);
@@ -15191,7 +15191,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
check_insn_opc_user_only(ctx, INSN_R5900);
}
check_mips_64(ctx);
- gen_st_cond(ctx, rt, rs, imm, MO_TE | MO_UQ, false);
+ gen_st_cond(ctx, rt, rs, imm, mo_endian(ctx) | MO_UQ, false);
break;
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
if (ctx->insn_flags & ISA_MIPS_R6) {
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index 1d290b86a98..ae3f5e19c43 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -340,12 +340,12 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)
tcg_gen_andi_tl(addr, addr, ~0xf);
/* Lower half */
- tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr(t0, a->rt);
/* Upper half */
tcg_gen_addi_i64(addr, addr, 8);
- tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
gen_store_gpr_hi(t0, a->rt);
return true;
}
@@ -364,12 +364,12 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a)
/* Lower half */
gen_load_gpr(t0, a->rt);
- tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
/* Upper half */
tcg_gen_addi_i64(addr, addr, 8);
gen_load_gpr_hi(t0, a->rt);
- tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TE | MO_UQ);
+ tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
return true;
}
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 343d64a0e85..171508f7deb 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -977,23 +977,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx);
return;
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
break;
case SWP:
gen_load_gpr(t1, rd);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
break;
#ifdef TARGET_MIPS64
@@ -1002,23 +1002,23 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx);
return;
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
break;
case SDP:
gen_load_gpr(t1, rd);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UQ |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
break;
#endif
@@ -2572,13 +2572,13 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st(ctx, mips32_op, rt, rs, offset);
break;
case SC:
- gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, false);
+ gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_SL, false);
break;
#if defined(TARGET_MIPS64)
case SCD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
- gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_UQ, false);
+ gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_UQ, false);
break;
#endif
case LD_EVA:
@@ -2659,7 +2659,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_SHE;
goto do_st_lr;
case SCE:
- gen_st_cond(ctx, rt, rs, offset, MO_TE | MO_SL, true);
+ gen_st_cond(ctx, rt, rs, offset, mo_endian(ctx) | MO_SL, true);
break;
case SWE:
mips32_op = OPC_SWE;
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index 6983636acbf..3c914a10c0f 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -135,7 +135,7 @@ static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0)
tcg_gen_movi_tl(t2, -4);
gen_op_addr_add(ctx, t0, t0, t2);
gen_load_gpr(t1, regidx);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
}
@@ -184,25 +184,25 @@ static void gen_mips16_save(DisasContext *ctx,
case 4:
gen_base_offset_addr(ctx, t0, 29, 12);
gen_load_gpr(t1, 7);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
/* Fall through */
case 3:
gen_base_offset_addr(ctx, t0, 29, 8);
gen_load_gpr(t1, 6);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
/* Fall through */
case 2:
gen_base_offset_addr(ctx, t0, 29, 4);
gen_load_gpr(t1, 5);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
/* Fall through */
case 1:
gen_base_offset_addr(ctx, t0, 29, 0);
gen_load_gpr(t1, 4);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UL |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
}
@@ -297,7 +297,7 @@ static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0)
tcg_gen_movi_tl(t2, -4);
gen_op_addr_add(ctx, t0, t0, t2);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL |
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TE | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, regidx);
}
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index c79c77b882d..a32b4c1d4f8 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
TCGv tmp2 = tcg_temp_new();
gen_base_offset_addr(ctx, taddr, base, offset);
- tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TE | MO_UQ | MO_ALIGN);
+ tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, mo_endian(ctx) | MO_UQ | MO_ALIGN);
if (disas_is_bigendian(ctx)) {
tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
} else {
@@ -1075,7 +1075,7 @@ static void gen_save(DisasContext *ctx, uint8_t rt, uint8_t count,
gen_base_offset_addr(ctx, va, 29, this_offset);
gen_load_gpr(t0, this_rt);
tcg_gen_qemu_st_tl(t0, va, ctx->mem_idx,
- MO_TE | MO_UL | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask);
counter++;
}
@@ -1095,7 +1095,7 @@ static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count,
int this_rt = use_gp ? 28 : (rt & 0x10) | ((rt + counter) & 0x1f);
int this_offset = u - ((counter + 1) << 2);
gen_base_offset_addr(ctx, va, 29, this_offset);
- tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, MO_TE | MO_SL |
+ tcg_gen_qemu_ld_tl(t0, va, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
tcg_gen_ext32s_tl(t0, t0);
gen_store_gpr(t0, this_rt);
@@ -2647,13 +2647,13 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
case NM_LHX:
/*case NM_LHXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TE | MO_SW | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_SW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_LWX:
/*case NM_LWXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TE | MO_SL | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_LBUX:
@@ -2663,7 +2663,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
case NM_LHUX:
/*case NM_LHUXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TE | MO_UW | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_SBX:
@@ -2676,14 +2676,14 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
check_nms(ctx);
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TE | MO_UW | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_UW | ctx->default_tcg_memop_mask);
break;
case NM_SWX:
/*case NM_SWXS:*/
check_nms(ctx);
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TE | MO_UL | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask);
break;
case NM_LWC1X:
/*case NM_LWC1XS:*/
@@ -3737,7 +3737,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
tcg_gen_movi_tl(t0, addr);
tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx,
- MO_TE | MO_SL | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask);
}
break;
case NM_SWPC48:
@@ -3754,7 +3754,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_load_gpr(t1, rt);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TE | MO_UL | ctx->default_tcg_memop_mask);
+ mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask);
}
break;
default:
@@ -4132,13 +4132,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
switch (extract32(ctx->opcode, 11, 4)) {
case NM_UALH:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TE | MO_SW |
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW |
MO_UNALN);
gen_store_gpr(t0, rt);
break;
case NM_UASH:
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TE | MO_UW |
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UW |
MO_UNALN);
break;
}
@@ -4161,7 +4161,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_P_SC:
switch (ctx->opcode & 0x03) {
case NM_SC:
- gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, false);
+ gen_st_cond(ctx, rt, rs, s, mo_endian(ctx) | MO_SL, false);
break;
case NM_SCWP:
check_xnp(ctx);
@@ -4274,7 +4274,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
check_xnp(ctx);
check_eva(ctx);
check_cp0_enabled(ctx);
- gen_st_cond(ctx, rt, rs, s, MO_TE | MO_SL, true);
+ gen_st_cond(ctx, rt, rs, s, mo_endian(ctx) | MO_SL, true);
break;
case NM_SCWPE:
check_xnp(ctx);
@@ -4317,7 +4317,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
switch (extract32(ctx->opcode, 11, 1)) {
case NM_LWM:
tcg_gen_qemu_ld_tl(t1, va, ctx->mem_idx,
- memop | MO_TE | MO_SL);
+ memop | mo_endian(ctx) | MO_SL);
gen_store_gpr(t1, this_rt);
if ((this_rt == rs) &&
(counter != (count - 1))) {
@@ -4328,7 +4328,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
this_rt = (rt == 0) ? 0 : this_rt;
gen_load_gpr(t1, this_rt);
tcg_gen_qemu_st_tl(t1, va, ctx->mem_idx,
- memop | MO_TE | MO_UL);
+ memop | mo_endian(ctx) | MO_UL);
break;
}
counter++;
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 11/16] target/mips: Have gen_addiupc() expand $pc during translation
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2024-10-10 21:50 ` [PATCH v2 10/16] target/mips: Replace MO_TE by mo_endian() Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-13 16:06 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 12/16] target/mips: Use gen_op_addr_addi() when possible Philippe Mathieu-Daudé
` (4 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/translate.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 4802a6a1d87..41f25c938de 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -11428,20 +11428,18 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
void gen_addiupc(DisasContext *ctx, int rx, int imm,
int is_64_bit, int extended)
{
- TCGv t0;
+ target_ulong npc;
if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
gen_reserved_instruction(ctx);
return;
}
- t0 = tcg_temp_new();
-
- tcg_gen_movi_tl(t0, pc_relative_pc(ctx));
- tcg_gen_addi_tl(cpu_gpr[rx], t0, imm);
+ npc = pc_relative_pc(ctx) + imm;
if (!is_64_bit) {
- tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
+ npc = (int32_t)npc;
}
+ tcg_gen_movi_tl(cpu_gpr[rx], npc);
}
static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 12/16] target/mips: Use gen_op_addr_addi() when possible
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2024-10-10 21:50 ` [PATCH v2 11/16] target/mips: Have gen_addiupc() expand $pc during translation Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-13 16:11 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 13/16] target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl() Philippe Mathieu-Daudé
` (3 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
Replace tcg_gen_movi_tl() + gen_op_addr_add() by a single
gen_op_addr_addi() call.
gen_op_addr_addi() calls tcg_gen_addi_tl() which might
optimize if the immediate is zero.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/translate.h | 1 +
target/mips/tcg/translate.c | 6 ++----
target/mips/tcg/micromips_translate.c.inc | 12 ++++--------
target/mips/tcg/mips16e_translate.c.inc | 15 ++++-----------
target/mips/tcg/nanomips_translate.c.inc | 4 +---
5 files changed, 12 insertions(+), 26 deletions(-)
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 49ff6b8cd80..5d196e69ac4 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -176,6 +176,7 @@ void gen_addiupc(DisasContext *ctx, int rx, int imm,
* Address Computation and Large Constant Instructions
*/
void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
+void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, target_long ofs);
bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 41f25c938de..8ff1d59eb64 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1456,8 +1456,7 @@ void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
#endif
}
-static inline void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base,
- target_long ofs)
+void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, target_long ofs)
{
tcg_gen_addi_tl(ret, base, ofs);
@@ -11265,10 +11264,9 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
} else {
/* OPC_JIC, OPC_JIALC */
TCGv tbase = tcg_temp_new();
- TCGv toffset = tcg_constant_tl(offset);
gen_load_gpr(tbase, rt);
- gen_op_addr_add(ctx, btarget, tbase, toffset);
+ gen_op_addr_addi(ctx, btarget, tbase, offset);
}
break;
default:
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 171508f7deb..3cbf53bf2b3 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -980,8 +980,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
- tcg_gen_movi_tl(t1, 4);
- gen_op_addr_add(ctx, t0, t0, t1);
+ gen_op_addr_addi(ctx, t0, t0, 4);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
@@ -990,8 +989,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
- tcg_gen_movi_tl(t1, 4);
- gen_op_addr_add(ctx, t0, t0, t1);
+ gen_op_addr_addi(ctx, t0, t0, 4);
gen_load_gpr(t1, rd + 1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
@@ -1005,8 +1003,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
- tcg_gen_movi_tl(t1, 8);
- gen_op_addr_add(ctx, t0, t0, t1);
+ gen_op_addr_addi(ctx, t0, t0, 8);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
@@ -1015,8 +1012,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
- tcg_gen_movi_tl(t1, 8);
- gen_op_addr_add(ctx, t0, t0, t1);
+ gen_op_addr_addi(ctx, t0, t0, 8);
gen_load_gpr(t1, rd + 1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index 3c914a10c0f..09092653fcc 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -130,10 +130,8 @@ static int xlat(int r)
static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0)
{
TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
- tcg_gen_movi_tl(t2, -4);
- gen_op_addr_add(ctx, t0, t0, t2);
+ gen_op_addr_addi(ctx, t0, t0, -4);
gen_load_gpr(t1, regidx);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
@@ -146,7 +144,6 @@ static void gen_mips16_save(DisasContext *ctx,
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
int args, astatic;
switch (aregs) {
@@ -286,8 +283,7 @@ static void gen_mips16_save(DisasContext *ctx,
}
}
- tcg_gen_movi_tl(t2, -framesize);
- gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
+ gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], -framesize);
}
static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0)
@@ -309,10 +305,8 @@ static void gen_mips16_restore(DisasContext *ctx,
{
int astatic;
TCGv t0 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
- tcg_gen_movi_tl(t2, framesize);
- gen_op_addr_add(ctx, t0, cpu_gpr[29], t2);
+ gen_op_addr_addi(ctx, t0, cpu_gpr[29], -framesize);
if (do_ra) {
decr_and_load(ctx, 31, t0);
@@ -392,8 +386,7 @@ static void gen_mips16_restore(DisasContext *ctx,
}
}
- tcg_gen_movi_tl(t2, framesize);
- gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
+ gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], -framesize);
}
#if defined(TARGET_MIPS64)
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index a32b4c1d4f8..d6149ea26e4 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -2469,11 +2469,9 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
} else {
/* OPC_JIC, OPC_JIALC */
TCGv tbase = tcg_temp_new();
- TCGv toffset = tcg_temp_new();
gen_load_gpr(tbase, rt);
- tcg_gen_movi_tl(toffset, offset);
- gen_op_addr_add(ctx, btarget, tbase, toffset);
+ gen_op_addr_addi(ctx, btarget, tbase, offset);
}
break;
default:
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 13/16] target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl()
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2024-10-10 21:50 ` [PATCH v2 12/16] target/mips: Use gen_op_addr_addi() when possible Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-10 21:50 ` [PATCH v2 14/16] target/mips: Expose MIPSCPU::is_big_endian property Philippe Mathieu-Daudé
` (2 subsequent siblings)
15 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
Directly use tcg_constant_tl() for constant integer, this
save a call to tcg_gen_movi_tl(), often saving a temp register.
Most of the places found using the following Coccinelle spatch script:
@@
identifier tmp;
constant val;
@@
* TCGv tmp = tcg_temp_new();
...
* tcg_gen_movi_tl(tmp, val);
@@
identifier tmp;
int val;
@@
* TCGv tmp = tcg_temp_new();
...
* tcg_gen_movi_i64(tmp, val);
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241004202621.4321-2-philmd@linaro.org>
---
target/mips/tcg/translate.c | 49 ++++------
target/mips/tcg/nanomips_translate.c.inc | 110 +++++++++--------------
2 files changed, 58 insertions(+), 101 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 8ff1d59eb64..254948583c8 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -2252,8 +2252,7 @@ static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
/* compare the address against that of the preceding LL */
gen_base_offset_addr(ctx, addr, base, offset);
tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
- tcg_gen_movi_tl(t0, 0);
- gen_store_gpr(t0, rt);
+ gen_store_gpr(tcg_constant_tl(0), rt);
tcg_gen_br(done);
gen_set_label(l1);
@@ -3059,8 +3058,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_and_tl(t2, t2, t3);
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
tcg_gen_or_tl(t2, t2, t3);
- tcg_gen_movi_tl(t3, 0);
- tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
+ tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
}
@@ -3076,30 +3074,27 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_and_tl(t2, t2, t3);
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
tcg_gen_or_tl(t2, t2, t3);
- tcg_gen_movi_tl(t3, 0);
- tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
+ tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
}
break;
case R6_OPC_DIVU:
{
- TCGv t2 = tcg_constant_tl(0);
- TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
- tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
+ tcg_constant_tl(0), tcg_constant_tl(1), t1);
tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
}
break;
case R6_OPC_MODU:
{
- TCGv t2 = tcg_constant_tl(0);
- TCGv t3 = tcg_constant_tl(1);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
- tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
+ tcg_constant_tl(0), tcg_constant_tl(1), t1);
tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
}
@@ -3154,8 +3149,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_and_tl(t2, t2, t3);
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
tcg_gen_or_tl(t2, t2, t3);
- tcg_gen_movi_tl(t3, 0);
- tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
+ tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
}
break;
@@ -3168,24 +3162,21 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_gen_and_tl(t2, t2, t3);
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
tcg_gen_or_tl(t2, t2, t3);
- tcg_gen_movi_tl(t3, 0);
- tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
+ tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
}
break;
case R6_OPC_DDIVU:
{
- TCGv t2 = tcg_constant_tl(0);
- TCGv t3 = tcg_constant_tl(1);
- tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
+ tcg_constant_tl(0), tcg_constant_tl(1), t1);
tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);
}
break;
case R6_OPC_DMODU:
{
- TCGv t2 = tcg_constant_tl(0);
- TCGv t3 = tcg_constant_tl(1);
- tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
+ tcg_constant_tl(0), tcg_constant_tl(1), t1);
tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);
}
break;
@@ -3238,8 +3229,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
tcg_gen_and_tl(t2, t2, t3);
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
tcg_gen_or_tl(t2, t2, t3);
- tcg_gen_movi_tl(t3, 0);
- tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
+ tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
tcg_gen_div_tl(cpu_LO[1], t0, t1);
tcg_gen_rem_tl(cpu_HI[1], t0, t1);
tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]);
@@ -3294,8 +3284,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_gen_and_tl(t2, t2, t3);
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
tcg_gen_or_tl(t2, t2, t3);
- tcg_gen_movi_tl(t3, 0);
- tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
+ tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
tcg_gen_div_tl(cpu_LO[acc], t0, t1);
tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
@@ -3347,17 +3336,15 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
tcg_gen_and_tl(t2, t2, t3);
tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0);
tcg_gen_or_tl(t2, t2, t3);
- tcg_gen_movi_tl(t3, 0);
- tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
+ tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, tcg_constant_tl(0), t2, t1);
tcg_gen_div_tl(cpu_LO[acc], t0, t1);
tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
}
break;
case OPC_DDIVU:
{
- TCGv t2 = tcg_constant_tl(0);
- TCGv t3 = tcg_constant_tl(1);
- tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1,
+ tcg_constant_tl(0), tcg_constant_tl(1), t1);
tcg_gen_divu_i64(cpu_LO[acc], t0, t1);
tcg_gen_remu_i64(cpu_HI[acc], t0, t1);
}
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index d6149ea26e4..6b7abf1f8f8 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -1052,8 +1052,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
tcg_gen_movi_tl(cpu_gpr[reg1], 0);
}
gen_set_label(lab_done);
- tcg_gen_movi_tl(lladdr, -1);
- tcg_gen_st_tl(lladdr, tcg_env, offsetof(CPUMIPSState, lladdr));
+ tcg_gen_st_tl(tcg_constant_tl(-1), tcg_env, offsetof(CPUMIPSState, lladdr));
}
static void gen_adjust_sp(DisasContext *ctx, int u)
@@ -1543,7 +1542,6 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
{
int16_t imm;
TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
TCGv v0_t = tcg_temp_new();
gen_load_gpr(v0_t, v1);
@@ -1570,12 +1568,10 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
check_dsp(ctx);
switch (extract32(ctx->opcode, 12, 2)) {
case NM_MTHLIP:
- tcg_gen_movi_tl(t0, v2 >> 3);
- gen_helper_mthlip(t0, v0_t, tcg_env);
+ gen_helper_mthlip(tcg_constant_tl(v2 >> 3), v0_t, tcg_env);
break;
case NM_SHILOV:
- tcg_gen_movi_tl(t0, v2 >> 3);
- gen_helper_shilo(t0, v0_t, tcg_env);
+ gen_helper_shilo(tcg_constant_tl(v2 >> 3), v0_t, tcg_env);
break;
default:
gen_reserved_instruction(ctx);
@@ -1587,39 +1583,34 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
imm = extract32(ctx->opcode, 14, 7);
switch (extract32(ctx->opcode, 12, 2)) {
case NM_RDDSP:
- tcg_gen_movi_tl(t0, imm);
- gen_helper_rddsp(t0, t0, tcg_env);
+ gen_helper_rddsp(t0, tcg_constant_tl(imm), tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_WRDSP:
gen_load_gpr(t0, ret);
- tcg_gen_movi_tl(t1, imm);
- gen_helper_wrdsp(t0, t1, tcg_env);
+ gen_helper_wrdsp(t0, tcg_constant_tl(imm), tcg_env);
break;
case NM_EXTP:
- tcg_gen_movi_tl(t0, v2 >> 3);
- tcg_gen_movi_tl(t1, v1);
- gen_helper_extp(t0, t0, t1, tcg_env);
+ gen_helper_extp(t0, tcg_constant_tl(v2 >> 3),
+ tcg_constant_tl(v1), tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_EXTPDP:
- tcg_gen_movi_tl(t0, v2 >> 3);
- tcg_gen_movi_tl(t1, v1);
- gen_helper_extpdp(t0, t0, t1, tcg_env);
+ gen_helper_extpdp(t0, tcg_constant_tl(v2 >> 3),
+ tcg_constant_tl(v1), tcg_env);
gen_store_gpr(t0, ret);
break;
}
break;
case NM_POOL32AXF_1_4:
check_dsp(ctx);
- tcg_gen_movi_tl(t0, v2 >> 2);
switch (extract32(ctx->opcode, 12, 1)) {
case NM_SHLL_QB:
- gen_helper_shll_qb(t0, t0, v0_t, tcg_env);
+ gen_helper_shll_qb(t0, tcg_constant_tl(v2 >> 2), v0_t, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_SHRL_QB:
- gen_helper_shrl_qb(t0, t0, v0_t);
+ gen_helper_shrl_qb(t0, tcg_constant_tl(v2 >> 2), v0_t);
gen_store_gpr(t0, ret);
break;
}
@@ -1630,23 +1621,25 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
break;
case NM_POOL32AXF_1_7:
check_dsp(ctx);
- tcg_gen_movi_tl(t0, v2 >> 3);
- tcg_gen_movi_tl(t1, v1);
switch (extract32(ctx->opcode, 12, 2)) {
case NM_EXTR_W:
- gen_helper_extr_w(t0, t0, t1, tcg_env);
+ gen_helper_extr_w(t0, tcg_constant_tl(v2 >> 3),
+ tcg_constant_tl(v1), tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_EXTR_R_W:
- gen_helper_extr_r_w(t0, t0, t1, tcg_env);
+ gen_helper_extr_r_w(t0, tcg_constant_tl(v2 >> 3),
+ tcg_constant_tl(v1), tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_EXTR_RS_W:
- gen_helper_extr_rs_w(t0, t0, t1, tcg_env);
+ gen_helper_extr_rs_w(t0, tcg_constant_tl(v2 >> 3),
+ tcg_constant_tl(v1), tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_EXTR_S_H:
- gen_helper_extr_s_h(t0, t0, t1, tcg_env);
+ gen_helper_extr_s_h(t0, tcg_constant_tl(v2 >> 3),
+ tcg_constant_tl(v1), tcg_env);
gen_store_gpr(t0, ret);
break;
}
@@ -1848,8 +1841,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
case NM_EXTRV_W:
check_dsp(ctx);
gen_load_gpr(v1_t, rs);
- tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extr_w(t0, t0, v1_t, tcg_env);
+ gen_helper_extr_w(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
}
@@ -1903,8 +1895,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
break;
case NM_EXTRV_R_W:
check_dsp(ctx);
- tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extr_r_w(t0, t0, v1_t, tcg_env);
+ gen_helper_extr_r_w(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
default:
@@ -1923,8 +1914,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
break;
case NM_EXTPV:
check_dsp(ctx);
- tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extp(t0, t0, v1_t, tcg_env);
+ gen_helper_extp(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_MSUB:
@@ -1947,8 +1937,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
break;
case NM_EXTRV_RS_W:
check_dsp(ctx);
- tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extr_rs_w(t0, t0, v1_t, tcg_env);
+ gen_helper_extr_rs_w(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
}
@@ -1964,8 +1953,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
break;
case NM_EXTPDPV:
check_dsp(ctx);
- tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extpdp(t0, t0, v1_t, tcg_env);
+ gen_helper_extpdp(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
case NM_MSUBU:
@@ -1990,8 +1978,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
break;
case NM_EXTRV_S_H:
check_dsp(ctx);
- tcg_gen_movi_tl(t0, rd >> 3);
- gen_helper_extr_s_h(t0, t0, v1_t, tcg_env);
+ gen_helper_extr_s_h(t0, tcg_constant_tl(rd >> 3), v1_t, tcg_env);
gen_store_gpr(t0, ret);
break;
}
@@ -2149,24 +2136,22 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
switch (opc) {
case NM_SHRA_R_QB:
check_dsp_r2(ctx);
- tcg_gen_movi_tl(t0, rd >> 2);
switch (extract32(ctx->opcode, 12, 1)) {
case 0:
/* NM_SHRA_QB */
- gen_helper_shra_qb(t0, t0, rs_t);
+ gen_helper_shra_qb(t0, tcg_constant_tl(rd >> 2), rs_t);
gen_store_gpr(t0, rt);
break;
case 1:
/* NM_SHRA_R_QB */
- gen_helper_shra_r_qb(t0, t0, rs_t);
+ gen_helper_shra_r_qb(t0, tcg_constant_tl(rd >> 2), rs_t);
gen_store_gpr(t0, rt);
break;
}
break;
case NM_SHRL_PH:
check_dsp_r2(ctx);
- tcg_gen_movi_tl(t0, rd >> 1);
- gen_helper_shrl_ph(t0, t0, rs_t);
+ gen_helper_shrl_ph(t0, tcg_constant_tl(rd >> 1), rs_t);
gen_store_gpr(t0, rt);
break;
case NM_REPL_QB:
@@ -2180,8 +2165,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
(uint32_t)imm << 8 |
(uint32_t)imm;
result = (int32_t)result;
- tcg_gen_movi_tl(t0, result);
- gen_store_gpr(t0, rt);
+ gen_store_gpr(tcg_constant_tl(result), rt);
}
break;
default:
@@ -2302,10 +2286,9 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
{
TCGCond cond = TCG_COND_ALWAYS;
TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
+ TCGv timm = tcg_constant_tl(imm);
gen_load_gpr(t0, rt);
- tcg_gen_movi_tl(t1, imm);
ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
/* Load needed operands and calculate btarget */
@@ -2334,7 +2317,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
} else {
tcg_gen_shri_tl(t0, t0, imm);
tcg_gen_andi_tl(t0, t0, 1);
- tcg_gen_movi_tl(t1, 0);
+ timm = tcg_constant_tl(0);
if (opc == NM_BBEQZC) {
cond = TCG_COND_EQ;
} else {
@@ -2389,7 +2372,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
/* Conditional compact branch */
TCGLabel *fs = gen_new_label();
- tcg_gen_brcond_tl(tcg_invert_cond(cond), t0, t1, fs);
+ tcg_gen_brcond_tl(tcg_invert_cond(cond), t0, timm, fs);
gen_goto_tb(ctx, 1, ctx->btarget);
gen_set_label(fs);
@@ -2403,7 +2386,6 @@ static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
int rt)
{
TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
/* load rs */
gen_load_gpr(t0, rs);
@@ -2415,8 +2397,7 @@ static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
/* calculate btarget */
tcg_gen_shli_tl(t0, t0, 1);
- tcg_gen_movi_tl(t1, ctx->base.pc_next + 4);
- gen_op_addr_add(ctx, btarget, t1, t0);
+ gen_op_addr_add(ctx, btarget, tcg_constant_tl(ctx->base.pc_next + 4), t0);
/* branch completion */
clear_branch_hflags(ctx);
@@ -3443,13 +3424,10 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
case NM_SHILO:
check_dsp(ctx);
{
- TCGv tv0 = tcg_temp_new();
- TCGv tv1 = tcg_temp_new();
int16_t imm = extract32(ctx->opcode, 16, 7);
- tcg_gen_movi_tl(tv0, rd >> 3);
- tcg_gen_movi_tl(tv1, imm);
- gen_helper_shilo(tv0, tv1, tcg_env);
+ gen_helper_shilo(tcg_constant_tl(rd >> 3),
+ tcg_constant_tl(imm), tcg_env);
}
break;
case NM_MULEQ_S_W_PHL:
@@ -3504,8 +3482,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
break;
case NM_SHRA_R_W:
check_dsp(ctx);
- tcg_gen_movi_tl(t0, rd);
- gen_helper_shra_r_w(v1_t, t0, v1_t);
+ gen_helper_shra_r_w(v1_t, tcg_constant_tl(rd), v1_t);
gen_store_gpr(v1_t, rt);
break;
case NM_SHRA_R_PH:
@@ -3545,8 +3522,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
break;
case NM_SHLL_S_W:
check_dsp(ctx);
- tcg_gen_movi_tl(t0, rd);
- gen_helper_shll_s_w(v1_t, t0, v1_t, tcg_env);
+ gen_helper_shll_s_w(v1_t, tcg_constant_tl(rd), v1_t, tcg_env);
gen_store_gpr(v1_t, rt);
break;
case NM_REPL_PH:
@@ -3727,31 +3703,25 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
case NM_LWPC48:
check_nms(ctx);
if (rt != 0) {
- TCGv t0;
- t0 = tcg_temp_new();
-
target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
addr_off);
- tcg_gen_movi_tl(t0, addr);
- tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx,
+ tcg_gen_qemu_ld_tl(cpu_gpr[rt], tcg_constant_tl(addr), ctx->mem_idx,
mo_endian(ctx) | MO_SL | ctx->default_tcg_memop_mask);
}
break;
case NM_SWPC48:
check_nms(ctx);
{
- TCGv t0, t1;
- t0 = tcg_temp_new();
+ TCGv t1;
t1 = tcg_temp_new();
target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
addr_off);
- tcg_gen_movi_tl(t0, addr);
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
+ tcg_gen_qemu_st_tl(t1, tcg_constant_tl(addr), ctx->mem_idx,
mo_endian(ctx) | MO_UL | ctx->default_tcg_memop_mask);
}
break;
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 14/16] target/mips: Expose MIPSCPU::is_big_endian property
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2024-10-10 21:50 ` [PATCH v2 13/16] target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl() Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-13 16:14 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 15/16] hw/mips/cps: Set the vCPU 'cpu-big-endian' property Philippe Mathieu-Daudé
2024-10-10 21:50 ` [PATCH v2 16/16] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument Philippe Mathieu-Daudé
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno
Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/mips/cpu.h | 3 +++
target/mips/cpu.c | 12 ++++++++----
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 3e906a175a3..070e11fe0da 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1209,6 +1209,9 @@ struct ArchCPU {
Clock *clock;
Clock *count_div; /* Divider for CP0_Count clock */
+
+ /* Properties */
+ bool is_big_endian;
};
/**
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 89655b1900f..04bf4b11db2 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -200,10 +200,8 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type)
/* Reset registers to their default values */
env->CP0_PRid = env->cpu_model->CP0_PRid;
- env->CP0_Config0 = env->cpu_model->CP0_Config0;
-#if TARGET_BIG_ENDIAN
- env->CP0_Config0 |= (1 << CP0C0_BE);
-#endif
+ env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0,
+ CP0C0_BE, 1, cpu->is_big_endian);
env->CP0_Config1 = env->cpu_model->CP0_Config1;
env->CP0_Config2 = env->cpu_model->CP0_Config2;
env->CP0_Config3 = env->cpu_model->CP0_Config3;
@@ -541,6 +539,11 @@ static const struct SysemuCPUOps mips_sysemu_ops = {
};
#endif
+static Property mips_cpu_properties[] = {
+ DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDIAN),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
/*
@@ -571,6 +574,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
DeviceClass *dc = DEVICE_CLASS(c);
ResettableClass *rc = RESETTABLE_CLASS(c);
+ device_class_set_props(dc, mips_cpu_properties);
device_class_set_parent_realize(dc, mips_cpu_realizefn,
&mcc->parent_realize);
resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL,
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 15/16] hw/mips/cps: Set the vCPU 'cpu-big-endian' property
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2024-10-10 21:50 ` [PATCH v2 14/16] target/mips: Expose MIPSCPU::is_big_endian property Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-13 16:58 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 16/16] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument Philippe Mathieu-Daudé
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno
Have the CPS expose a 'cpu-big-endian' property so it can
set it to the vCPUs it creates.
Note, since the number of vCPUs created is dynamic, we can
not use QOM aliases.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
include/hw/mips/cps.h | 1 +
hw/mips/cps.c | 4 ++++
hw/mips/malta.c | 2 ++
3 files changed, 7 insertions(+)
diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h
index 04d636246ab..05ef9f76b74 100644
--- a/include/hw/mips/cps.h
+++ b/include/hw/mips/cps.h
@@ -38,6 +38,7 @@ struct MIPSCPSState {
uint32_t num_vp;
uint32_t num_irq;
char *cpu_type;
+ bool cpu_is_bigendian;
MemoryRegion container;
MIPSGCRState gcr;
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 07b73b0a1f4..13046628cd2 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -77,6 +77,9 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type));
CPUMIPSState *env = &cpu->env;
+ object_property_set_bool(OBJECT(cpu), "big-endian", s->cpu_is_bigendian,
+ &error_abort);
+
/* All VPs are halted on reset. Leave powering up to CPC. */
object_property_set_bool(OBJECT(cpu), "start-powered-off", true,
&error_abort);
@@ -167,6 +170,7 @@ static Property mips_cps_properties[] = {
DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
+ DEFINE_PROP_BOOL("cpu-big-endian", MIPSCPSState, cpu_is_bigendian, false),
DEFINE_PROP_END_OF_LIST()
};
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 1df00c4bf99..964d3592da7 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1054,6 +1054,8 @@ static void create_cps(MachineState *ms, MaltaState *s,
object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS);
object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type,
&error_fatal);
+ object_property_set_bool(OBJECT(&s->cps), "cpu-big-endian",
+ TARGET_BIG_ENDIAN, &error_abort);
object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus,
&error_fatal);
qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk);
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v2 16/16] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2024-10-10 21:50 ` [PATCH v2 15/16] hw/mips/cps: Set the vCPU 'cpu-big-endian' property Philippe Mathieu-Daudé
@ 2024-10-10 21:50 ` Philippe Mathieu-Daudé
2024-10-13 17:00 ` Richard Henderson
15 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-10 21:50 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, Philippe Mathieu-Daudé, Jiaxun Yang,
Hervé Poussineau, Aleksandar Rikalo, Aurelien Jarno
mips_cpu_create_with_clock() creates a vCPU. Pass it the vCPU
endianness requested by argument. Update the board call sites.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/mips/cpu.h | 4 +++-
hw/mips/fuloong2e.c | 2 +-
hw/mips/jazz.c | 2 +-
hw/mips/loongson3_virt.c | 2 +-
hw/mips/malta.c | 3 ++-
hw/mips/mipssim.c | 2 +-
target/mips/cpu.c | 5 ++++-
7 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 070e11fe0da..a4a46ebbe98 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1376,12 +1376,14 @@ static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc,
* mips_cpu_create_with_clock:
* @typename: a MIPS CPU type.
* @cpu_refclk: this cpu input clock (an output clock of another device)
+ * @is_big_endian: whether this CPU is configured in big endianness
*
* Instantiates a MIPS CPU, set the input clock of the CPU to @cpu_refclk,
* then realizes the CPU.
*
* Returns: A #CPUState or %NULL if an error occurred.
*/
-MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk);
+MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk,
+ bool is_big_endian);
#endif /* MIPS_CPU_H */
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 6e4303ba473..7fd8296ccb6 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -229,7 +229,7 @@ static void mips_fuloong2e_init(MachineState *machine)
clock_set_hz(cpuclk, 533080000); /* ~533 MHz */
/* init CPUs */
- cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
+ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false);
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index 33ce51fb09c..d6bc698ef17 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -212,7 +212,7 @@ static void mips_jazz_init(MachineState *machine,
* ext_clk[jazz_model].pll_mult);
/* init CPUs */
- cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
+ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, TARGET_BIG_ENDIAN);
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c
index a2db98665df..f3b6326cc59 100644
--- a/hw/mips/loongson3_virt.c
+++ b/hw/mips/loongson3_virt.c
@@ -567,7 +567,7 @@ static void mips_loongson3_virt_init(MachineState *machine)
int ip;
/* init CPUs */
- cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
+ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false);
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 964d3592da7..198da5ba3d4 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1034,7 +1034,8 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
int i;
for (i = 0; i < ms->smp.cpus; i++) {
- cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk);
+ cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk,
+ TARGET_BIG_ENDIAN);
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c
index a07732d3dc5..54cdcd61724 100644
--- a/hw/mips/mipssim.c
+++ b/hw/mips/mipssim.c
@@ -160,7 +160,7 @@ mips_mipssim_init(MachineState *machine)
#endif
/* Init CPUs. */
- cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
+ cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, TARGET_BIG_ENDIAN);
env = &cpu->env;
reset_info = g_new0(ResetData, 1);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 04bf4b11db2..9724e71a5e0 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -643,12 +643,15 @@ static void mips_cpu_register_types(void)
type_init(mips_cpu_register_types)
/* Could be used by generic CPU object */
-MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk)
+MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk,
+ bool is_big_endian)
{
DeviceState *cpu;
cpu = DEVICE(object_new(cpu_type));
qdev_connect_clock_in(cpu, "clk-in", cpu_refclk);
+ object_property_set_bool(OBJECT(cpu), "big-endian", is_big_endian,
+ &error_abort);
qdev_realize(cpu, NULL, &error_abort);
return MIPS_CPU(cpu);
--
2.45.2
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH v2 01/16] target/mips: Declare mips_env_is_bigendian() in 'internal.h'
2024-10-10 21:49 ` [PATCH v2 01/16] target/mips: Declare mips_env_is_bigendian() in 'internal.h' Philippe Mathieu-Daudé
@ 2024-10-13 15:51 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 15:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/10/24 14:49, Philippe Mathieu-Daudé wrote:
> In order to re-use cpu_is_bigendian(), declare it on "internal.h"
> after renaming it as mips_env_is_bigendian().
>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Tested-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> Message-Id:<20241004162118.84570-6-philmd@linaro.org>
> ---
> target/mips/internal.h | 5 +++++
> target/mips/tcg/ldst_helper.c | 15 +++++----------
> 2 files changed, 10 insertions(+), 10 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 02/16] target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian()
2024-10-10 21:50 ` [PATCH v2 02/16] target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian() Philippe Mathieu-Daudé
@ 2024-10-13 15:52 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 15:52 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
> Methods using the 'cpu_' prefix usually take a (Arch)CPUState
> argument. Since this method takes a DisasContext argument,
> rename it as disas_is_bigendian().
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/mips/tcg/translate.h | 2 +-
> target/mips/tcg/translate.c | 6 +++---
> target/mips/tcg/nanomips_translate.c.inc | 4 ++--
> 3 files changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 03/16] target/mips: Introduce mo_endian_env() helper
2024-10-10 21:50 ` [PATCH v2 03/16] target/mips: Introduce mo_endian_env() helper Philippe Mathieu-Daudé
@ 2024-10-13 15:52 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 15:52 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
> Introduce mo_endian_env() which returns the endian
> MemOp corresponding to the vCPU env.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Tested-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> ---
> target/mips/internal.h | 5 +++++
> 1 file changed, 5 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 04/16] target/mips: Replace MO_TE by mo_endian_env() in get_pte()
2024-10-10 21:50 ` [PATCH v2 04/16] target/mips: Replace MO_TE by mo_endian_env() in get_pte() Philippe Mathieu-Daudé
@ 2024-10-13 15:53 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 15:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
> Replace compile-time MO_TE evaluation by runtime mo_endian_env()
> one, which expand target endianness from vCPU env.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Tested-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> ---
> target/mips/tcg/sysemu/tlb_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 06/16] target/mips: Factor mo_endian_rev() out of MXU code
2024-10-10 21:50 ` [PATCH v2 06/16] target/mips: Factor mo_endian_rev() out of MXU code Philippe Mathieu-Daudé
@ 2024-10-13 15:59 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 15:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
> Instead of swapping the reversed target endianness
> using MO_BSWAP, directly return the correct endianness.
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/mips/tcg/translate.h | 5 +++++
> target/mips/tcg/mxu_translate.c | 8 ++++----
> 2 files changed, 9 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 07/16] target/mips: Explode MO_TExx -> MO_TE | MO_xx
2024-10-10 21:50 ` [PATCH v2 07/16] target/mips: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
@ 2024-10-13 16:00 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 16:00 UTC (permalink / raw)
To: qemu-devel
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
> Extract the implicit MO_TE definition in order to replace
> it by runtime variable in the next commit.
>
> Mechanical change using:
>
> $ for n in UW UL UQ UO SW SL SQ; do \
> sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
> $(git grep -l MO_TE$n target/mips); \
> done
>
> manually remove superfluous parenthesis in nanoMIPS gen_save().
>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Tested-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/mips/tcg/translate.c | 120 +++++++++++-----------
> target/mips/tcg/tx79_translate.c | 8 +-
> target/mips/tcg/micromips_translate.c.inc | 22 ++--
> target/mips/tcg/mips16e_translate.c.inc | 10 +-
> target/mips/tcg/nanomips_translate.c.inc | 32 +++---
> 5 files changed, 96 insertions(+), 96 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 08/16] target/mips: Rename unused sysemu argument of OP_LD_ATOMIC()
2024-10-10 21:50 ` [PATCH v2 08/16] target/mips: Rename unused sysemu argument of OP_LD_ATOMIC() Philippe Mathieu-Daudé
@ 2024-10-13 16:01 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 16:01 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
> In commit 6d0cad12594 ("target/mips: Finish conversion to
> tcg_gen_qemu_{ld,st}_*") we renamed the argument of the user
> definition. Rename the system part for coherency. Since the
> argument is ignored, prefix with 'ignored_'.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/mips/tcg/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 09/16] target/mips: Introduce mo_endian() helper
2024-10-10 21:50 ` [PATCH v2 09/16] target/mips: Introduce mo_endian() helper Philippe Mathieu-Daudé
@ 2024-10-13 16:01 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 16:01 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
> Introduce mo_endian() which returns the endian MemOp
> corresponding to the vCPU DisasContext.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Tested-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> ---
> target/mips/tcg/translate.h | 5 +++++
> 1 file changed, 5 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 10/16] target/mips: Replace MO_TE by mo_endian()
2024-10-10 21:50 ` [PATCH v2 10/16] target/mips: Replace MO_TE by mo_endian() Philippe Mathieu-Daudé
@ 2024-10-13 16:05 ` Richard Henderson
2024-10-14 22:18 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 16:05 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
> +++ b/target/mips/tcg/msa_helper.c
> @@ -8213,7 +8213,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
>
> #if !defined(CONFIG_USER_ONLY)
> #define MEMOP_IDX(DF) \
> - MemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
> + MemOpIdx oi = make_memop_idx(mo_endian(dc) | DF | MO_UNALN, \
> mips_env_mmu_index(env));
> #else
This one is not within a translation context.
Surely this should be mo_endian_env().
I would have expected this not to compile?
The rest of the changes appear correct, based on filenames.
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 11/16] target/mips: Have gen_addiupc() expand $pc during translation
2024-10-10 21:50 ` [PATCH v2 11/16] target/mips: Have gen_addiupc() expand $pc during translation Philippe Mathieu-Daudé
@ 2024-10-13 16:06 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 16:06 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/mips/tcg/translate.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 12/16] target/mips: Use gen_op_addr_addi() when possible
2024-10-10 21:50 ` [PATCH v2 12/16] target/mips: Use gen_op_addr_addi() when possible Philippe Mathieu-Daudé
@ 2024-10-13 16:11 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 16:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
> Replace tcg_gen_movi_tl() + gen_op_addr_add() by a single
> gen_op_addr_addi() call.
>
> gen_op_addr_addi() calls tcg_gen_addi_tl() which might
> optimize if the immediate is zero.
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> ---
> target/mips/tcg/translate.h | 1 +
> target/mips/tcg/translate.c | 6 ++----
> target/mips/tcg/micromips_translate.c.inc | 12 ++++--------
> target/mips/tcg/mips16e_translate.c.inc | 15 ++++-----------
> target/mips/tcg/nanomips_translate.c.inc | 4 +---
> 5 files changed, 12 insertions(+), 26 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 14/16] target/mips: Expose MIPSCPU::is_big_endian property
2024-10-10 21:50 ` [PATCH v2 14/16] target/mips: Expose MIPSCPU::is_big_endian property Philippe Mathieu-Daudé
@ 2024-10-13 16:14 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 16:14 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
> Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Tested-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> ---
> target/mips/cpu.h | 3 +++
> target/mips/cpu.c | 12 ++++++++----
> 2 files changed, 11 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 15/16] hw/mips/cps: Set the vCPU 'cpu-big-endian' property
2024-10-10 21:50 ` [PATCH v2 15/16] hw/mips/cps: Set the vCPU 'cpu-big-endian' property Philippe Mathieu-Daudé
@ 2024-10-13 16:58 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 16:58 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
> Have the CPS expose a 'cpu-big-endian' property so it can
> set it to the vCPUs it creates.
> Note, since the number of vCPUs created is dynamic, we can
> not use QOM aliases.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Tested-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> ---
> include/hw/mips/cps.h | 1 +
> hw/mips/cps.c | 4 ++++
> hw/mips/malta.c | 2 ++
> 3 files changed, 7 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 16/16] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument
2024-10-10 21:50 ` [PATCH v2 16/16] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument Philippe Mathieu-Daudé
@ 2024-10-13 17:00 ` Richard Henderson
0 siblings, 0 replies; 34+ messages in thread
From: Richard Henderson @ 2024-10-13 17:00 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
> mips_cpu_create_with_clock() creates a vCPU. Pass it the vCPU
> endianness requested by argument. Update the board call sites.
>
> Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org>
> Reviewed-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> Tested-by: Jiaxun Yang<jiaxun.yang@flygoat.com>
> ---
> target/mips/cpu.h | 4 +++-
> hw/mips/fuloong2e.c | 2 +-
> hw/mips/jazz.c | 2 +-
> hw/mips/loongson3_virt.c | 2 +-
> hw/mips/malta.c | 3 ++-
> hw/mips/mipssim.c | 2 +-
> target/mips/cpu.c | 5 ++++-
> 7 files changed, 13 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 10/16] target/mips: Replace MO_TE by mo_endian()
2024-10-13 16:05 ` Richard Henderson
@ 2024-10-14 22:18 ` Philippe Mathieu-Daudé
2024-10-14 23:13 ` Richard Henderson
0 siblings, 1 reply; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-14 22:18 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 13/10/24 13:05, Richard Henderson wrote:
> On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
>> +++ b/target/mips/tcg/msa_helper.c
>> @@ -8213,7 +8213,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env,
>> uint32_t df, uint32_t wd,
>> #if !defined(CONFIG_USER_ONLY)
>> #define
>> MEMOP_IDX(DF) \
>> - MemOpIdx oi = make_memop_idx(MO_TE | DF |
>> MO_UNALN, \
>> + MemOpIdx oi = make_memop_idx(mo_endian(dc) | DF |
>> MO_UNALN, \
>> mips_env_mmu_index(env));
>> #else
>
> This one is not within a translation context.
> Surely this should be mo_endian_env().
>
> I would have expected this not to compile?
Dead code since commit 948f88661c6 ("target/mips: Use cpu_*_data_ra
for msa load/store"):
$ git grep -w MEMOP_IDX
target/mips/tcg/msa_helper.c:8215:#define MEMOP_IDX(DF)
\
target/mips/tcg/msa_helper.c:8219:#define MEMOP_IDX(DF)
I'll send a cleanup patch removing the #define lines.
>
> The rest of the changes appear correct, based on filenames.
Might I use your R-b tag on this patch, removing the tcg/msa_helper.c
change?
Regards,
Phil.
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 10/16] target/mips: Replace MO_TE by mo_endian()
2024-10-14 22:18 ` Philippe Mathieu-Daudé
@ 2024-10-14 23:13 ` Richard Henderson
2024-10-15 14:45 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 34+ messages in thread
From: Richard Henderson @ 2024-10-14 23:13 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 10/14/24 15:18, Philippe Mathieu-Daudé wrote:
> On 13/10/24 13:05, Richard Henderson wrote:
>> On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
>>> +++ b/target/mips/tcg/msa_helper.c
>>> @@ -8213,7 +8213,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df,
>>> uint32_t wd,
>>> #if !defined(CONFIG_USER_ONLY)
>>> #define MEMOP_IDX(DF) \
>>> - MemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
>>> + MemOpIdx oi = make_memop_idx(mo_endian(dc) | DF | MO_UNALN, \
>>> mips_env_mmu_index(env));
>>> #else
>>
>> This one is not within a translation context.
>> Surely this should be mo_endian_env().
>>
>> I would have expected this not to compile?
>
> Dead code since commit 948f88661c6 ("target/mips: Use cpu_*_data_ra
> for msa load/store"):
>
> $ git grep -w MEMOP_IDX
> target/mips/tcg/msa_helper.c:8215:#define MEMOP_IDX(DF) \
> target/mips/tcg/msa_helper.c:8219:#define MEMOP_IDX(DF)
>
> I'll send a cleanup patch removing the #define lines.
Ah, excellent.
> Might I use your R-b tag on this patch, removing the tcg/msa_helper.c change?
Yes.
r~
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v2 10/16] target/mips: Replace MO_TE by mo_endian()
2024-10-14 23:13 ` Richard Henderson
@ 2024-10-15 14:45 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 34+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-15 14:45 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Huacai Chen, Jiaxun Yang, Hervé Poussineau,
Aleksandar Rikalo, Aurelien Jarno
On 14/10/24 20:13, Richard Henderson wrote:
> On 10/14/24 15:18, Philippe Mathieu-Daudé wrote:
>> On 13/10/24 13:05, Richard Henderson wrote:
>>> On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
>>>> +++ b/target/mips/tcg/msa_helper.c
>>>> @@ -8213,7 +8213,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env,
>>>> uint32_t df, uint32_t wd,
>>>> #if !defined(CONFIG_USER_ONLY)
>>>> #define
>>>> MEMOP_IDX(DF) \
>>>> - MemOpIdx oi = make_memop_idx(MO_TE | DF |
>>>> MO_UNALN, \
>>>> + MemOpIdx oi = make_memop_idx(mo_endian(dc) | DF |
>>>> MO_UNALN, \
>>>> mips_env_mmu_index(env));
>>>> #else
>>>
>>> This one is not within a translation context.
>>> Surely this should be mo_endian_env().
>>>
>>> I would have expected this not to compile?
>>
>> Dead code since commit 948f88661c6 ("target/mips: Use cpu_*_data_ra
>> for msa load/store"):
>>
>> $ git grep -w MEMOP_IDX
>> target/mips/tcg/msa_helper.c:8215:#define MEMOP_IDX(DF)
>> \
>> target/mips/tcg/msa_helper.c:8219:#define MEMOP_IDX(DF)
>>
>> I'll send a cleanup patch removing the #define lines.
>
> Ah, excellent.
>
>> Might I use your R-b tag on this patch, removing the tcg/msa_helper.c
>> change?
>
> Yes.
Thanks! Series queued then.
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2024-10-15 14:46 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-10 21:49 [PATCH v2 00/16] target/mips: Remove target-specific endianness knowledge Philippe Mathieu-Daudé
2024-10-10 21:49 ` [PATCH v2 01/16] target/mips: Declare mips_env_is_bigendian() in 'internal.h' Philippe Mathieu-Daudé
2024-10-13 15:51 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 02/16] target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian() Philippe Mathieu-Daudé
2024-10-13 15:52 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 03/16] target/mips: Introduce mo_endian_env() helper Philippe Mathieu-Daudé
2024-10-13 15:52 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 04/16] target/mips: Replace MO_TE by mo_endian_env() in get_pte() Philippe Mathieu-Daudé
2024-10-13 15:53 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 05/16] target/mips: Convert mips16e decr_and_load/store() macros to functions Philippe Mathieu-Daudé
2024-10-10 21:50 ` [PATCH v2 06/16] target/mips: Factor mo_endian_rev() out of MXU code Philippe Mathieu-Daudé
2024-10-13 15:59 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 07/16] target/mips: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2024-10-13 16:00 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 08/16] target/mips: Rename unused sysemu argument of OP_LD_ATOMIC() Philippe Mathieu-Daudé
2024-10-13 16:01 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 09/16] target/mips: Introduce mo_endian() helper Philippe Mathieu-Daudé
2024-10-13 16:01 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 10/16] target/mips: Replace MO_TE by mo_endian() Philippe Mathieu-Daudé
2024-10-13 16:05 ` Richard Henderson
2024-10-14 22:18 ` Philippe Mathieu-Daudé
2024-10-14 23:13 ` Richard Henderson
2024-10-15 14:45 ` Philippe Mathieu-Daudé
2024-10-10 21:50 ` [PATCH v2 11/16] target/mips: Have gen_addiupc() expand $pc during translation Philippe Mathieu-Daudé
2024-10-13 16:06 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 12/16] target/mips: Use gen_op_addr_addi() when possible Philippe Mathieu-Daudé
2024-10-13 16:11 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 13/16] target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl() Philippe Mathieu-Daudé
2024-10-10 21:50 ` [PATCH v2 14/16] target/mips: Expose MIPSCPU::is_big_endian property Philippe Mathieu-Daudé
2024-10-13 16:14 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 15/16] hw/mips/cps: Set the vCPU 'cpu-big-endian' property Philippe Mathieu-Daudé
2024-10-13 16:58 ` Richard Henderson
2024-10-10 21:50 ` [PATCH v2 16/16] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument Philippe Mathieu-Daudé
2024-10-13 17:00 ` Richard Henderson
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