From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Ilya Leoshkevich <iii@linux.ibm.com>
Subject: [PULL 04/27] target/i386/gdbstub: Factor out gdb_get_reg() and gdb_write_reg()
Date: Sun, 13 Oct 2024 15:12:12 -0700 [thread overview]
Message-ID: <20241013221235.1585193-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20241013221235.1585193-1-richard.henderson@linaro.org>
From: Ilya Leoshkevich <iii@linux.ibm.com>
i386 gdbstub handles both i386 and x86_64. Factor out two functions
for reading and writing registers without knowing their bitness.
While at it, simplify the TARGET_LONG_BITS == 32 case.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-ID: <20240912093012.402366-4-iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/i386/gdbstub.c | 51 +++++++++++++++++++++++++------------------
1 file changed, 30 insertions(+), 21 deletions(-)
diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c
index 4acf485879..cc5eceeb7e 100644
--- a/target/i386/gdbstub.c
+++ b/target/i386/gdbstub.c
@@ -96,6 +96,19 @@ static int gdb_write_reg_cs64(uint32_t hflags, uint8_t *buf, target_ulong *val)
return 4;
}
+static int gdb_get_reg(CPUX86State *env, GByteArray *mem_buf, target_ulong val)
+{
+ if (TARGET_LONG_BITS == 64) {
+ if (env->hflags & HF_CS64_MASK) {
+ return gdb_get_reg64(mem_buf, val);
+ } else {
+ return gdb_get_reg64(mem_buf, val & 0xffffffffUL);
+ }
+ } else {
+ return gdb_get_reg32(mem_buf, val);
+ }
+}
+
int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
X86CPU *cpu = X86_CPU(cs);
@@ -137,15 +150,7 @@ int x86_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
} else {
switch (n) {
case IDX_IP_REG:
- if (TARGET_LONG_BITS == 64) {
- if (env->hflags & HF_CS64_MASK) {
- return gdb_get_reg64(mem_buf, env->eip);
- } else {
- return gdb_get_reg64(mem_buf, env->eip & 0xffffffffUL);
- }
- } else {
- return gdb_get_reg32(mem_buf, env->eip);
- }
+ return gdb_get_reg(env, mem_buf, env->eip);
case IDX_FLAGS_REG:
return gdb_get_reg32(mem_buf, env->eflags);
@@ -248,6 +253,21 @@ static int x86_cpu_gdb_load_seg(X86CPU *cpu, X86Seg sreg, uint8_t *mem_buf)
return 4;
}
+static int gdb_write_reg(CPUX86State *env, uint8_t *mem_buf, target_ulong *val)
+{
+ if (TARGET_LONG_BITS == 64) {
+ if (env->hflags & HF_CS64_MASK) {
+ *val = ldq_p(mem_buf);
+ } else {
+ *val = ldq_p(mem_buf) & 0xffffffffUL;
+ }
+ return 8;
+ } else {
+ *val = (uint32_t)ldl_p(mem_buf);
+ return 4;
+ }
+}
+
int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
X86CPU *cpu = X86_CPU(cs);
@@ -288,18 +308,7 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
} else {
switch (n) {
case IDX_IP_REG:
- if (TARGET_LONG_BITS == 64) {
- if (env->hflags & HF_CS64_MASK) {
- env->eip = ldq_p(mem_buf);
- } else {
- env->eip = ldq_p(mem_buf) & 0xffffffffUL;
- }
- return 8;
- } else {
- env->eip &= ~0xffffffffUL;
- env->eip |= (uint32_t)ldl_p(mem_buf);
- return 4;
- }
+ return gdb_write_reg(env, mem_buf, &env->eip);
case IDX_FLAGS_REG:
env->eflags = ldl_p(mem_buf);
return 4;
--
2.43.0
next prev parent reply other threads:[~2024-10-13 22:16 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-13 22:12 [PULL 00/27] tcg + linux patch queue Richard Henderson
2024-10-13 22:12 ` [PULL 01/27] tcg: remove singlestep_enabled from DisasContextBase Richard Henderson
2024-10-13 22:12 ` [PULL 02/27] include/exec: Introduce env_cpu_const() Richard Henderson
2024-10-13 22:12 ` [PULL 03/27] linux-user/i386: Emulate orig_ax Richard Henderson
2024-10-13 22:12 ` Richard Henderson [this message]
2024-10-13 22:12 ` [PULL 05/27] target/i386/gdbstub: Expose orig_ax Richard Henderson
2024-10-13 22:12 ` [PULL 06/27] tests/tcg: Run test-proc-mappings.py on i386 Richard Henderson
2024-10-13 22:12 ` [PULL 07/27] linux-user/vm86: Fix compilation with Clang Richard Henderson
2024-10-13 22:12 ` [PULL 08/27] accel/tcg: Assert noreturn from write-only page for atomics Richard Henderson
2024-10-13 22:12 ` [PULL 09/27] include/exec/memop: Move get_alignment_bits from tcg.h Richard Henderson
2024-10-13 22:12 ` [PULL 10/27] include/exec/memop: Rename get_alignment_bits Richard Henderson
2024-10-13 22:12 ` [PULL 11/27] include/exec/memop: Introduce memop_atomicity_bits Richard Henderson
2024-10-13 22:12 ` [PULL 12/27] accel/tcg: Add TCGCPUOps.tlb_fill_align Richard Henderson
2024-10-13 22:12 ` [PULL 13/27] accel/tcg: Use the alignment test in tlb_fill_align Richard Henderson
2024-10-13 22:12 ` [PULL 14/27] target/hppa: Add MemOp argument to hppa_get_physical_address Richard Henderson
2024-10-13 22:12 ` [PULL 15/27] target/hppa: Perform access rights before protection id check Richard Henderson
2024-10-13 22:12 ` [PULL 16/27] target/hppa: Fix priority of T, D, and B page faults Richard Henderson
2024-10-13 22:12 ` [PULL 17/27] target/hppa: Handle alignment faults in hppa_get_physical_address Richard Henderson
2024-10-13 22:12 ` [PULL 18/27] target/hppa: Implement TCGCPUOps.tlb_fill_align Richard Henderson
2024-10-13 22:12 ` [PULL 19/27] target/arm: Pass MemOp to get_phys_addr Richard Henderson
2024-10-13 22:12 ` [PULL 20/27] target/arm: Pass MemOp to get_phys_addr_with_space_nogpc Richard Henderson
2024-10-13 22:12 ` [PULL 21/27] target/arm: Pass MemOp to get_phys_addr_gpc Richard Henderson
2024-10-13 22:12 ` [PULL 22/27] target/arm: Pass MemOp to get_phys_addr_nogpc Richard Henderson
2024-10-13 22:12 ` [PULL 23/27] target/arm: Pass MemOp through get_phys_addr_twostage Richard Henderson
2024-10-13 22:12 ` [PULL 24/27] target/arm: Pass MemOp to get_phys_addr_lpae Richard Henderson
2024-10-13 22:12 ` [PULL 25/27] target/arm: Move device detection earlier in get_phys_addr_lpae Richard Henderson
2024-10-13 22:12 ` [PULL 26/27] target/arm: Implement TCGCPUOps.tlb_fill_align Richard Henderson
2024-10-13 22:12 ` [PULL 27/27] target/arm: Fix alignment fault priority in get_phys_addr_lpae Richard Henderson
2024-10-14 12:03 ` [PULL 00/27] tcg + linux patch queue Peter Maydell
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