From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/28] hw/arm/stm32f405: Add RCC device to stm32f405 SoC
Date: Tue, 15 Oct 2024 11:37:43 +0100 [thread overview]
Message-ID: <20241015103808.133024-4-peter.maydell@linaro.org> (raw)
In-Reply-To: <20241015103808.133024-1-peter.maydell@linaro.org>
From: Román Cárdenas Rodríguez <rcardenas.rod@gmail.com>
Add the reset and clock controller device to the stm32f405 SoC.
Signed-off-by: Roman Cardenas Rodriguez <rcardenas.rod@gmail.com>
[PMM: tweak commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/stm32.rst | 3 ++-
include/hw/arm/stm32f405_soc.h | 2 ++
hw/arm/stm32f405_soc.c | 12 +++++++++++-
hw/arm/Kconfig | 1 +
4 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst
index 3b640f3ee07..ca7a55841b4 100644
--- a/docs/system/arm/stm32.rst
+++ b/docs/system/arm/stm32.rst
@@ -36,6 +36,7 @@ Supported devices
* SPI controller
* System configuration (SYSCFG)
* Timer controller (TIMER)
+ * Reset and Clock Controller (RCC) (STM32F4 only, reset and enable only)
Missing devices
---------------
@@ -53,7 +54,7 @@ Missing devices
* Power supply configuration (PWR)
* Random Number Generator (RNG)
* Real-Time Clock (RTC) controller
- * Reset and Clock Controller (RCC)
+ * Reset and Clock Controller (RCC) (other features than reset and enable)
* Secure Digital Input/Output (SDIO) interface
* USB OTG
* Watchdog controller (IWDG, WWDG)
diff --git a/include/hw/arm/stm32f405_soc.h b/include/hw/arm/stm32f405_soc.h
index d15c03c4b5d..2eeada64ded 100644
--- a/include/hw/arm/stm32f405_soc.h
+++ b/include/hw/arm/stm32f405_soc.h
@@ -25,6 +25,7 @@
#ifndef HW_ARM_STM32F405_SOC_H
#define HW_ARM_STM32F405_SOC_H
+#include "hw/misc/stm32_rcc.h"
#include "hw/misc/stm32f4xx_syscfg.h"
#include "hw/timer/stm32f2xx_timer.h"
#include "hw/char/stm32f2xx_usart.h"
@@ -55,6 +56,7 @@ struct STM32F405State {
ARMv7MState armv7m;
+ STM32RccState rcc;
STM32F4xxSyscfgState syscfg;
STM32F4xxExtiState exti;
STM32F2XXUsartState usart[STM_NUM_USARTS];
diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c
index 2ad5b79a069..72ae62156f3 100644
--- a/hw/arm/stm32f405_soc.c
+++ b/hw/arm/stm32f405_soc.c
@@ -30,6 +30,7 @@
#include "hw/qdev-clock.h"
#include "hw/misc/unimp.h"
+#define RCC_ADDR 0x40023800
#define SYSCFG_ADD 0x40013800
static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
0x40004C00, 0x40005000, 0x40011400,
@@ -59,6 +60,8 @@ static void stm32f405_soc_initfn(Object *obj)
object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
+ object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32_RCC);
+
object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG);
for (i = 0; i < STM_NUM_USARTS; i++) {
@@ -160,6 +163,14 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
return;
}
+ /* Reset and clock controller */
+ dev = DEVICE(&s->rcc);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->rcc), errp)) {
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, RCC_ADDR);
+
/* System configuration controller */
dev = DEVICE(&s->syscfg);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) {
@@ -276,7 +287,6 @@ static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
create_unimplemented_device("GPIOH", 0x40021C00, 0x400);
create_unimplemented_device("GPIOI", 0x40022000, 0x400);
create_unimplemented_device("CRC", 0x40023000, 0x400);
- create_unimplemented_device("RCC", 0x40023800, 0x400);
create_unimplemented_device("Flash Int", 0x40023C00, 0x400);
create_unimplemented_device("BKPSRAM", 0x40024000, 0x400);
create_unimplemented_device("DMA1", 0x40026000, 0x400);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index e7b9cfb59c0..f1e981622a1 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -397,6 +397,7 @@ config STM32F405_SOC
bool
select ARM_V7M
select OR_IRQ
+ select STM32_RCC
select STM32F4XX_SYSCFG
select STM32F4XX_EXTI
--
2.34.1
next prev parent reply other threads:[~2024-10-15 10:41 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-15 10:37 [PULL 00/28] target-arm queue Peter Maydell
2024-10-15 10:37 ` [PULL 01/28] hw/arm/omap1: Remove unused omap_uwire_attach() method Peter Maydell
2024-10-15 10:37 ` [PULL 02/28] hw/misc/stm32_rcc: Implement RCC device for STM32F4 SoCs Peter Maydell
2024-10-15 10:37 ` Peter Maydell [this message]
2024-10-15 10:37 ` [PULL 04/28] hw/intc/arm_gicv3: Add cast to match the documentation Peter Maydell
2024-10-15 10:37 ` [PULL 05/28] " Peter Maydell
2024-10-15 10:37 ` [PULL 06/28] hw/intc/arm_gicv3_cpuif: " Peter Maydell
2024-10-15 10:37 ` [PULL 07/28] hw/misc: Create STM32L4x5 SYSCFG clock Peter Maydell
2024-10-15 10:37 ` [PULL 08/28] hw/clock: Expose 'qtest-clock-period' QOM property for QTests Peter Maydell
2024-10-15 10:37 ` [PULL 09/28] tests/qtest: Check STM32L4x5 clock connections Peter Maydell
2024-10-15 10:37 ` [PULL 10/28] hw/ssi: Allwinner A10 SPI emulation Peter Maydell
2024-10-15 10:37 ` [PULL 11/28] hw/arm: Add SPI to Allwinner A10 Peter Maydell
2024-10-15 10:37 ` [PULL 12/28] hw/intc/omap_intc: Remove now-unnecessary abstract base class Peter Maydell
2024-10-15 10:37 ` [PULL 13/28] hw/char/pl011: Use correct masks for IBRD and FBRD Peter Maydell
2024-10-15 10:37 ` [PULL 14/28] docs/devel/blkdebug: Convert to rST format Peter Maydell
2024-10-15 10:37 ` [PULL 15/28] docs/devel/blkverify: " Peter Maydell
2024-10-15 10:37 ` [PULL 16/28] docs/devel/lockcnt: " Peter Maydell
2024-10-15 10:37 ` [PULL 17/28] docs/devel/multiple-iothreads: " Peter Maydell
2024-10-15 10:37 ` [PULL 18/28] docs/devel/rcu: " Peter Maydell
2024-10-15 10:37 ` [PULL 19/28] include: Move QemuLockCnt APIs to their own header Peter Maydell
2024-10-15 10:38 ` [PULL 20/28] docs/devel/lockcnt: Include kernel-doc API documentation Peter Maydell
2024-10-15 10:38 ` [PULL 21/28] hw/adc: Remove MAX111X device Peter Maydell
2024-10-15 10:38 ` [PULL 22/28] hw/gpio: Remove MAX7310 device Peter Maydell
2024-10-15 10:38 ` [PULL 23/28] hw/ide: Remove DSCM-1XXXX microdrive device model Peter Maydell
2024-10-15 10:38 ` [PULL 24/28] hw: Remove PCMCIA subsystem Peter Maydell
2024-10-15 10:38 ` [PULL 25/28] hw/block: Remove ecc Peter Maydell
2024-10-15 10:38 ` [PULL 26/28] vl.c: Remove pxa2xx-specific -portrait and -rotate options Peter Maydell
2024-10-15 10:38 ` [PULL 27/28] dma: Fix function names in documentation Peter Maydell
2024-10-15 10:38 ` [PULL 28/28] hw/arm/xilinx_zynq: Add various missing unimplemented devices Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241015103808.133024-4-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).