From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: Chao Gao <chao.gao@intel.com>
Subject: [PULL 05/25] target/i386: Add more features enumerated by CPUID.7.2.EDX
Date: Tue, 15 Oct 2024 16:16:51 +0200 [thread overview]
Message-ID: <20241015141711.528342-6-pbonzini@redhat.com> (raw)
In-Reply-To: <20241015141711.528342-1-pbonzini@redhat.com>
From: Chao Gao <chao.gao@intel.com>
Following 5 bits in CPUID.7.2.EDX are supported by KVM. Add their
supports in QEMU. Each of them indicates certain bits of IA32_SPEC_CTRL
are supported. Those bits can control CPU speculation behavior which can
be used to defend against side-channel attacks.
bit0: intel-psfd
if 1, indicates bit 7 of the IA32_SPEC_CTRL MSR is supported. Bit 7 of
this MSR disables Fast Store Forwarding Predictor without disabling
Speculative Store Bypass
bit1: ipred-ctrl
If 1, indicates bits 3 and 4 of the IA32_SPEC_CTRL MSR are supported.
Bit 3 of this MSR enables IPRED_DIS control for CPL3. Bit 4 of this
MSR enables IPRED_DIS control for CPL0/1/2
bit2: rrsba-ctrl
If 1, indicates bits 5 and 6 of the IA32_SPEC_CTRL MSR are supported.
Bit 5 of this MSR disables RRSBA behavior for CPL3. Bit 6 of this MSR
disables RRSBA behavior for CPL0/1/2
bit3: ddpd-u
If 1, indicates bit 8 of the IA32_SPEC_CTRL MSR is supported. Bit 8 of
this MSR disables Data Dependent Prefetcher.
bit4: bhi-ctrl
if 1, indicates bit 10 of the IA32_SPEC_CTRL MSR is supported. Bit 10
of this MSR enables BHI_DIS_S behavior.
Signed-off-by: Chao Gao <chao.gao@intel.com>
Link: https://lore.kernel.org/r/20240919051011.118309-1-chao.gao@intel.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 5535f4e6ab4..9a6b9e9e51b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1148,8 +1148,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
[FEAT_7_2_EDX] = {
.type = CPUID_FEATURE_WORD,
.feat_names = {
- NULL, NULL, NULL, NULL,
- NULL, "mcdt-no", NULL, NULL,
+ "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u",
+ "bhi-ctrl", "mcdt-no", NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
--
2.46.2
next prev parent reply other threads:[~2024-10-15 14:18 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-15 14:16 [PULL 00/25] x86 and KVM patches for 2024-10-15 Paolo Bonzini
2024-10-15 14:16 ` [PULL 01/25] target/i386: Don't construct a all-zero entry for CPUID[0xD 0x3f] Paolo Bonzini
2024-10-15 14:16 ` [PULL 02/25] target/i386: Enable fdp-excptn-only and zero-fcs-fds Paolo Bonzini
2024-10-15 14:16 ` [PULL 03/25] target/i386: Construct CPUID 2 as stateful iff times > 1 Paolo Bonzini
2024-10-15 14:16 ` [PULL 04/25] target/i386: Make invtsc migratable when user sets tsc-khz explicitly Paolo Bonzini
2024-10-15 14:16 ` Paolo Bonzini [this message]
2024-10-15 14:16 ` [PULL 06/25] target/i386: Add support save/load HWCR MSR Paolo Bonzini
2024-10-15 14:16 ` [PULL 07/25] target/i386: Fix conditional CONFIG_SYNDBG enablement Paolo Bonzini
2024-10-15 14:16 ` [PULL 08/25] target/i386: Exclude 'hv-syndbg' from 'hv-passthrough' Paolo Bonzini
2024-10-15 14:16 ` [PULL 09/25] target/i386: Make sure SynIC state is really updated before KVM_RUN Paolo Bonzini
2024-10-15 14:16 ` [PULL 10/25] docs/system: Add recommendations to Hyper-V enlightenments doc Paolo Bonzini
2024-10-15 14:16 ` [PULL 11/25] target/i386: convert bit test instructions to new decoder Paolo Bonzini
2024-10-15 14:16 ` [PULL 12/25] target/i386: decode address before going back to translate.c Paolo Bonzini
2024-10-15 14:16 ` [PULL 13/25] target/i386: convert CMPXCHG8B/CMPXCHG16B to new decoder Paolo Bonzini
2024-10-16 16:37 ` Philippe Mathieu-Daudé
2024-10-17 9:14 ` Paolo Bonzini
2024-10-15 14:17 ` [PULL 14/25] target/i386: do not check PREFIX_LOCK in old-style decoder Paolo Bonzini
2024-10-15 14:17 ` [PULL 15/25] target/i386: list instructions still in translate.c Paolo Bonzini
2024-10-15 14:17 ` [PULL 16/25] target/i386: assert that cc_op* and pc_save are preserved Paolo Bonzini
2024-10-15 14:17 ` [PULL 17/25] KVM: Dynamic sized kvm memslots array Paolo Bonzini
2024-10-15 14:17 ` [PULL 18/25] KVM: Define KVM_MEMSLOTS_NUM_MAX_DEFAULT Paolo Bonzini
2024-10-15 14:17 ` [PULL 19/25] KVM: Rename KVMMemoryListener.nr_used_slots to nr_slots_used Paolo Bonzini
2024-10-15 14:17 ` [PULL 20/25] KVM: Rename KVMState->nr_slots to nr_slots_max Paolo Bonzini
2024-10-15 14:17 ` [PULL 21/25] target/i386/tcg: Use DPL-level accesses for interrupts and call gates Paolo Bonzini
2024-10-15 14:17 ` [PULL 22/25] accel/kvm: check for KVM_CAP_MULTI_ADDRESS_SPACE on vm Paolo Bonzini
2024-10-15 14:17 ` [PULL 23/25] accel/kvm: check for KVM_CAP_MEMORY_ATTRIBUTES " Paolo Bonzini
2024-10-15 14:17 ` [PULL 24/25] accel/kvm: check for KVM_CAP_READONLY_MEM on VM Paolo Bonzini
2024-10-15 14:17 ` [PULL 25/25] target/i386: Use only 16 and 32-bit operands for IN/OUT Paolo Bonzini
2024-10-17 10:32 ` [PULL 00/25] x86 and KVM patches for 2024-10-15 Peter Maydell
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