* [PULL v2 00/28] target-arm queue
@ 2024-10-15 14:18 Peter Maydell
2024-10-15 16:30 ` Peter Maydell
0 siblings, 1 reply; 6+ messages in thread
From: Peter Maydell @ 2024-10-15 14:18 UTC (permalink / raw)
To: qemu-devel
v2: added missing qtest_quit() call to the new STM32L4x5 qtest,
which was causing the test to hang on OpenBSD.
-- PMM
The following changes since commit 35152940b78e478b97051a799cb6275ced03192e:
Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2024-10-14 17:05:25 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241015-1
for you to fetch changes up to f160a4f8d0ef322377db3519c0aa088ccd99edf1:
hw/arm/xilinx_zynq: Add various missing unimplemented devices (2024-10-15 15:16:17 +0100)
----------------------------------------------------------------
target-arm queue:
* hw/arm/omap1: Remove unused omap_uwire_attach() method
* stm32f405: Add RCC device to stm32f405 SoC
* arm/gicv3: add missing casts
* hw/misc: Create STM32L4x5 SYSCFG clock
* hw/arm: Add SPI to Allwinner A10
* hw/intc/omap_intc: Remove now-unnecessary abstract base class
* hw/char/pl011: Use correct masks for IBRD and FBRD
* docs/devel: Convert txt files to rST
* Remove MAX111X, MAX7310, DSCM-1XXXX, pcmcia devices (used only
by now-removed omap/pxa2xx boards)
* vl.c: Remove pxa2xx-specific -portrait and -rotate options
* dma: Fix function names in documentation
* hw/arm/xilinx_zynq: Add various missing unimplemented devices
----------------------------------------------------------------
Akihiko Odaki (1):
dma: Fix function names in documentation
Alexandra Diupina (3):
hw/intc/arm_gicv3: Add cast to match the documentation
hw/intc/arm_gicv3: Add cast to match the documentation
hw/intc/arm_gicv3_cpuif: Add cast to match the documentation
Chao Liu (1):
hw/arm/xilinx_zynq: Add various missing unimplemented devices
Inès Varhol (3):
hw/misc: Create STM32L4x5 SYSCFG clock
hw/clock: Expose 'qtest-clock-period' QOM property for QTests
tests/qtest: Check STM32L4x5 clock connections
Peter Maydell (15):
hw/intc/omap_intc: Remove now-unnecessary abstract base class
hw/char/pl011: Use correct masks for IBRD and FBRD
docs/devel/blkdebug: Convert to rST format
docs/devel/blkverify: Convert to rST format
docs/devel/lockcnt: Convert to rST format
docs/devel/multiple-iothreads: Convert to rST format
docs/devel/rcu: Convert to rST format
include: Move QemuLockCnt APIs to their own header
docs/devel/lockcnt: Include kernel-doc API documentation
hw/adc: Remove MAX111X device
hw/gpio: Remove MAX7310 device
hw/ide: Remove DSCM-1XXXX microdrive device model
hw: Remove PCMCIA subsystem
hw/block: Remove ecc
vl.c: Remove pxa2xx-specific -portrait and -rotate options
Philippe Mathieu-Daudé (1):
hw/arm/omap1: Remove unused omap_uwire_attach() method
Román Cárdenas Rodríguez (2):
hw/misc/stm32_rcc: Implement RCC device for STM32F4 SoCs
hw/arm/stm32f405: Add RCC device to stm32f405 SoC
Strahinja Jankovic (2):
hw/ssi: Allwinner A10 SPI emulation
hw/arm: Add SPI to Allwinner A10
MAINTAINERS | 10 +-
docs/about/removed-features.rst | 23 +
docs/devel/blkdebug.txt | 162 ------
docs/devel/clocks.rst | 6 +
docs/devel/index-api.rst | 1 +
docs/devel/index-internals.rst | 2 +
docs/devel/{lockcnt.txt => lockcnt.rst} | 89 +--
docs/devel/multiple-iothreads.rst | 139 +++++
docs/devel/multiple-iothreads.txt | 130 -----
docs/devel/{rcu.txt => rcu.rst} | 172 +++---
docs/devel/testing/blkdebug.rst | 177 ++++++
.../devel/{blkverify.txt => testing/blkverify.rst} | 30 +-
docs/devel/testing/index.rst | 2 +
docs/system/arm/cubieboard.rst | 1 +
docs/system/arm/stm32.rst | 3 +-
include/block/aio.h | 1 +
include/hw/adc/max111x.h | 56 --
include/hw/arm/allwinner-a10.h | 2 +
include/hw/arm/omap.h | 10 +-
include/hw/arm/stm32f405_soc.h | 2 +
include/hw/block/flash.h | 11 -
include/hw/core/cpu.h | 1 +
include/hw/misc/stm32_rcc.h | 91 +++
include/hw/misc/stm32l4x5_syscfg.h | 1 +
include/hw/pcmcia.h | 66 ---
include/hw/ssi/allwinner-a10-spi.h | 57 ++
include/qemu/lockcnt.h | 130 +++++
include/qemu/thread.h | 111 ----
include/sysemu/dma.h | 11 +-
include/sysemu/sysemu.h | 1 -
tests/qtest/stm32l4x5.h | 42 ++
accel/accel-blocker.c | 1 +
hw/adc/max111x.c | 236 --------
hw/arm/allwinner-a10.c | 8 +
hw/arm/omap1.c | 29 +-
hw/arm/stm32f405_soc.c | 12 +-
hw/arm/stm32l4x5_soc.c | 2 +
hw/arm/xilinx_zynq.c | 70 +++
hw/block/ecc.c | 91 ---
hw/char/pl011.c | 4 +-
hw/core/clock.c | 16 +
hw/core/cpu-common.c | 1 +
hw/gpio/max7310.c | 217 -------
hw/ide/microdrive.c | 644 ---------------------
hw/intc/arm_gicv3_cpuif.c | 6 +-
hw/intc/omap_intc.c | 13 +-
hw/misc/stm32_rcc.c | 162 ++++++
hw/misc/stm32l4x5_syscfg.c | 19 +-
hw/pcmcia/pcmcia.c | 24 -
hw/ssi/allwinner-a10-spi.c | 561 ++++++++++++++++++
system/globals.c | 1 -
system/vl.c | 11 -
tests/qtest/stm32l4x5_gpio-test.c | 23 +
tests/qtest/stm32l4x5_syscfg-test.c | 20 +-
tests/qtest/stm32l4x5_usart-test.c | 28 +
ui/input.c | 36 --
util/aio-posix.c | 1 +
util/aio-win32.c | 1 +
util/async.c | 1 +
util/fdmon-epoll.c | 1 +
util/lockcnt.c | 1 +
hw/Kconfig | 1 -
hw/adc/Kconfig | 3 -
hw/adc/meson.build | 1 -
hw/arm/Kconfig | 3 +-
hw/block/Kconfig | 3 -
hw/block/meson.build | 1 -
hw/gpio/Kconfig | 4 -
hw/gpio/meson.build | 1 -
hw/ide/Kconfig | 6 -
hw/ide/meson.build | 1 -
hw/meson.build | 1 -
hw/misc/Kconfig | 4 +-
hw/misc/meson.build | 1 +
hw/misc/trace-events | 6 +
hw/pcmcia/Kconfig | 2 -
hw/pcmcia/meson.build | 1 -
hw/ssi/Kconfig | 4 +
hw/ssi/meson.build | 1 +
hw/ssi/trace-events | 10 +
qemu-options.hx | 16 -
81 files changed, 1802 insertions(+), 2048 deletions(-)
delete mode 100644 docs/devel/blkdebug.txt
rename docs/devel/{lockcnt.txt => lockcnt.rst} (75%)
create mode 100644 docs/devel/multiple-iothreads.rst
delete mode 100644 docs/devel/multiple-iothreads.txt
rename docs/devel/{rcu.txt => rcu.rst} (73%)
create mode 100644 docs/devel/testing/blkdebug.rst
rename docs/devel/{blkverify.txt => testing/blkverify.rst} (77%)
delete mode 100644 include/hw/adc/max111x.h
create mode 100644 include/hw/misc/stm32_rcc.h
delete mode 100644 include/hw/pcmcia.h
create mode 100644 include/hw/ssi/allwinner-a10-spi.h
create mode 100644 include/qemu/lockcnt.h
create mode 100644 tests/qtest/stm32l4x5.h
delete mode 100644 hw/adc/max111x.c
delete mode 100644 hw/block/ecc.c
delete mode 100644 hw/gpio/max7310.c
delete mode 100644 hw/ide/microdrive.c
create mode 100644 hw/misc/stm32_rcc.c
delete mode 100644 hw/pcmcia/pcmcia.c
create mode 100644 hw/ssi/allwinner-a10-spi.c
delete mode 100644 hw/pcmcia/Kconfig
delete mode 100644 hw/pcmcia/meson.build
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PULL v2 00/28] target-arm queue
2024-10-15 14:18 [PULL v2 00/28] target-arm queue Peter Maydell
@ 2024-10-15 16:30 ` Peter Maydell
0 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2024-10-15 16:30 UTC (permalink / raw)
To: qemu-devel
On Tue, 15 Oct 2024 at 15:18, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> v2: added missing qtest_quit() call to the new STM32L4x5 qtest,
> which was causing the test to hang on OpenBSD.
>
> -- PMM
>
> The following changes since commit 35152940b78e478b97051a799cb6275ced03192e:
>
> Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2024-10-14 17:05:25 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241015-1
>
> for you to fetch changes up to f160a4f8d0ef322377db3519c0aa088ccd99edf1:
>
> hw/arm/xilinx_zynq: Add various missing unimplemented devices (2024-10-15 15:16:17 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * hw/arm/omap1: Remove unused omap_uwire_attach() method
> * stm32f405: Add RCC device to stm32f405 SoC
> * arm/gicv3: add missing casts
> * hw/misc: Create STM32L4x5 SYSCFG clock
> * hw/arm: Add SPI to Allwinner A10
> * hw/intc/omap_intc: Remove now-unnecessary abstract base class
> * hw/char/pl011: Use correct masks for IBRD and FBRD
> * docs/devel: Convert txt files to rST
> * Remove MAX111X, MAX7310, DSCM-1XXXX, pcmcia devices (used only
> by now-removed omap/pxa2xx boards)
> * vl.c: Remove pxa2xx-specific -portrait and -rotate options
> * dma: Fix function names in documentation
> * hw/arm/xilinx_zynq: Add various missing unimplemented devices
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.2
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PULL v2 00/28] target-arm queue
@ 2022-12-15 17:40 Peter Maydell
2022-12-15 21:39 ` Peter Maydell
2022-12-16 11:47 ` Alex Bennée
0 siblings, 2 replies; 6+ messages in thread
From: Peter Maydell @ 2022-12-15 17:40 UTC (permalink / raw)
To: qemu-devel
drop the sysregs patch as the tcg sysregs test fails
(probably a bug in the test)
-- PMM
The following changes since commit ae2b87341b5ddb0dcb1b3f2d4f586ef18de75873:
Merge tag 'pull-qapi-2022-12-14-v2' of https://repo.or.cz/qemu/armbru into staging (2022-12-14 22:42:14 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221215-1
for you to fetch changes up to 9e406eea309bbe44c7fb17f6af112d2b756854ad:
target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator (2022-12-15 17:37:48 +0000)
----------------------------------------------------------------
target-arm queue:
* hw/arm/virt: Add properties to allow more granular
configuration of use of highmem space
* target/arm: Add Cortex-A55 CPU
* hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
* Implement FEAT_EVT
* Some 3-phase-reset conversions for Arm GIC, SMMU
* hw/arm/boot: set initrd with #address-cells type in fdt
* hw/misc: Move some arm-related files from specific_ss into softmmu_ss
* Restrict arm_cpu_exec_interrupt() to TCG accelerator
----------------------------------------------------------------
Gavin Shan (7):
hw/arm/virt: Introduce virt_set_high_memmap() helper
hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap()
hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()
hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper
hw/arm/virt: Improve high memory region address assignment
hw/arm/virt: Add 'compact-highmem' property
hw/arm/virt: Add properties to disable high memory regions
Luke Starrett (1):
hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
Mihai Carabas (1):
hw/arm/virt: build SMBIOS 19 table
Peter Maydell (15):
target/arm: Allow relevant HCR bits to be written for FEAT_EVT
target/arm: Implement HCR_EL2.TTLBIS traps
target/arm: Implement HCR_EL2.TTLBOS traps
target/arm: Implement HCR_EL2.TICAB,TOCU traps
target/arm: Implement HCR_EL2.TID4 traps
target/arm: Report FEAT_EVT for TCG '-cpu max'
hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset
hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset
hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset
hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset
hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset
hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset
hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset
hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset
hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset
Philippe Mathieu-Daudé (1):
target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator
Schspa Shi (1):
hw/arm/boot: set initrd with #address-cells type in fdt
Thomas Huth (1):
hw/misc: Move some arm-related files from specific_ss into softmmu_ss
Timofey Kutergin (1):
target/arm: Add Cortex-A55 CPU
docs/system/arm/emulation.rst | 1 +
docs/system/arm/virt.rst | 18 +++
include/hw/arm/smmuv3.h | 2 +-
include/hw/arm/virt.h | 2 +
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 2 +-
target/arm/cpu.h | 30 +++++
target/arm/kvm-consts.h | 8 +-
hw/arm/boot.c | 10 +-
hw/arm/smmu-common.c | 7 +-
hw/arm/smmuv3.c | 12 +-
hw/arm/virt.c | 202 +++++++++++++++++++++++++++------
hw/intc/arm_gic_common.c | 7 +-
hw/intc/arm_gic_kvm.c | 14 ++-
hw/intc/arm_gicv3_common.c | 7 +-
hw/intc/arm_gicv3_dist.c | 4 +-
hw/intc/arm_gicv3_its.c | 14 ++-
hw/intc/arm_gicv3_its_common.c | 7 +-
hw/intc/arm_gicv3_its_kvm.c | 14 ++-
hw/intc/arm_gicv3_kvm.c | 14 ++-
hw/misc/imx6_src.c | 2 +-
hw/misc/iotkit-sysctl.c | 1 -
target/arm/cpu.c | 5 +-
target/arm/cpu64.c | 70 ++++++++++++
target/arm/cpu_tcg.c | 1 +
target/arm/helper.c | 135 ++++++++++++++--------
hw/misc/meson.build | 11 +-
26 files changed, 459 insertions(+), 141 deletions(-)
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PULL v2 00/28] target-arm queue
2022-12-15 17:40 Peter Maydell
@ 2022-12-15 21:39 ` Peter Maydell
2022-12-16 11:47 ` Alex Bennée
1 sibling, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2022-12-15 21:39 UTC (permalink / raw)
To: qemu-devel
On Thu, 15 Dec 2022 at 17:40, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> drop the sysregs patch as the tcg sysregs test fails
> (probably a bug in the test)
>
> -- PMM
>
> The following changes since commit ae2b87341b5ddb0dcb1b3f2d4f586ef18de75873:
>
> Merge tag 'pull-qapi-2022-12-14-v2' of https://repo.or.cz/qemu/armbru into staging (2022-12-14 22:42:14 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221215-1
>
> for you to fetch changes up to 9e406eea309bbe44c7fb17f6af112d2b756854ad:
>
> target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator (2022-12-15 17:37:48 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * hw/arm/virt: Add properties to allow more granular
> configuration of use of highmem space
> * target/arm: Add Cortex-A55 CPU
> * hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
> * Implement FEAT_EVT
> * Some 3-phase-reset conversions for Arm GIC, SMMU
> * hw/arm/boot: set initrd with #address-cells type in fdt
> * hw/misc: Move some arm-related files from specific_ss into softmmu_ss
> * Restrict arm_cpu_exec_interrupt() to TCG accelerator
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PULL v2 00/28] target-arm queue
2022-12-15 17:40 Peter Maydell
2022-12-15 21:39 ` Peter Maydell
@ 2022-12-16 11:47 ` Alex Bennée
2022-12-16 11:54 ` Peter Maydell
1 sibling, 1 reply; 6+ messages in thread
From: Alex Bennée @ 2022-12-16 11:47 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
Peter Maydell <peter.maydell@linaro.org> writes:
> drop the sysregs patch as the tcg sysregs test fails
> (probably a bug in the test)
Well I assume because it complains about extra bits leaking into
userspace:
➜ ./qemu-aarch64 ./tests/tcg/aarch64-linux-user/sysregs
Checking Counter registers
ctr_el0 : 0x0000000080038003
cntvct_el0 : 0x017314376c668b73
cntfrq_el0 : 0x0000000003b9aca0
Checking CPUID registers
id_aa64isar0_el1 : 0x1021111110212120
!!extra bits!! : 0x1000000000000000
id_aa64isar1_el1 : 0x0011101101211012
!!extra bits!! : 0x0011100100000000
id_aa64mmfr0_el1 : 0xffffffffff000000
!!extra bits!! : 0xffffffff00000000
id_aa64pfr0_el1 : 0x0001000100110011
id_aa64pfr1_el1 : 0x0000000001000321
!!extra bits!! : 0x0000000001000301
id_aa64dfr0_el1 : 0x0000000000000006
id_aa64zfr0_el1 : 0x0110110100110021 (not RAZ!)
midr_el1 : 0x00000000000f0510
mpidr_el1 : 0x0000000080000000
Remaining registers should fail
id_mmfr0_el1 : 0x00000000deadbeef
id_mmfr1_el1 : 0x00000000deadbeef
id_mmfr2_el1 : 0x00000000deadbeef
id_mmfr3_el1 : 0x00000000deadbeef
mvfr0_el1 : 0x00000000deadbeef
mvfr1_el1 : 0x00000000deadbeef
Extra information leaked to user-space!
So it should have been updated when the API was changed.
>
> -- PMM
>
> The following changes since commit ae2b87341b5ddb0dcb1b3f2d4f586ef18de75873:
>
> Merge tag 'pull-qapi-2022-12-14-v2' of https://repo.or.cz/qemu/armbru into staging (2022-12-14 22:42:14 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221215-1
>
> for you to fetch changes up to 9e406eea309bbe44c7fb17f6af112d2b756854ad:
>
> target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator (2022-12-15 17:37:48 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * hw/arm/virt: Add properties to allow more granular
> configuration of use of highmem space
> * target/arm: Add Cortex-A55 CPU
> * hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
> * Implement FEAT_EVT
> * Some 3-phase-reset conversions for Arm GIC, SMMU
> * hw/arm/boot: set initrd with #address-cells type in fdt
> * hw/misc: Move some arm-related files from specific_ss into softmmu_ss
> * Restrict arm_cpu_exec_interrupt() to TCG accelerator
>
> ----------------------------------------------------------------
> Gavin Shan (7):
> hw/arm/virt: Introduce virt_set_high_memmap() helper
> hw/arm/virt: Rename variable size to region_size in virt_set_high_memmap()
> hw/arm/virt: Introduce variable region_base in virt_set_high_memmap()
> hw/arm/virt: Introduce virt_get_high_memmap_enabled() helper
> hw/arm/virt: Improve high memory region address assignment
> hw/arm/virt: Add 'compact-highmem' property
> hw/arm/virt: Add properties to disable high memory regions
>
> Luke Starrett (1):
> hw/intc/arm_gicv3: Fix GICD_TYPER ITLinesNumber advertisement
>
> Mihai Carabas (1):
> hw/arm/virt: build SMBIOS 19 table
>
> Peter Maydell (15):
> target/arm: Allow relevant HCR bits to be written for FEAT_EVT
> target/arm: Implement HCR_EL2.TTLBIS traps
> target/arm: Implement HCR_EL2.TTLBOS traps
> target/arm: Implement HCR_EL2.TICAB,TOCU traps
> target/arm: Implement HCR_EL2.TID4 traps
> target/arm: Report FEAT_EVT for TCG '-cpu max'
> hw/arm: Convert TYPE_ARM_SMMU to 3-phase reset
> hw/arm: Convert TYPE_ARM_SMMUV3 to 3-phase reset
> hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset
> hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset
> hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset
> hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset
> hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset
> hw/intc: Convert TYPE_ARM_GICV3_ITS to 3-phase reset
> hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset
>
> Philippe Mathieu-Daudé (1):
> target/arm: Restrict arm_cpu_exec_interrupt() to TCG accelerator
>
> Schspa Shi (1):
> hw/arm/boot: set initrd with #address-cells type in fdt
>
> Thomas Huth (1):
> hw/misc: Move some arm-related files from specific_ss into softmmu_ss
>
> Timofey Kutergin (1):
> target/arm: Add Cortex-A55 CPU
>
> docs/system/arm/emulation.rst | 1 +
> docs/system/arm/virt.rst | 18 +++
> include/hw/arm/smmuv3.h | 2 +-
> include/hw/arm/virt.h | 2 +
> include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 2 +-
> target/arm/cpu.h | 30 +++++
> target/arm/kvm-consts.h | 8 +-
> hw/arm/boot.c | 10 +-
> hw/arm/smmu-common.c | 7 +-
> hw/arm/smmuv3.c | 12 +-
> hw/arm/virt.c | 202 +++++++++++++++++++++++++++------
> hw/intc/arm_gic_common.c | 7 +-
> hw/intc/arm_gic_kvm.c | 14 ++-
> hw/intc/arm_gicv3_common.c | 7 +-
> hw/intc/arm_gicv3_dist.c | 4 +-
> hw/intc/arm_gicv3_its.c | 14 ++-
> hw/intc/arm_gicv3_its_common.c | 7 +-
> hw/intc/arm_gicv3_its_kvm.c | 14 ++-
> hw/intc/arm_gicv3_kvm.c | 14 ++-
> hw/misc/imx6_src.c | 2 +-
> hw/misc/iotkit-sysctl.c | 1 -
> target/arm/cpu.c | 5 +-
> target/arm/cpu64.c | 70 ++++++++++++
> target/arm/cpu_tcg.c | 1 +
> target/arm/helper.c | 135 ++++++++++++++--------
> hw/misc/meson.build | 11 +-
> 26 files changed, 459 insertions(+), 141 deletions(-)
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PULL v2 00/28] target-arm queue
2022-12-16 11:47 ` Alex Bennée
@ 2022-12-16 11:54 ` Peter Maydell
0 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2022-12-16 11:54 UTC (permalink / raw)
To: Alex Bennée; +Cc: qemu-devel
On Fri, 16 Dec 2022 at 11:49, Alex Bennée <alex.bennee@linaro.org> wrote:
>
>
> Peter Maydell <peter.maydell@linaro.org> writes:
>
> > drop the sysregs patch as the tcg sysregs test fails
> > (probably a bug in the test)
>
> Well I assume because it complains about extra bits leaking into
> userspace:
>
> ➜ ./qemu-aarch64 ./tests/tcg/aarch64-linux-user/sysregs
> Checking Counter registers
> ctr_el0 : 0x0000000080038003
> cntvct_el0 : 0x017314376c668b73
> cntfrq_el0 : 0x0000000003b9aca0
> Checking CPUID registers
> id_aa64isar0_el1 : 0x1021111110212120
> !!extra bits!! : 0x1000000000000000
> id_aa64isar1_el1 : 0x0011101101211012
> !!extra bits!! : 0x0011100100000000
> id_aa64mmfr0_el1 : 0xffffffffff000000
> !!extra bits!! : 0xffffffff00000000
> id_aa64pfr0_el1 : 0x0001000100110011
> id_aa64pfr1_el1 : 0x0000000001000321
> !!extra bits!! : 0x0000000001000301
> id_aa64dfr0_el1 : 0x0000000000000006
> id_aa64zfr0_el1 : 0x0110110100110021 (not RAZ!)
> midr_el1 : 0x00000000000f0510
> mpidr_el1 : 0x0000000080000000
> Remaining registers should fail
> id_mmfr0_el1 : 0x00000000deadbeef
> id_mmfr1_el1 : 0x00000000deadbeef
> id_mmfr2_el1 : 0x00000000deadbeef
> id_mmfr3_el1 : 0x00000000deadbeef
> mvfr0_el1 : 0x00000000deadbeef
> mvfr1_el1 : 0x00000000deadbeef
> Extra information leaked to user-space!
>
> So it should have been updated when the API was changed.
Yes, exactly (or written in a way that supports "in future
we might expose more fields").
thanks
-- PMM
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2024-10-15 14:18 [PULL v2 00/28] target-arm queue Peter Maydell
2024-10-15 16:30 ` Peter Maydell
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2022-12-15 17:40 Peter Maydell
2022-12-15 21:39 ` Peter Maydell
2022-12-16 11:47 ` Alex Bennée
2022-12-16 11:54 ` Peter Maydell
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