From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [PULL 21/33] target/mips: Convert mips16e decr_and_load/store() macros to functions
Date: Tue, 15 Oct 2024 12:44:30 -0300 [thread overview]
Message-ID: <20241015154443.71763-22-philmd@linaro.org> (raw)
In-Reply-To: <20241015154443.71763-1-philmd@linaro.org>
Functions are easier to rework than macros. Besides,
there is no gain here in inlining these.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241010215015.44326-6-philmd@linaro.org>
---
target/mips/tcg/mips16e_translate.c.inc | 101 +++++++++++++-----------
1 file changed, 53 insertions(+), 48 deletions(-)
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index 5cffe0e412d..cabc17345f4 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -122,11 +122,23 @@ enum {
static int xlat(int r)
{
- static int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
+ static const int map[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
return map[r];
}
+static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0)
+{
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ tcg_gen_movi_tl(t2, -4);
+ gen_op_addr_add(ctx, t0, t0, t2);
+ gen_load_gpr(t1, regidx);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
+}
+
static void gen_mips16_save(DisasContext *ctx,
int xsregs, int aregs,
int do_ra, int do_s0, int do_s1,
@@ -196,46 +208,38 @@ static void gen_mips16_save(DisasContext *ctx,
gen_load_gpr(t0, 29);
-#define DECR_AND_STORE(reg) do { \
- tcg_gen_movi_tl(t2, -4); \
- gen_op_addr_add(ctx, t0, t0, t2); \
- gen_load_gpr(t1, reg); \
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | \
- ctx->default_tcg_memop_mask); \
- } while (0)
-
if (do_ra) {
- DECR_AND_STORE(31);
+ decr_and_store(ctx, 31, t0);
}
switch (xsregs) {
case 7:
- DECR_AND_STORE(30);
+ decr_and_store(ctx, 30, t0);
/* Fall through */
case 6:
- DECR_AND_STORE(23);
+ decr_and_store(ctx, 23, t0);
/* Fall through */
case 5:
- DECR_AND_STORE(22);
+ decr_and_store(ctx, 22, t0);
/* Fall through */
case 4:
- DECR_AND_STORE(21);
+ decr_and_store(ctx, 21, t0);
/* Fall through */
case 3:
- DECR_AND_STORE(20);
+ decr_and_store(ctx, 20, t0);
/* Fall through */
case 2:
- DECR_AND_STORE(19);
+ decr_and_store(ctx, 19, t0);
/* Fall through */
case 1:
- DECR_AND_STORE(18);
+ decr_and_store(ctx, 18, t0);
}
if (do_s1) {
- DECR_AND_STORE(17);
+ decr_and_store(ctx, 17, t0);
}
if (do_s0) {
- DECR_AND_STORE(16);
+ decr_and_store(ctx, 16, t0);
}
switch (aregs) {
@@ -270,23 +274,34 @@ static void gen_mips16_save(DisasContext *ctx,
}
if (astatic > 0) {
- DECR_AND_STORE(7);
+ decr_and_store(ctx, 7, t0);
if (astatic > 1) {
- DECR_AND_STORE(6);
+ decr_and_store(ctx, 6, t0);
if (astatic > 2) {
- DECR_AND_STORE(5);
+ decr_and_store(ctx, 5, t0);
if (astatic > 3) {
- DECR_AND_STORE(4);
+ decr_and_store(ctx, 4, t0);
}
}
}
}
-#undef DECR_AND_STORE
tcg_gen_movi_tl(t2, -framesize);
gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
}
+static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0)
+{
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+
+ tcg_gen_movi_tl(t2, -4);
+ gen_op_addr_add(ctx, t0, t0, t2);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL |
+ ctx->default_tcg_memop_mask);
+ gen_store_gpr(t1, regidx);
+}
+
static void gen_mips16_restore(DisasContext *ctx,
int xsregs, int aregs,
int do_ra, int do_s0, int do_s1,
@@ -294,52 +309,43 @@ static void gen_mips16_restore(DisasContext *ctx,
{
int astatic;
TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
TCGv t2 = tcg_temp_new();
tcg_gen_movi_tl(t2, framesize);
gen_op_addr_add(ctx, t0, cpu_gpr[29], t2);
-#define DECR_AND_LOAD(reg) do { \
- tcg_gen_movi_tl(t2, -4); \
- gen_op_addr_add(ctx, t0, t0, t2); \
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | \
- ctx->default_tcg_memop_mask); \
- gen_store_gpr(t1, reg); \
- } while (0)
-
if (do_ra) {
- DECR_AND_LOAD(31);
+ decr_and_load(ctx, 31, t0);
}
switch (xsregs) {
case 7:
- DECR_AND_LOAD(30);
+ decr_and_load(ctx, 30, t0);
/* Fall through */
case 6:
- DECR_AND_LOAD(23);
+ decr_and_load(ctx, 23, t0);
/* Fall through */
case 5:
- DECR_AND_LOAD(22);
+ decr_and_load(ctx, 22, t0);
/* Fall through */
case 4:
- DECR_AND_LOAD(21);
+ decr_and_load(ctx, 21, t0);
/* Fall through */
case 3:
- DECR_AND_LOAD(20);
+ decr_and_load(ctx, 20, t0);
/* Fall through */
case 2:
- DECR_AND_LOAD(19);
+ decr_and_load(ctx, 19, t0);
/* Fall through */
case 1:
- DECR_AND_LOAD(18);
+ decr_and_load(ctx, 18, t0);
}
if (do_s1) {
- DECR_AND_LOAD(17);
+ decr_and_load(ctx, 17, t0);
}
if (do_s0) {
- DECR_AND_LOAD(16);
+ decr_and_load(ctx, 16, t0);
}
switch (aregs) {
@@ -374,18 +380,17 @@ static void gen_mips16_restore(DisasContext *ctx,
}
if (astatic > 0) {
- DECR_AND_LOAD(7);
+ decr_and_load(ctx, 7, t0);
if (astatic > 1) {
- DECR_AND_LOAD(6);
+ decr_and_load(ctx, 6, t0);
if (astatic > 2) {
- DECR_AND_LOAD(5);
+ decr_and_load(ctx, 5, t0);
if (astatic > 3) {
- DECR_AND_LOAD(4);
+ decr_and_load(ctx, 4, t0);
}
}
}
}
-#undef DECR_AND_LOAD
tcg_gen_movi_tl(t2, framesize);
gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
--
2.45.2
next prev parent reply other threads:[~2024-10-15 15:47 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-15 15:44 [PULL 00/33] Endianness cleanup patches for 2024-10-15 Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 01/33] qemu/bswap: Undefine CPU_CONVERT() once done Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 02/33] exec/tswap: Massage target_needs_bswap() definition Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 03/33] exec/memop: Remove unused memop_big_endian() helper Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 04/33] target/hexagon: Replace ldtul_p() -> ldl_p() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 05/33] target/alpha: Replace ldtul_p() -> ldq_p() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 06/33] gdbstub/helpers: Introduce ldtul_$endian_p() helpers Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 07/33] target/alpha: Use explicit little-endian LD/ST API Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 08/33] target/hexagon: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 09/33] hw/i386: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 10/33] target/avr: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 11/33] linux-user/i386: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 12/33] target/loongarch: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 13/33] target/tricore: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 14/33] target/tricore: Use tcg_constant_tl() instead of tcg_gen_movi_tl() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 15/33] target/ppc: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 16/33] hw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ry Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 17/33] target/mips: Declare mips_env_is_bigendian() in 'internal.h' Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 18/33] target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 19/33] target/mips: Introduce mo_endian_env() helper Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 20/33] target/mips: Replace MO_TE by mo_endian_env() in get_pte() Philippe Mathieu-Daudé
2024-10-15 15:44 ` Philippe Mathieu-Daudé [this message]
2024-10-15 15:44 ` [PULL 22/33] target/mips: Factor mo_endian_rev() out of MXU code Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 23/33] target/mips: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 24/33] target/mips: Rename unused sysemu argument of OP_LD_ATOMIC() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 25/33] target/mips: Remove unused MEMOP_IDX() macro Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 26/33] target/mips: Introduce mo_endian() helper Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 27/33] target/mips: Replace MO_TE by mo_endian() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 28/33] target/mips: Have gen_addiupc() expand $pc during translation Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 29/33] target/mips: Use gen_op_addr_addi() when possible Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 30/33] target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 31/33] target/mips: Expose MIPSCPU::is_big_endian property Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 32/33] hw/mips/cps: Set the vCPU 'cpu-big-endian' property Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 33/33] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument Philippe Mathieu-Daudé
2024-10-17 11:42 ` [PULL 00/33] Endianness cleanup patches for 2024-10-15 Peter Maydell
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