From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [PULL 29/33] target/mips: Use gen_op_addr_addi() when possible
Date: Tue, 15 Oct 2024 12:44:38 -0300 [thread overview]
Message-ID: <20241015154443.71763-30-philmd@linaro.org> (raw)
In-Reply-To: <20241015154443.71763-1-philmd@linaro.org>
Replace tcg_gen_movi_tl() + gen_op_addr_add() by a single
gen_op_addr_addi() call.
gen_op_addr_addi() calls tcg_gen_addi_tl() which might
optimize if the immediate is zero.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241010215015.44326-13-philmd@linaro.org>
---
target/mips/tcg/translate.h | 1 +
target/mips/tcg/translate.c | 6 ++----
target/mips/tcg/micromips_translate.c.inc | 12 ++++--------
target/mips/tcg/mips16e_translate.c.inc | 15 ++++-----------
target/mips/tcg/nanomips_translate.c.inc | 4 +---
5 files changed, 12 insertions(+), 26 deletions(-)
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 49ff6b8cd80..5d196e69ac4 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -176,6 +176,7 @@ void gen_addiupc(DisasContext *ctx, int rx, int imm,
* Address Computation and Large Constant Instructions
*/
void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
+void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, target_long ofs);
bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 0ccf32d185e..53a0cbf92be 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1456,8 +1456,7 @@ void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
#endif
}
-static inline void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base,
- target_long ofs)
+void gen_op_addr_addi(DisasContext *ctx, TCGv ret, TCGv base, target_long ofs)
{
tcg_gen_addi_tl(ret, base, ofs);
@@ -11265,10 +11264,9 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
} else {
/* OPC_JIC, OPC_JIALC */
TCGv tbase = tcg_temp_new();
- TCGv toffset = tcg_constant_tl(offset);
gen_load_gpr(tbase, rt);
- gen_op_addr_add(ctx, btarget, tbase, toffset);
+ gen_op_addr_addi(ctx, btarget, tbase, offset);
}
break;
default:
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 171508f7deb..3cbf53bf2b3 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -980,8 +980,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
- tcg_gen_movi_tl(t1, 4);
- gen_op_addr_add(ctx, t0, t0, t1);
+ gen_op_addr_addi(ctx, t0, t0, 4);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
@@ -990,8 +989,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
- tcg_gen_movi_tl(t1, 4);
- gen_op_addr_add(ctx, t0, t0, t1);
+ gen_op_addr_addi(ctx, t0, t0, 4);
gen_load_gpr(t1, rd + 1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
@@ -1005,8 +1003,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
- tcg_gen_movi_tl(t1, 8);
- gen_op_addr_add(ctx, t0, t0, t1);
+ gen_op_addr_addi(ctx, t0, t0, 8);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
@@ -1015,8 +1012,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
- tcg_gen_movi_tl(t1, 8);
- gen_op_addr_add(ctx, t0, t0, t1);
+ gen_op_addr_addi(ctx, t0, t0, 8);
gen_load_gpr(t1, rd + 1);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ |
ctx->default_tcg_memop_mask);
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index ef7a0ec0d38..a9af8f1e74a 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -130,10 +130,8 @@ static int xlat(int r)
static void decr_and_store(DisasContext *ctx, unsigned regidx, TCGv t0)
{
TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
- tcg_gen_movi_tl(t2, -4);
- gen_op_addr_add(ctx, t0, t0, t2);
+ gen_op_addr_addi(ctx, t0, t0, -4);
gen_load_gpr(t1, regidx);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL |
ctx->default_tcg_memop_mask);
@@ -146,7 +144,6 @@ static void gen_mips16_save(DisasContext *ctx,
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
int args, astatic;
switch (aregs) {
@@ -286,8 +283,7 @@ static void gen_mips16_save(DisasContext *ctx,
}
}
- tcg_gen_movi_tl(t2, -framesize);
- gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
+ gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], -framesize);
}
static void decr_and_load(DisasContext *ctx, unsigned regidx, TCGv t0)
@@ -309,10 +305,8 @@ static void gen_mips16_restore(DisasContext *ctx,
{
int astatic;
TCGv t0 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
- tcg_gen_movi_tl(t2, framesize);
- gen_op_addr_add(ctx, t0, cpu_gpr[29], t2);
+ gen_op_addr_addi(ctx, t0, cpu_gpr[29], -framesize);
if (do_ra) {
decr_and_load(ctx, 31, t0);
@@ -392,8 +386,7 @@ static void gen_mips16_restore(DisasContext *ctx,
}
}
- tcg_gen_movi_tl(t2, framesize);
- gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2);
+ gen_op_addr_addi(ctx, cpu_gpr[29], cpu_gpr[29], -framesize);
}
#if defined(TARGET_MIPS64)
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index d462173348f..8e05a36b545 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -2470,11 +2470,9 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
} else {
/* OPC_JIC, OPC_JIALC */
TCGv tbase = tcg_temp_new();
- TCGv toffset = tcg_temp_new();
gen_load_gpr(tbase, rt);
- tcg_gen_movi_tl(toffset, offset);
- gen_op_addr_add(ctx, btarget, tbase, toffset);
+ gen_op_addr_addi(ctx, btarget, tbase, offset);
}
break;
default:
--
2.45.2
next prev parent reply other threads:[~2024-10-15 15:51 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-15 15:44 [PULL 00/33] Endianness cleanup patches for 2024-10-15 Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 01/33] qemu/bswap: Undefine CPU_CONVERT() once done Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 02/33] exec/tswap: Massage target_needs_bswap() definition Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 03/33] exec/memop: Remove unused memop_big_endian() helper Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 04/33] target/hexagon: Replace ldtul_p() -> ldl_p() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 05/33] target/alpha: Replace ldtul_p() -> ldq_p() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 06/33] gdbstub/helpers: Introduce ldtul_$endian_p() helpers Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 07/33] target/alpha: Use explicit little-endian LD/ST API Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 08/33] target/hexagon: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 09/33] hw/i386: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 10/33] target/avr: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 11/33] linux-user/i386: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 12/33] target/loongarch: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 13/33] target/tricore: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 14/33] target/tricore: Use tcg_constant_tl() instead of tcg_gen_movi_tl() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 15/33] target/ppc: " Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 16/33] hw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ry Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 17/33] target/mips: Declare mips_env_is_bigendian() in 'internal.h' Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 18/33] target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 19/33] target/mips: Introduce mo_endian_env() helper Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 20/33] target/mips: Replace MO_TE by mo_endian_env() in get_pte() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 21/33] target/mips: Convert mips16e decr_and_load/store() macros to functions Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 22/33] target/mips: Factor mo_endian_rev() out of MXU code Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 23/33] target/mips: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 24/33] target/mips: Rename unused sysemu argument of OP_LD_ATOMIC() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 25/33] target/mips: Remove unused MEMOP_IDX() macro Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 26/33] target/mips: Introduce mo_endian() helper Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 27/33] target/mips: Replace MO_TE by mo_endian() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 28/33] target/mips: Have gen_addiupc() expand $pc during translation Philippe Mathieu-Daudé
2024-10-15 15:44 ` Philippe Mathieu-Daudé [this message]
2024-10-15 15:44 ` [PULL 30/33] target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl() Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 31/33] target/mips: Expose MIPSCPU::is_big_endian property Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 32/33] hw/mips/cps: Set the vCPU 'cpu-big-endian' property Philippe Mathieu-Daudé
2024-10-15 15:44 ` [PULL 33/33] hw/mips: Have mips_cpu_create_with_clock() take an endianness argument Philippe Mathieu-Daudé
2024-10-17 11:42 ` [PULL 00/33] Endianness cleanup patches for 2024-10-15 Peter Maydell
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