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From: Michael Kowal <kowal@linux.ibm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, clg@kaod.org, fbarrat@linux.ibm.com,
	npiggin@gmail.com, milesg@linux.ibm.com, danielhb413@gmail.com,
	david@gibson.dropbear.id.au, harshpb@linux.ibm.com,
	thuth@redhat.com, lvivier@redhat.com, pbonzini@redhat.com
Subject: [PATCH 01/14] ppc/xive2: Update NVP save/restore for group attributes
Date: Tue, 15 Oct 2024 16:13:16 -0500	[thread overview]
Message-ID: <20241015211329.21113-2-kowal@linux.ibm.com> (raw)
In-Reply-To: <20241015211329.21113-1-kowal@linux.ibm.com>

From: Frederic Barrat <fbarrat@linux.ibm.com>

If the 'H' attribute is set on the NVP structure, the hardware
automatically saves and restores some attributes from the TIMA in the
NVP structure.
The group-specific attributes LSMFB, LGS and T have an extra flag to
individually control what is saved/restored.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
---
 include/hw/ppc/xive2_regs.h |  5 +++++
 hw/intc/xive2.c             | 18 ++++++++++++++++--
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
index 1d00c8df64..30868e8e09 100644
--- a/include/hw/ppc/xive2_regs.h
+++ b/include/hw/ppc/xive2_regs.h
@@ -152,6 +152,9 @@ typedef struct Xive2Nvp {
         uint32_t       w0;
 #define NVP2_W0_VALID              PPC_BIT32(0)
 #define NVP2_W0_HW                 PPC_BIT32(7)
+#define NVP2_W0_L                  PPC_BIT32(8)
+#define NVP2_W0_G                  PPC_BIT32(9)
+#define NVP2_W0_T                  PPC_BIT32(10)
 #define NVP2_W0_ESC_END            PPC_BIT32(25) /* 'N' bit 0:ESB  1:END */
 #define NVP2_W0_PGOFIRST           PPC_BITMASK32(26, 31)
         uint32_t       w1;
@@ -163,6 +166,8 @@ typedef struct Xive2Nvp {
 #define NVP2_W2_CPPR               PPC_BITMASK32(0, 7)
 #define NVP2_W2_IPB                PPC_BITMASK32(8, 15)
 #define NVP2_W2_LSMFB              PPC_BITMASK32(16, 23)
+#define NVP2_W2_T                  PPC_BIT32(27)
+#define NVP2_W2_LGS                PPC_BITMASK32(28, 31)
         uint32_t       w3;
         uint32_t       w4;
 #define NVP2_W4_ESC_ESB_BLOCK      PPC_BITMASK32(0, 3)  /* N:0 */
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index d1df35e9b3..4adc3b6950 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -313,7 +313,19 @@ static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
 
     nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]);
     nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]);
-    nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]);
+    if (nvp.w0 & NVP2_W0_L) {
+        /*
+         * Typically not used. If LSMFB is restored with 0, it will
+         * force a backlog rescan
+         */
+        nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]);
+    }
+    if (nvp.w0 & NVP2_W0_G) {
+        nvp.w2 = xive_set_field32(NVP2_W2_LGS, nvp.w2, regs[TM_LGS]);
+    }
+    if (nvp.w0 & NVP2_W0_T) {
+        nvp.w2 = xive_set_field32(NVP2_W2_T, nvp.w2, regs[TM_T]);
+    }
     xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
 
     nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0);
@@ -527,7 +539,9 @@ static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
     xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2);
 
     tctx->regs[TM_QW1_OS + TM_CPPR] = cppr;
-    /* we don't model LSMFB */
+    tctx->regs[TM_QW1_OS + TM_LSMFB] = xive_get_field32(NVP2_W2_LSMFB, nvp->w2);
+    tctx->regs[TM_QW1_OS + TM_LGS] = xive_get_field32(NVP2_W2_LGS, nvp->w2);
+    tctx->regs[TM_QW1_OS + TM_T] = xive_get_field32(NVP2_W2_T, nvp->w2);
 
     nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1);
     nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1);
-- 
2.43.0



  reply	other threads:[~2024-10-15 21:14 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-15 21:13 [PATCH 00/14] XIVE2 changes to support Group and Crowd operations Michael Kowal
2024-10-15 21:13 ` Michael Kowal [this message]
2024-10-15 21:13 ` [PATCH 02/14] ppc/xive2: Add grouping level to notification Michael Kowal
2024-11-19  2:08   ` Nicholas Piggin
2024-11-21 22:31     ` Mike Kowal
2024-10-15 21:13 ` [PATCH 03/14] ppc/xive2: Support group-matching when looking for target Michael Kowal
2024-11-19  3:22   ` Nicholas Piggin
2024-11-21 22:56     ` Mike Kowal
2024-12-02 22:08       ` Mike Kowal
2024-10-15 21:13 ` [PATCH 04/14] ppc/xive2: Add undelivered group interrupt to backlog Michael Kowal
2024-10-15 21:13 ` [PATCH 05/14] ppc/xive2: Process group backlog when pushing an OS context Michael Kowal
2024-11-19  4:20   ` Nicholas Piggin
2024-10-15 21:13 ` [PATCH 06/14] ppc/xive2: Process group backlog when updating the CPPR Michael Kowal
2024-11-19  4:34   ` Nicholas Piggin
2024-11-21 23:12     ` Mike Kowal
2024-10-15 21:13 ` [PATCH 07/14] qtest/xive: Add group-interrupt test Michael Kowal
2024-10-15 21:13 ` [PATCH 08/14] Add support for MMIO operations on the NVPG/NVC BAR Michael Kowal
2024-10-15 21:13 ` [PATCH 09/14] ppc/xive2: Support crowd-matching when looking for target Michael Kowal
2024-10-15 21:13 ` [PATCH 10/14] ppc/xive2: Check crowd backlog when scanning group backlog Michael Kowal
2024-10-15 21:13 ` [PATCH 11/14] pnv/xive: Only support crowd size of 0, 2, 4 and 16 Michael Kowal
2024-11-19  2:31   ` Nicholas Piggin
2024-10-15 21:13 ` [PATCH 12/14] pnv/xive: Support ESB Escalation Michael Kowal
2024-11-19  5:00   ` Nicholas Piggin
2024-11-21 23:22     ` Mike Kowal
2024-10-15 21:13 ` [PATCH 13/14] pnv/xive: Fix problem with treating NVGC as a NVP Michael Kowal
2024-11-19  5:04   ` Nicholas Piggin
2024-10-15 21:13 ` [PATCH 14/14] qtest/xive: Add test of pool interrupts Michael Kowal
2024-10-16  8:33   ` Thomas Huth
2024-10-16 15:41     ` Mike Kowal

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