From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
zhiwei_liu@linux.alibaba.com,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: [PATCH v6 10/14] tcg/riscv: Implement vector sat/mul ops
Date: Wed, 16 Oct 2024 12:31:36 -0700 [thread overview]
Message-ID: <20241016193140.2206352-11-richard.henderson@linaro.org> (raw)
In-Reply-To: <20241016193140.2206352-1-richard.henderson@linaro.org>
From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20241007025700.47259-9-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.h | 4 ++--
tcg/riscv/tcg-target.c.inc | 41 ++++++++++++++++++++++++++++++++++++++
2 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index ae10381e02..1d4d8878ce 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -160,8 +160,8 @@ typedef enum {
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
-#define TCG_TARGET_HAS_mul_vec 0
-#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_mul_vec 1
+#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 1
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 1ce2f291d3..4758555565 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -284,6 +284,16 @@ typedef enum {
OPC_VXOR_VV = 0x2c000057 | V_OPIVV,
OPC_VXOR_VI = 0x2c000057 | V_OPIVI,
+ OPC_VMUL_VV = 0x94000057 | V_OPMVV,
+ OPC_VSADD_VV = 0x84000057 | V_OPIVV,
+ OPC_VSADD_VI = 0x84000057 | V_OPIVI,
+ OPC_VSSUB_VV = 0x8c000057 | V_OPIVV,
+ OPC_VSSUB_VI = 0x8c000057 | V_OPIVI,
+ OPC_VSADDU_VV = 0x80000057 | V_OPIVV,
+ OPC_VSADDU_VI = 0x80000057 | V_OPIVI,
+ OPC_VSSUBU_VV = 0x88000057 | V_OPIVV,
+ OPC_VSSUBU_VI = 0x88000057 | V_OPIVI,
+
OPC_VMSEQ_VV = 0x60000057 | V_OPIVV,
OPC_VMSEQ_VI = 0x60000057 | V_OPIVI,
OPC_VMSEQ_VX = 0x60000057 | V_OPIVX,
@@ -2376,6 +2386,26 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
set_vtype_len_sew(s, type, vece);
tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a1, 0);
break;
+ case INDEX_op_mul_vec:
+ set_vtype_len_sew(s, type, vece);
+ tcg_out_opc_vv(s, OPC_VMUL_VV, a0, a1, a2);
+ break;
+ case INDEX_op_ssadd_vec:
+ set_vtype_len_sew(s, type, vece);
+ tcg_out_opc_vv_vi(s, OPC_VSADD_VV, OPC_VSADD_VI, a0, a1, a2, c2);
+ break;
+ case INDEX_op_sssub_vec:
+ set_vtype_len_sew(s, type, vece);
+ tcg_out_opc_vv_vi(s, OPC_VSSUB_VV, OPC_VSSUB_VI, a0, a1, a2, c2);
+ break;
+ case INDEX_op_usadd_vec:
+ set_vtype_len_sew(s, type, vece);
+ tcg_out_opc_vv_vi(s, OPC_VSADDU_VV, OPC_VSADDU_VI, a0, a1, a2, c2);
+ break;
+ case INDEX_op_ussub_vec:
+ set_vtype_len_sew(s, type, vece);
+ tcg_out_opc_vv_vi(s, OPC_VSSUBU_VV, OPC_VSSUBU_VI, a0, a1, a2, c2);
+ break;
case INDEX_op_cmp_vec:
tcg_out_cmpsel(s, type, vece, args[3], a0, a1, a2, c2,
-1, true, 0, true);
@@ -2407,6 +2437,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_xor_vec:
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
+ case INDEX_op_mul_vec:
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_ussub_vec:
case INDEX_op_cmp_vec:
case INDEX_op_cmpsel_vec:
return 1;
@@ -2567,9 +2602,15 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_and_vec:
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_ussub_vec:
return C_O1_I2(v, v, vK);
case INDEX_op_sub_vec:
return C_O1_I2(v, vK, v);
+ case INDEX_op_mul_vec:
+ return C_O1_I2(v, v, v);
case INDEX_op_cmp_vec:
return C_O1_I2(v, v, vL);
case INDEX_op_cmpsel_vec:
--
2.43.0
next prev parent reply other threads:[~2024-10-16 19:34 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-16 19:31 [PATCH v6 00/14] tcg/riscv: Add support for vector Richard Henderson
2024-10-16 19:31 ` [PATCH v6 01/14] tcg: Reset data_gen_ptr correctly Richard Henderson
2024-10-21 1:16 ` Alistair Francis
2024-10-21 17:31 ` Pierrick Bouvier
2024-10-22 2:48 ` LIU Zhiwei
2024-10-16 19:31 ` [PATCH v6 02/14] disas/riscv: Fix vsetivli disassembly Richard Henderson
2024-10-21 1:17 ` Alistair Francis
2024-10-21 17:41 ` Pierrick Bouvier
2024-10-22 3:12 ` LIU Zhiwei
2024-10-16 19:31 ` [PATCH v6 03/14] util: Add RISC-V vector extension probe in cpuinfo Richard Henderson
2024-10-21 1:20 ` Alistair Francis
2024-10-21 18:25 ` Daniel Henrique Barboza
2024-10-21 18:52 ` Richard Henderson
2024-10-21 19:16 ` Daniel Henrique Barboza
2024-10-16 19:31 ` [PATCH v6 04/14] tcg/riscv: Add basic support for vector Richard Henderson
2024-10-16 19:31 ` [PATCH v6 05/14] tcg/riscv: Implement vector mov/dup{m/i} Richard Henderson
2024-10-16 19:31 ` [PATCH v6 06/14] tcg/riscv: Add support for basic vector opcodes Richard Henderson
2024-10-16 19:31 ` [PATCH v6 07/14] tcg/riscv: Implement vector cmp/cmpsel ops Richard Henderson
2024-10-16 19:31 ` [PATCH v6 08/14] tcg/riscv: Implement vector neg ops Richard Henderson
2024-10-16 19:31 ` [PATCH v6 09/14] tcg/riscv: Accept constant first argument to sub_vec Richard Henderson
2024-10-22 6:31 ` LIU Zhiwei
2024-10-16 19:31 ` Richard Henderson [this message]
2024-10-16 19:31 ` [PATCH v6 11/14] tcg/riscv: Implement vector min/max ops Richard Henderson
2024-10-16 19:31 ` [PATCH v6 12/14] tcg/riscv: Implement vector shi/s/v ops Richard Henderson
2024-10-16 19:31 ` [PATCH v6 13/14] tcg/riscv: Implement vector roti/v/x ops Richard Henderson
2024-10-16 19:31 ` [PATCH v6 14/14] tcg/riscv: Enable native vector support for TCG host Richard Henderson
2024-10-21 1:42 ` [PATCH v6 00/14] tcg/riscv: Add support for vector Alistair Francis
2024-10-22 6:59 ` LIU Zhiwei
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