From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23AA8D37485 for ; Thu, 17 Oct 2024 13:20:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t1QPd-00048L-L8; Thu, 17 Oct 2024 09:19:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t1QPc-00047h-Hq; Thu, 17 Oct 2024 09:19:32 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t1QPY-0003PA-To; Thu, 17 Oct 2024 09:19:32 -0400 Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4XTpLt2DRqz6JBTK; Thu, 17 Oct 2024 21:18:46 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 99CE81400DB; Thu, 17 Oct 2024 21:19:26 +0800 (CST) Received: from localhost (10.126.174.164) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Thu, 17 Oct 2024 15:19:25 +0200 Date: Thu, 17 Oct 2024 14:19:23 +0100 To: Zhao Liu CC: "Daniel P =?ISO-8859-1?Q?Berrang=E9?=" , "Igor Mammedov" , Eduardo Habkost , Marcel Apfelbaum , Philippe =?ISO-8859-1?Q?Ma?= =?ISO-8859-1?Q?thieu-Daud=E9?= , Yanan Wang , "Michael S.Tsirkin " , "Paolo Bonzini" , Richard Henderson , Eric Blake , "Markus Armbruster" , Marcelo Tosatti , Alex =?ISO-8859-1?Q?Benn=E9e?= , Peter Maydell , Sia Jee Heng , Alireza Sanaee , , , , , "Zhenyu Wang" , Dapeng Mi Subject: Re: [PATCH v3 0/7] Introduce SMP Cache Topology Message-ID: <20241017141923.00007f64@Huawei.com> In-Reply-To: <20241012104429.1048908-1-zhao1.liu@intel.com> References: <20241012104429.1048908-1-zhao1.liu@intel.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.126.174.164] X-ClientProxiedBy: lhrpeml500002.china.huawei.com (7.191.160.78) To frapeml500008.china.huawei.com (7.182.85.71) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org RESEND (again, sorry) as didn't reach list. Issue some stray " in various email addresses. On Sat, 12 Oct 2024 18:44:22 +0800 Zhao Liu wrote: > Hi all, >=20 > Compared with v2 [1], the changes in v3 are quite minor, and most of > patches (except for patch 1 and 7) have received Jonathan=E2=80=99s R/b (= thanks > Jonathan!). >=20 > Meanwhile, ARM side has also worked a lot on the smp-cache based on > this series [2], so I think we are very close to the final merge, to > catch up with this cycle. :) This would finally solve a long standing missing control for our virtualization usecases (TCG and MPAM stuff is an added bonus), so I'm very keen in this making 9.2 (and maybe even the ARM part of things happen to move fast enough). Ali is out this week, but should be back sometime next week. Looks like rebase of his ARM patches on this should be simple! I think this set mostly needs a QAPI review (perhaps from Markus?) >=20 > This series is based on the commit 7e3b6d8063f2 ("Merge tag 'crypto- > fixes-pull-request' of https://gitlab.com/berrange/qemu into staging"). >=20 > Background > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >=20 > The x86 and ARM (RISCV) need to allow user to configure cache properties *laughs*. I definitely going to start emailing ARM folk with ARM (RISCV) =20 :) =20 > (current only topology): > * For x86, the default cache topology model (of max/host CPU) does not > always match the Host's real physical cache topology. Performance can > increase when the configured virtual topology is closer to the > physical topology than a default topology would be. > * For ARM, QEMU can't get the cache topology information from the CPU > registers, then user configuration is necessary. Additionally, the > cache information is also needed for MPAM emulation (for TCG) to > build the right PPTT. (Originally from Jonathan)