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Fri, 18 Oct 2024 13:00:15 +0000 (GMT) Date: Fri, 18 Oct 2024 18:30:10 +0530 From: Amit Machhiwal To: Harsh Prateek Bora Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Vaibhav Jain , David Gibson , Daniel Henrique Barboza , qemu-devel@nongnu.org Subject: Re: [PATCH] spapr: nested: Add support for DPDES SPR in GSB for TCG L0 Message-ID: <20241018142059.c417f28d-c2-amachhiw@linux.ibm.com> Mail-Followup-To: Harsh Prateek Bora , Nicholas Piggin , qemu-ppc@nongnu.org, Vaibhav Jain , David Gibson , Daniel Henrique Barboza , qemu-devel@nongnu.org References: <20241017110033.3929988-1-amachhiw@linux.ibm.com> <07af4e02-aa2a-494c-9279-cd70389fc97e@linux.ibm.com> <952fc526-03a5-4965-9bba-f3aa30147370@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <952fc526-03a5-4965-9bba-f3aa30147370@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 6qTGRSU7U3BRWQIkSe5K-i0k1cEib8aj X-Proofpoint-ORIG-GUID: yWsfPFL81KPbl_JuhQUFQZF1T5vGCull X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1051,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-10-15_01,2024-10-11_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=outbound_spam_definite policy=outbound score=100 priorityscore=1501 suspectscore=0 lowpriorityscore=0 impostorscore=0 mlxlogscore=-999 malwarescore=0 bulkscore=0 adultscore=0 spamscore=100 phishscore=0 clxscore=1015 mlxscore=100 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410180080 Received-SPF: pass client-ip=148.163.156.1; envelope-from=amachhiw@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Harsh, Thanks for looking into this patch. My comments are below: On 2024/10/18 02:13 PM, Harsh Prateek Bora wrote: > Hi Amit, > > On 10/18/24 10:47, Harsh Prateek Bora wrote: > > Hi Amit, > > > > On 10/17/24 16:30, Amit Machhiwal wrote: > > > The DPDES support for doorbell emulation and handling for KVM on PAPR > > > guests was added in Linux via [1]. Subsequently, a new GSB element for > > > DPDES was added in Linux; the same has been missing in QEMU L0. Add > > > > s/QEMU L0/ TCG L0 implementation? > > > > > support for DPDES register's APIv2 GSB element and required handling in > > > `spapr_nested.c`. > > > > > > Currently, booting a KVM guest inside a QEMU TCG guest fails with the > > > below crash. The crash is encountered when GUEST_RUN_VCPU hcall made > > > into QEMU TCG L0 fails because H_INVALID_ELEMENT_VALUE is returned as > > > the mapping of the element ID corresponding to DPDES (unknown to QEMU > > > TCG L0) in GSR (Guest State Request) of TCG guest's KVM to the GSB > > > (Guest State Buffer) elements of QEMU TCG L0 fails. > > > > GSB full form would be more appropriate along with first mention of GSB > > in above text. > > > > With that: > > Reviewed-by: Harsh Prateek Bora > > > > > > > > > > > diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c > > > index c02785756c1e..b696ad537a77 100644 > > > --- a/hw/ppc/spapr_nested.c > > > +++ b/hw/ppc/spapr_nested.c > > > @@ -194,6 +194,7 @@ static void nested_save_state(struct > > > nested_ppc_state *save, PowerPCCPU *cpu) > > >           save->fscr = env->spr[SPR_FSCR]; > > >           save->pspb = env->spr[SPR_PSPB]; > > >           save->ctrl = env->spr[SPR_CTRL]; > > > +        save->dpdes = env->spr[SPR_DPDES]; > > >           save->vrsave = env->spr[SPR_VRSAVE]; > > >           save->dar = env->spr[SPR_DAR]; > > >           save->dsisr = env->spr[SPR_DSISR]; > > > @@ -293,6 +294,7 @@ static void nested_load_state(PowerPCCPU *cpu, > > > struct nested_ppc_state *load) > > >           env->spr[SPR_FSCR] = load->fscr; > > >           env->spr[SPR_PSPB] = load->pspb; > > >           env->spr[SPR_CTRL] = load->ctrl; > > > +        env->spr[SPR_DPDES] = load->dpdes; > > >           env->spr[SPR_VRSAVE] = load->vrsave; > > >           env->spr[SPR_DAR] = load->dar; > > >           env->spr[SPR_DSISR] = load->dsisr; > > Looks like we overlooked above inits already present in existing code. > I just checked above inits in nested_{save,load}_state are already > present as common code between apiv1 & apiv2. So, we only need the inits > below for initializing the lookup table. The common code already has that handled, indeed. I'll make this change and the ones you posted in the other response and send out a V2. Thanks for pointing this out. Thanks, Amit > > regards, > Harsh > > > @@ -982,6 +984,7 @@ struct guest_state_element_type > > > guest_state_element_types[] = { > > >       GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_FSCR,  fscr), > > >       GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_PSPB,   pspb), > > >       GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_CTRL,  ctrl), > > > +    GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DPDES, dpdes), > > >       GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_VRSAVE, vrsave), > > >       GUEST_STATE_ELEMENT_ENV_DW(GSB_VCPU_SPR_DAR,   dar), > > >       GUEST_STATE_ELEMENT_ENV_W(GSB_VCPU_SPR_DSISR,  dsisr), > > > diff --git a/include/hw/ppc/spapr_nested.h > > > b/include/hw/ppc/spapr_nested.h > > > index 93ef14adcc5e..3b5cd993c256 100644 > > > --- a/include/hw/ppc/spapr_nested.h > > > +++ b/include/hw/ppc/spapr_nested.h > > > @@ -99,7 +99,8 @@ > > >   #define GSB_VCPU_SPR_HASHKEYR   0x1050 > > >   #define GSB_VCPU_SPR_HASHPKEYR  0x1051 > > >   #define GSB_VCPU_SPR_CTRL       0x1052 > > > -                    /* RESERVED 0x1053 - 0x1FFF */ > > > +#define GSB_VCPU_SPR_DPDES      0x1053 > > > +                    /* RESERVED 0x1054 - 0x1FFF */ > > >   #define GSB_VCPU_SPR_CR         0x2000 > > >   #define GSB_VCPU_SPR_PIDR       0x2001 > > >   #define GSB_VCPU_SPR_DSISR      0x2002 > > > > > > base-commit: aa54f5be44be786636a5d51cc1612ad208a24849 > >