From: Jim Shu <jim.shu@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Jim Shu <jim.shu@sifive.com>
Subject: [PATCH 0/2] Support 64-bit address of initrd
Date: Mon, 21 Oct 2024 12:09:40 +0800 [thread overview]
Message-ID: <20241021040942.400-1-jim.shu@sifive.com> (raw)
Support to load DTB after 3GB on RV64 system, so that larger initrd
doesn't be overlapped to DTB. Update initrd DT to support different
"#address-cells".
Verify the patch via running 4GB initramfs on the virt machine.
Jim Shu (2):
hw/riscv: Support to load DTB after 3GB memory on 64-bit system.
hw/riscv: Support different address-cells for initrd
hw/riscv/boot.c | 22 ++++++++++++++++++----
hw/riscv/microchip_pfsoc.c | 4 ++--
hw/riscv/sifive_u.c | 4 ++--
hw/riscv/spike.c | 4 ++--
hw/riscv/virt.c | 2 +-
include/hw/riscv/boot.h | 2 +-
6 files changed, 26 insertions(+), 12 deletions(-)
--
2.17.1
next reply other threads:[~2024-10-21 4:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-21 4:09 Jim Shu [this message]
2024-10-21 4:09 ` [PATCH 1/2] hw/riscv: Support to load DTB after 3GB memory on 64-bit system Jim Shu
2024-10-21 13:41 ` Daniel Henrique Barboza
2024-10-23 10:19 ` Jim Shu
2024-10-24 14:23 ` Daniel Henrique Barboza
2024-10-21 4:09 ` [PATCH 2/2] hw/riscv: Support different address-cells for initrd Jim Shu
2024-10-21 19:30 ` Daniel Henrique Barboza
2024-10-23 10:44 ` Jim Shu
2024-10-24 15:20 ` Conor Dooley
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