From: Jim Shu <jim.shu@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Jim Shu <jim.shu@sifive.com>
Subject: [PATCH 2/2] hw/riscv: Support different address-cells for initrd
Date: Mon, 21 Oct 2024 12:09:42 +0800 [thread overview]
Message-ID: <20241021040942.400-3-jim.shu@sifive.com> (raw)
In-Reply-To: <20241021040942.400-1-jim.shu@sifive.com>
The cells of 'initrd-start/end' should follow the '#address-cell'.
QEMU API could support 1 and 2 cells.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
---
hw/riscv/boot.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index ad45bd7a6a..76b099c696 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -182,6 +182,7 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
void *fdt = machine->fdt;
hwaddr start, end;
ssize_t size;
+ uint32_t acells;
g_assert(filename != NULL);
@@ -209,9 +210,18 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry)
/* Some RISC-V machines (e.g. opentitan) don't have a fdt. */
if (fdt) {
+ acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
+ NULL, NULL);
+ if (acells == 0) {
+ error_report("dtb file invalid (#address-cells 0)");
+ exit(1);
+ }
+
end = start + size;
- qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-start", start);
- qemu_fdt_setprop_u64(fdt, "/chosen", "linux,initrd-end", end);
+ qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start",
+ acells, start);
+ qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end",
+ acells, end);
}
}
--
2.17.1
next prev parent reply other threads:[~2024-10-21 4:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-21 4:09 [PATCH 0/2] Support 64-bit address of initrd Jim Shu
2024-10-21 4:09 ` [PATCH 1/2] hw/riscv: Support to load DTB after 3GB memory on 64-bit system Jim Shu
2024-10-21 13:41 ` Daniel Henrique Barboza
2024-10-23 10:19 ` Jim Shu
2024-10-24 14:23 ` Daniel Henrique Barboza
2024-10-21 4:09 ` Jim Shu [this message]
2024-10-21 19:30 ` [PATCH 2/2] hw/riscv: Support different address-cells for initrd Daniel Henrique Barboza
2024-10-23 10:44 ` Jim Shu
2024-10-24 15:20 ` Conor Dooley
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