From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, dbarboza@ventanamicro.com, alistair23@gmail.com
Subject: [PATCH v7 09/14] tcg/riscv: Accept constant first argument to sub_vec
Date: Mon, 21 Oct 2024 17:11:29 -0700 [thread overview]
Message-ID: <20241022001134.828724-10-richard.henderson@linaro.org> (raw)
In-Reply-To: <20241022001134.828724-1-richard.henderson@linaro.org>
Use vrsub.vi to subtract from a constant.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target-con-set.h | 1 +
tcg/riscv/tcg-target.c.inc | 8 ++++++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
index 97e6ecdb0f..d8ce5414f5 100644
--- a/tcg/riscv/tcg-target-con-set.h
+++ b/tcg/riscv/tcg-target-con-set.h
@@ -25,6 +25,7 @@ C_O0_I2(v, r)
C_O1_I1(v, r)
C_O1_I1(v, v)
C_O1_I2(v, v, v)
+C_O1_I2(v, vK, v)
C_O1_I2(v, v, vK)
C_O1_I2(v, v, vL)
C_O1_I4(v, v, vL, vK, vK)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index ce8d6d0293..1ce2f291d3 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -2350,7 +2350,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_sub_vec:
set_vtype_len_sew(s, type, vece);
- tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2);
+ if (const_args[1]) {
+ tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a2, a1);
+ } else {
+ tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2);
+ }
break;
case INDEX_op_and_vec:
set_vtype_len(s, type);
@@ -2565,7 +2569,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_xor_vec:
return C_O1_I2(v, v, vK);
case INDEX_op_sub_vec:
- return C_O1_I2(v, v, v);
+ return C_O1_I2(v, vK, v);
case INDEX_op_cmp_vec:
return C_O1_I2(v, v, vL);
case INDEX_op_cmpsel_vec:
--
2.43.0
next prev parent reply other threads:[~2024-10-22 0:13 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-22 0:11 [PATCH v7 00/14] tcg/riscv: Add support for vector Richard Henderson
2024-10-22 0:11 ` [PATCH v7 01/14] tcg: Reset data_gen_ptr correctly Richard Henderson
2024-10-22 0:11 ` [PATCH v7 02/14] disas/riscv: Fix vsetivli disassembly Richard Henderson
2024-10-22 0:11 ` [PATCH v7 03/14] util: Add RISC-V vector extension probe in cpuinfo Richard Henderson
2024-10-22 11:34 ` Daniel Henrique Barboza
2024-10-22 0:11 ` [PATCH v7 04/14] tcg/riscv: Add basic support for vector Richard Henderson
2024-10-22 0:11 ` [PATCH v7 05/14] tcg/riscv: Implement vector mov/dup{m/i} Richard Henderson
2024-10-22 0:11 ` [PATCH v7 06/14] tcg/riscv: Add support for basic vector opcodes Richard Henderson
2024-10-22 0:11 ` [PATCH v7 07/14] tcg/riscv: Implement vector cmp/cmpsel ops Richard Henderson
2024-10-22 0:11 ` [PATCH v7 08/14] tcg/riscv: Implement vector neg ops Richard Henderson
2024-10-22 0:11 ` Richard Henderson [this message]
2024-10-23 2:34 ` [PATCH v7 09/14] tcg/riscv: Accept constant first argument to sub_vec Alistair Francis
2024-10-22 0:11 ` [PATCH v7 10/14] tcg/riscv: Implement vector sat/mul ops Richard Henderson
2024-10-22 0:11 ` [PATCH v7 11/14] tcg/riscv: Implement vector min/max ops Richard Henderson
2024-10-22 0:11 ` [PATCH v7 12/14] tcg/riscv: Implement vector shi/s/v ops Richard Henderson
2024-10-22 0:11 ` [PATCH v7 13/14] tcg/riscv: Implement vector roti/v/x ops Richard Henderson
2024-10-22 0:11 ` [PATCH v7 14/14] tcg/riscv: Enable native vector support for TCG host Richard Henderson
2024-10-23 2:41 ` [PATCH v7 00/14] tcg/riscv: Add support for vector Alistair Francis
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