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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37ee0b9cd48sm5971780f8f.111.2024.10.22.00.34.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2024 00:34:50 -0700 (PDT) Date: Tue, 22 Oct 2024 09:34:49 +0200 From: Igor Mammedov To: Marcin Juszkiewicz Cc: "Michael S. Tsirkin" , qemu-devel@nongnu.org, Marcel Apfelbaum Subject: Re: [PATCH] pcie: enable Extended tag field capability Message-ID: <20241022093449.04c007cb@imammedo.users.ipa.redhat.com> In-Reply-To: <560a13ec-3954-45b6-a3b7-85c106b36eaf@linaro.org> References: <20241017-pcie-extend-v1-1-03eb1029f4ca@linaro.org> <20241017125724-mutt-send-email-mst@kernel.org> <560a13ec-3954-45b6-a3b7-85c106b36eaf@linaro.org> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.43; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.421, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-1.699, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, 18 Oct 2024 12:24:05 +0200 Marcin Juszkiewicz wrote: > W dniu 17.10.2024 o=C2=A018:58, Michael S. Tsirkin pisze: > >> diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c > >> index 4b2f0805c6..54c0f1ec67 100644 > >> --- a/hw/pci/pcie.c > >> +++ b/hw/pci/pcie.c > >> @@ -86,7 +86,8 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8= _t type, uint8_t version) > >> * Specification, Revision 1.1., or subsequent PCI Express Base > >> * Specification revisions. > >> */ > >> - pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER); > >> + pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER | > >> + PCI_EXP_DEVCAP_EXT_TAG); > >> =20 > >> pci_set_long(exp_cap + PCI_EXP_LNKCAP, > >> (port << PCI_EXP_LNKCAP_PN_SHIFT) | =20 > >=20 > > We can't change capabilities unconditionally. > > It needs at least a machine type compat thing. =20 >=20 > Started looking and wonder how to pass it from MachineClass level down=20 > to pcie.c/pcie_cap_v1_fill() level. see as an example: fa905f65c5549 hw/nvme: add machine compatibility parameter to enable msix= exclusive bar =20 > hw/arm/sbsa-ref.c (the machine I know best) has create_pcie() which=20 > allocates PCI_HOST_BRIDGE and then creates 2 pcie devices (default_nic=20 > (e1000e) and bochs-display gfx). >=20 > If I add "pcie_uses_ext_tags =3D true" to SBSAMachineState then I need to= =20 > have it stored in PCIBus structure so pci_create_simple() will know.=20 > This function would copy it into "dev" (PCIDevice) to make it pass to=20 > pcie_cap_v1_fill() function. >=20 > But that's not right way because other PCIe devices are created in other= =20 > places. >=20 > Need to dig deeper. >=20