* [PATCH v4 0/9] Introduce SMP Cache Topology
@ 2024-10-22 13:51 Zhao Liu
2024-10-22 13:51 ` [PATCH v4 1/9] i386/cpu: Don't enumerate the "invalid" CPU topology level Zhao Liu
` (9 more replies)
0 siblings, 10 replies; 16+ messages in thread
From: Zhao Liu @ 2024-10-22 13:51 UTC (permalink / raw)
To: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
Michael S . Tsirkin, Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Jonathan Cameron, Sia Jee Heng, Alireza Sanaee
Cc: qemu-devel, kvm, qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi,
Zhao Liu
Hi all,
Compared with v3 [1], the v4 mainly changes these places:
* Don't expose "invalid" enumeration in QAPI and define it by a
macro instead. (new patch 1, and updated patch 2)
* Check cache topology after the arch machine loads the user-
configured cache model from MachineState.smp_cache and consumes
the special "default" level by replacing it with the specific level.
(new patch 5, and updated patch 7)
* Describ the omitting cache will use "default" level and describ
the default cache topology model of i386 PC machine. (updated
patch 8)
All the above changes are tested and the interface design has remained
stable.
Meanwhile, ARM side has also worked a lot on the smp-cache based on
this series [2].
This series is based on the commit cc5adbbd50d8 ("Merge tag
'pull-tpm-2024-10-18-1' of https://github.com/stefanberger/qemu-tpm into
staging").
Welcome your feedback, and I appreciate your reviews. Hope our series
can catch up with the 9.2 cycle. :)
Background
==========
The x86 and ARM (RISCV) need to allow user to configure cache properties
(current only topology):
* For x86, the default cache topology model (of max/host CPU) does not
always match the Host's real physical cache topology. Performance can
increase when the configured virtual topology is closer to the
physical topology than a default topology would be.
* For ARM, QEMU can't get the cache topology information from the CPU
registers, then user configuration is necessary. Additionally, the
cache information is also needed for MPAM emulation (for TCG) to
build the right PPTT. (Originally from Jonathan)
About smp-cache
===============
The API design has been discussed heavily in [3].
Now, smp-cache is implemented as a array integrated in -machine. Though
-machine currently can't support JSON format, this is the one of the
directions of future.
An example is as follows:
smp_cache=smp-cache.0.cache=l1i,smp-cache.0.topology=core,smp-cache.1.cache=l1d,smp-cache.1.topology=core,smp-cache.2.cache=l2,smp-cache.2.topology=module,smp-cache.3.cache=l3,smp-cache.3.topology=die
"cache" specifies the cache that the properties will be applied on. This
field is the combination of cache level and cache type. Now it supports
"l1d" (L1 data cache), "l1i" (L1 instruction cache), "l2" (L2 unified
cache) and "l3" (L3 unified cache).
"topology" field accepts CPU topology levels including "thread", "core",
"module", "cluster", "die", "socket", "book", "drawer" and a special
value "default".
The "default" is introduced to make it easier for libvirt to set a
default parameter value without having to care about the specific
machine (because currently there is no proper way for machine to
expose supported topology levels and caches).
If "default" is set, then the cache topology will follow the
architecture's default cache topology model. If other CPU topology level
is set, the cache will be shared at corresponding CPU topology level.
Welcome your feedback and review!
[1]: Patch v3: https://lore.kernel.org/qemu-devel/20241012104429.1048908-1-zhao1.liu@intel.com/
[2]: ARM smp-cache: https://lore.kernel.org/qemu-devel/20241010111822.345-1-alireza.sanaee@huawei.com/
[3]: API disscussion: https://lore.kernel.org/qemu-devel/8734ndj33j.fsf@pond.sub.org/
Thanks and Best Regards,
Zhao
---
Changelog:
Main changes since Patch v3:
* Stopped exposing "invalid" enumeration in QAPI and define it by a
macro instead. (Dainel)
* Checked cache topology after the arch machine loads the
user-configured cache model from MachineState.smp_cache and consumes
the special "default" level by replacing it with the specific level.
(Daniel)
* Described the omitting cache will use "default" level and described
the default cache topology model of i386 PC machine. (Daniel)
Main changes since Patch v2:
* Updated version of new QAPI structures to v9.2. (Jonathan)
* Merged the QAPI change and smp-cache property support of machine
into one commit. (Jonathan)
* Picked Alireza's patch to add a has_caches flag.
* Polished english and coding style. (Jonathan)
Main changes since Patch v1:
* Dropped handwriten smp-cache object and integrated cache properties
list into MachineState and used -machine to configure SMP cache
properties. (Markus)
* Dropped prefix of CpuTopologyLevel enumeration. (Markus)
* Rename CPU_TOPO_LEVEL_* to CPU_TOPOLOGY_LEVEL_* to match the QAPI's
generated code. (Markus)
* Renamed SMPCacheProperty/SMPCacheProperties (QAPI structures) to
SmpCacheProperties/SmpCachePropertiesWrapper. (Markus)
* Renamed SMPCacheName (QAPI structure) to SmpCacheLevelAndType and
dropped prefix. (Markus)
* Renamed 'name' field in SmpCacheProperties to 'cache', since the
type and level of the cache in SMP system could be able to specify
all of these kinds of cache explicitly enough.
* Renamed 'topo' field in SmpCacheProperties to 'topology'. (Markus)
* Returned error information when user repeats setting cache
properties. (Markus)
* Renamed SmpCacheLevelAndType to CacheLevelAndType, since this
representation is general across SMP or hybrid system.
* Dropped machine_check_smp_cache_support() and did the check when
-machine parses smp-cache in machine_parse_smp_cache().
Main changes since RFC v2:
* Dropped cpu-topology.h and cpu-topology.c since QAPI has the helper
(CpuTopologyLevel_str) to convert enum to string. (Markus)
* Fixed text format in machine.json (CpuTopologyLevel naming, 2 spaces
between sentences). (Markus)
* Added a new level "default" to de-compatibilize some arch-specific
topo settings. (Daniel)
* Moved CpuTopologyLevel to qapi/machine-common.json, at where the
cache enumeration and smp-cache object would be added.
- If smp-cache object is defined in qapi/machine.json, storage-daemon
will complain about the qmp cmds in qapi/machine.json during
compiling.
* Referred to Daniel's suggestion to introduce cache JSON list, though
as a standalone object since -smp/-machine can't support JSON.
* Linked machine's smp_cache to smp-cache object instead of a builtin
structure. This is to get around the fact that the keyval format of
-machine can't support JSON.
* Wrapped the cache topology level access into a helper.
* Split as a separate commit to just include compatibility checking and
topology checking.
* Allow setting "default" topology level even though the cache
isn't supported by machine. (Daniel)
* Rewrote the document of smp-cache object.
Main changes since RFC v1:
* Split CpuTopology renaimg out of this RFC.
* Use QAPI to enumerate CPU topology levels.
* Drop string_to_cpu_topo() since QAPI will help to parse the topo
levels.
* Set has_*_cache field in machine_get_smp(). (JeeHeng)
* Use "*_cache=topo_level" as -smp example as the original "level"
term for a cache has a totally different meaning. (Jonathan)
---
Alireza Sanaee (1):
i386/cpu: add has_caches flag to check smp_cache configuration
Zhao Liu (8):
i386/cpu: Don't enumerate the "invalid" CPU topology level
hw/core: Make CPU topology enumeration arch-agnostic
qapi/qom: Define cache enumeration and properties for machine
hw/core: Check smp cache topology support for machine
hw/core: Add a helper to check the cache topology level
i386/cpu: Support thread and module level cache topology
i386/cpu: Update cache topology with machine's configuration
i386/pc: Support cache topology in -machine for PC machine
hw/core/machine-smp.c | 128 +++++++++++++++++++++
hw/core/machine.c | 44 ++++++++
hw/i386/pc.c | 4 +
hw/i386/x86-common.c | 4 +-
include/hw/boards.h | 19 ++++
include/hw/i386/topology.h | 22 +---
qapi/machine-common.json | 94 +++++++++++++++-
qemu-options.hx | 31 ++++-
target/i386/cpu.c | 225 ++++++++++++++++++++++++-------------
target/i386/cpu.h | 4 +-
10 files changed, 474 insertions(+), 101 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 1/9] i386/cpu: Don't enumerate the "invalid" CPU topology level
2024-10-22 13:51 [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
@ 2024-10-22 13:51 ` Zhao Liu
2024-10-22 14:43 ` Jonathan Cameron via
2024-10-22 13:51 ` [PATCH v4 2/9] hw/core: Make CPU topology enumeration arch-agnostic Zhao Liu
` (8 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Zhao Liu @ 2024-10-22 13:51 UTC (permalink / raw)
To: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
Michael S . Tsirkin, Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Jonathan Cameron, Sia Jee Heng, Alireza Sanaee
Cc: qemu-devel, kvm, qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi,
Zhao Liu
In the follow-up change, the CPU topology enumeration will be moved to
QAPI. And considerring "invalid" should not be exposed to QAPI as an
unsettable item, so, as a preparation for future changes, remove
"invalid" level from the current CPU topology enumeration structure
and define it by a macro instead.
Due to the removal of the enumeration of "invalid", bit 0 of
CPUX86State.avail_cpu_topo bitmap will no longer correspond to "invalid"
level, but will start at the SMT level. Therefore, to honor this change,
update the encoding rule for CPUID[0x1F].
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Tested by the following cases to ensure 0x1f's behavior hasn't
changed:
-smp cpus=24,sockets=2,dies=3,modules=2,cores=2,threads=1
-smp cpus=24,sockets=2,dies=1,modules=3,cores=2,threads=2
-smp cpus=24,sockets=2,modules=3,cores=2,threads=2
-smp cpus=24,sockets=2,dies=3,modules=1,cores=2,threads=2
-smp cpus=24,sockets=2,dies=3,cores=2,threads=2
---
Changes since Patch v3:
* Now commit to stop exposing "invalid" enumeration in QAPI. (Daniel)
---
include/hw/i386/topology.h | 3 ++-
target/i386/cpu.c | 13 ++++++++-----
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index dff49fce1154..48b43edc5a90 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -62,6 +62,8 @@ typedef struct X86CPUTopoInfo {
unsigned threads_per_core;
} X86CPUTopoInfo;
+#define CPU_TOPO_LEVEL_INVALID CPU_TOPO_LEVEL_MAX
+
/*
* CPUTopoLevel is the general i386 topology hierarchical representation,
* ordered by increasing hierarchical relationship.
@@ -69,7 +71,6 @@ typedef struct X86CPUTopoInfo {
* or AMD (CPUID[0x80000026]).
*/
enum CPUTopoLevel {
- CPU_TOPO_LEVEL_INVALID,
CPU_TOPO_LEVEL_SMT,
CPU_TOPO_LEVEL_CORE,
CPU_TOPO_LEVEL_MODULE,
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 1ff1af032eaa..638de9c29c4c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -367,20 +367,21 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count,
uint32_t *ecx, uint32_t *edx)
{
X86CPU *cpu = env_archcpu(env);
- unsigned long level, next_level;
+ unsigned long level, base_level, next_level;
uint32_t num_threads_next_level, offset_next_level;
- assert(count + 1 < CPU_TOPO_LEVEL_MAX);
+ assert(count <= CPU_TOPO_LEVEL_PACKAGE);
/*
* Find the No.(count + 1) topology level in avail_cpu_topo bitmap.
- * The search starts from bit 1 (CPU_TOPO_LEVEL_INVALID + 1).
+ * The search starts from bit 0 (CPU_TOPO_LEVEL_SMT).
*/
- level = CPU_TOPO_LEVEL_INVALID;
+ level = CPU_TOPO_LEVEL_SMT;
+ base_level = level;
for (int i = 0; i <= count; i++) {
level = find_next_bit(env->avail_cpu_topo,
CPU_TOPO_LEVEL_PACKAGE,
- level + 1);
+ base_level);
/*
* CPUID[0x1f] doesn't explicitly encode the package level,
@@ -391,6 +392,8 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count,
level = CPU_TOPO_LEVEL_INVALID;
break;
}
+ /* Search the next level. */
+ base_level = level + 1;
}
if (level == CPU_TOPO_LEVEL_INVALID) {
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 2/9] hw/core: Make CPU topology enumeration arch-agnostic
2024-10-22 13:51 [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
2024-10-22 13:51 ` [PATCH v4 1/9] i386/cpu: Don't enumerate the "invalid" CPU topology level Zhao Liu
@ 2024-10-22 13:51 ` Zhao Liu
2024-10-29 20:10 ` Philippe Mathieu-Daudé
2024-10-22 13:51 ` [PATCH v4 3/9] qapi/qom: Define cache enumeration and properties for machine Zhao Liu
` (7 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Zhao Liu @ 2024-10-22 13:51 UTC (permalink / raw)
To: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
Michael S . Tsirkin, Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Jonathan Cameron, Sia Jee Heng, Alireza Sanaee
Cc: qemu-devel, kvm, qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi,
Zhao Liu, Yongwei Ma
Cache topology needs to be defined based on CPU topology levels. Thus,
define CPU topology enumeration in qapi/machine.json to make it generic
for all architectures.
To match the general topology naming style, rename CPU_TOPO_LEVEL_* to
CPU_TOPOLOGY_LEVEL_*, and rename SMT and package levels to thread and
socket.
Also, enumerate additional topology levels for non-i386 arches, and add
a CPU_TOPOLOGY_LEVEL_DEFAULT to help future smp-cache object to work
with compatibility requirement of arch-specific cache topology models.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Changes since Patch v3:
* Dropped "invalid" level to avoid an unsettable option. (Daniel)
---
hw/i386/x86-common.c | 4 +-
include/hw/i386/topology.h | 23 ++----
qapi/machine-common.json | 44 +++++++++++-
target/i386/cpu.c | 144 ++++++++++++++++++-------------------
target/i386/cpu.h | 4 +-
5 files changed, 123 insertions(+), 96 deletions(-)
diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c
index b86c38212eab..bc360a9ea44b 100644
--- a/hw/i386/x86-common.c
+++ b/hw/i386/x86-common.c
@@ -273,12 +273,12 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
if (ms->smp.modules > 1) {
env->nr_modules = ms->smp.modules;
- set_bit(CPU_TOPO_LEVEL_MODULE, env->avail_cpu_topo);
+ set_bit(CPU_TOPOLOGY_LEVEL_MODULE, env->avail_cpu_topo);
}
if (ms->smp.dies > 1) {
env->nr_dies = ms->smp.dies;
- set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo);
+ set_bit(CPU_TOPOLOGY_LEVEL_DIE, env->avail_cpu_topo);
}
/*
diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
index 48b43edc5a90..b2c8bf2de158 100644
--- a/include/hw/i386/topology.h
+++ b/include/hw/i386/topology.h
@@ -39,7 +39,7 @@
* CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width().
*/
-
+#include "qapi/qapi-types-machine-common.h"
#include "qemu/bitops.h"
/*
@@ -62,22 +62,7 @@ typedef struct X86CPUTopoInfo {
unsigned threads_per_core;
} X86CPUTopoInfo;
-#define CPU_TOPO_LEVEL_INVALID CPU_TOPO_LEVEL_MAX
-
-/*
- * CPUTopoLevel is the general i386 topology hierarchical representation,
- * ordered by increasing hierarchical relationship.
- * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F])
- * or AMD (CPUID[0x80000026]).
- */
-enum CPUTopoLevel {
- CPU_TOPO_LEVEL_SMT,
- CPU_TOPO_LEVEL_CORE,
- CPU_TOPO_LEVEL_MODULE,
- CPU_TOPO_LEVEL_DIE,
- CPU_TOPO_LEVEL_PACKAGE,
- CPU_TOPO_LEVEL_MAX,
-};
+#define CPU_TOPOLOGY_LEVEL_INVALID CPU_TOPOLOGY_LEVEL__MAX
/* Return the bit width needed for 'count' IDs */
static unsigned apicid_bitwidth_for_count(unsigned count)
@@ -213,8 +198,8 @@ static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info,
*/
static inline bool x86_has_extended_topo(unsigned long *topo_bitmap)
{
- return test_bit(CPU_TOPO_LEVEL_MODULE, topo_bitmap) ||
- test_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap);
+ return test_bit(CPU_TOPOLOGY_LEVEL_MODULE, topo_bitmap) ||
+ test_bit(CPU_TOPOLOGY_LEVEL_DIE, topo_bitmap);
}
#endif /* HW_I386_TOPOLOGY_H */
diff --git a/qapi/machine-common.json b/qapi/machine-common.json
index b64e4895cfd7..1a5687fb99fc 100644
--- a/qapi/machine-common.json
+++ b/qapi/machine-common.json
@@ -5,7 +5,7 @@
# See the COPYING file in the top-level directory.
##
-# = Machines S390 data types
+# = Common machine types
##
##
@@ -18,3 +18,45 @@
##
{ 'enum': 'S390CpuEntitlement',
'data': [ 'auto', 'low', 'medium', 'high' ] }
+
+##
+# @CpuTopologyLevel:
+#
+# An enumeration of CPU topology levels.
+#
+# @thread: thread level, which would also be called SMT level or
+# logical processor level. The @threads option in
+# SMPConfiguration is used to configure the topology of this
+# level.
+#
+# @core: core level. The @cores option in SMPConfiguration is used
+# to configure the topology of this level.
+#
+# @module: module level. The @modules option in SMPConfiguration is
+# used to configure the topology of this level.
+#
+# @cluster: cluster level. The @clusters option in SMPConfiguration
+# is used to configure the topology of this level.
+#
+# @die: die level. The @dies option in SMPConfiguration is used to
+# configure the topology of this level.
+#
+# @socket: socket level, which would also be called package level.
+# The @sockets option in SMPConfiguration is used to configure
+# the topology of this level.
+#
+# @book: book level. The @books option in SMPConfiguration is used
+# to configure the topology of this level.
+#
+# @drawer: drawer level. The @drawers option in SMPConfiguration is
+# used to configure the topology of this level.
+#
+# @default: default level. Some architectures will have default
+# topology settings (e.g., cache topology), and this special
+# level means following the architecture-specific settings.
+#
+# Since: 9.2
+##
+{ 'enum': 'CpuTopologyLevel',
+ 'data': [ 'thread', 'core', 'module', 'cluster', 'die',
+ 'socket', 'book', 'drawer', 'default' ] }
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 638de9c29c4c..f1cbcaf9f4ad 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -235,23 +235,23 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
0 /* Invalid value */)
static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info,
- enum CPUTopoLevel share_level)
+ enum CpuTopologyLevel share_level)
{
uint32_t num_ids = 0;
switch (share_level) {
- case CPU_TOPO_LEVEL_CORE:
+ case CPU_TOPOLOGY_LEVEL_CORE:
num_ids = 1 << apicid_core_offset(topo_info);
break;
- case CPU_TOPO_LEVEL_DIE:
+ case CPU_TOPOLOGY_LEVEL_DIE:
num_ids = 1 << apicid_die_offset(topo_info);
break;
- case CPU_TOPO_LEVEL_PACKAGE:
+ case CPU_TOPOLOGY_LEVEL_SOCKET:
num_ids = 1 << apicid_pkg_offset(topo_info);
break;
default:
/*
- * Currently there is no use case for SMT and MODULE, so use
+ * Currently there is no use case for THREAD and MODULE, so use
* assert directly to facilitate debugging.
*/
g_assert_not_reached();
@@ -300,19 +300,19 @@ static void encode_cache_cpuid4(CPUCacheInfo *cache,
}
static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info,
- enum CPUTopoLevel topo_level)
+ enum CpuTopologyLevel topo_level)
{
switch (topo_level) {
- case CPU_TOPO_LEVEL_SMT:
+ case CPU_TOPOLOGY_LEVEL_THREAD:
return 1;
- case CPU_TOPO_LEVEL_CORE:
+ case CPU_TOPOLOGY_LEVEL_CORE:
return topo_info->threads_per_core;
- case CPU_TOPO_LEVEL_MODULE:
+ case CPU_TOPOLOGY_LEVEL_MODULE:
return topo_info->threads_per_core * topo_info->cores_per_module;
- case CPU_TOPO_LEVEL_DIE:
+ case CPU_TOPOLOGY_LEVEL_DIE:
return topo_info->threads_per_core * topo_info->cores_per_module *
topo_info->modules_per_die;
- case CPU_TOPO_LEVEL_PACKAGE:
+ case CPU_TOPOLOGY_LEVEL_SOCKET:
return topo_info->threads_per_core * topo_info->cores_per_module *
topo_info->modules_per_die * topo_info->dies_per_pkg;
default:
@@ -322,18 +322,18 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoInfo *topo_info,
}
static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info,
- enum CPUTopoLevel topo_level)
+ enum CpuTopologyLevel topo_level)
{
switch (topo_level) {
- case CPU_TOPO_LEVEL_SMT:
+ case CPU_TOPOLOGY_LEVEL_THREAD:
return 0;
- case CPU_TOPO_LEVEL_CORE:
+ case CPU_TOPOLOGY_LEVEL_CORE:
return apicid_core_offset(topo_info);
- case CPU_TOPO_LEVEL_MODULE:
+ case CPU_TOPOLOGY_LEVEL_MODULE:
return apicid_module_offset(topo_info);
- case CPU_TOPO_LEVEL_DIE:
+ case CPU_TOPOLOGY_LEVEL_DIE:
return apicid_die_offset(topo_info);
- case CPU_TOPO_LEVEL_PACKAGE:
+ case CPU_TOPOLOGY_LEVEL_SOCKET:
return apicid_pkg_offset(topo_info);
default:
g_assert_not_reached();
@@ -341,18 +341,18 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info,
return 0;
}
-static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level)
+static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level)
{
switch (topo_level) {
- case CPU_TOPO_LEVEL_INVALID:
+ case CPU_TOPOLOGY_LEVEL_INVALID:
return CPUID_1F_ECX_TOPO_LEVEL_INVALID;
- case CPU_TOPO_LEVEL_SMT:
+ case CPU_TOPOLOGY_LEVEL_THREAD:
return CPUID_1F_ECX_TOPO_LEVEL_SMT;
- case CPU_TOPO_LEVEL_CORE:
+ case CPU_TOPOLOGY_LEVEL_CORE:
return CPUID_1F_ECX_TOPO_LEVEL_CORE;
- case CPU_TOPO_LEVEL_MODULE:
+ case CPU_TOPOLOGY_LEVEL_MODULE:
return CPUID_1F_ECX_TOPO_LEVEL_MODULE;
- case CPU_TOPO_LEVEL_DIE:
+ case CPU_TOPOLOGY_LEVEL_DIE:
return CPUID_1F_ECX_TOPO_LEVEL_DIE;
default:
/* Other types are not supported in QEMU. */
@@ -370,17 +370,17 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count,
unsigned long level, base_level, next_level;
uint32_t num_threads_next_level, offset_next_level;
- assert(count <= CPU_TOPO_LEVEL_PACKAGE);
+ assert(count <= CPU_TOPOLOGY_LEVEL_SOCKET);
/*
* Find the No.(count + 1) topology level in avail_cpu_topo bitmap.
- * The search starts from bit 0 (CPU_TOPO_LEVEL_SMT).
+ * The search starts from bit 0 (CPU_TOPOLOGY_LEVEL_THREAD).
*/
- level = CPU_TOPO_LEVEL_SMT;
+ level = CPU_TOPOLOGY_LEVEL_THREAD;
base_level = level;
for (int i = 0; i <= count; i++) {
level = find_next_bit(env->avail_cpu_topo,
- CPU_TOPO_LEVEL_PACKAGE,
+ CPU_TOPOLOGY_LEVEL_SOCKET,
base_level);
/*
@@ -388,20 +388,20 @@ static void encode_topo_cpuid1f(CPUX86State *env, uint32_t count,
* and it just encodes the invalid level (all fields are 0)
* into the last subleaf of 0x1f.
*/
- if (level == CPU_TOPO_LEVEL_PACKAGE) {
- level = CPU_TOPO_LEVEL_INVALID;
+ if (level == CPU_TOPOLOGY_LEVEL_SOCKET) {
+ level = CPU_TOPOLOGY_LEVEL_INVALID;
break;
}
/* Search the next level. */
base_level = level + 1;
}
- if (level == CPU_TOPO_LEVEL_INVALID) {
+ if (level == CPU_TOPOLOGY_LEVEL_INVALID) {
num_threads_next_level = 0;
offset_next_level = 0;
} else {
next_level = find_next_bit(env->avail_cpu_topo,
- CPU_TOPO_LEVEL_PACKAGE,
+ CPU_TOPOLOGY_LEVEL_SOCKET,
level + 1);
num_threads_next_level = num_threads_by_topo_level(topo_info,
next_level);
@@ -577,7 +577,7 @@ static CPUCacheInfo legacy_l1d_cache = {
.sets = 64,
.partitions = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
@@ -592,7 +592,7 @@ static CPUCacheInfo legacy_l1d_cache_amd = {
.partitions = 1,
.lines_per_tag = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/* L1 instruction cache: */
@@ -606,7 +606,7 @@ static CPUCacheInfo legacy_l1i_cache = {
.sets = 64,
.partitions = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
@@ -621,7 +621,7 @@ static CPUCacheInfo legacy_l1i_cache_amd = {
.partitions = 1,
.lines_per_tag = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/* Level 2 unified cache: */
@@ -635,7 +635,7 @@ static CPUCacheInfo legacy_l2_cache = {
.sets = 4096,
.partitions = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
@@ -645,7 +645,7 @@ static CPUCacheInfo legacy_l2_cache_cpuid2 = {
.size = 2 * MiB,
.line_size = 64,
.associativity = 8,
- .share_level = CPU_TOPO_LEVEL_INVALID,
+ .share_level = CPU_TOPOLOGY_LEVEL_INVALID,
};
@@ -659,7 +659,7 @@ static CPUCacheInfo legacy_l2_cache_amd = {
.associativity = 16,
.sets = 512,
.partitions = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
};
/* Level 3 unified cache: */
@@ -675,7 +675,7 @@ static CPUCacheInfo legacy_l3_cache = {
.self_init = true,
.inclusive = true,
.complex_indexing = true,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
};
/* TLB definitions: */
@@ -2026,7 +2026,7 @@ static const CPUCaches epyc_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2039,7 +2039,7 @@ static const CPUCaches epyc_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2050,7 +2050,7 @@ static const CPUCaches epyc_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2064,7 +2064,7 @@ static const CPUCaches epyc_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = true,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -2080,7 +2080,7 @@ static CPUCaches epyc_v4_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2093,7 +2093,7 @@ static CPUCaches epyc_v4_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2104,7 +2104,7 @@ static CPUCaches epyc_v4_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2118,7 +2118,7 @@ static CPUCaches epyc_v4_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = false,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -2134,7 +2134,7 @@ static const CPUCaches epyc_rome_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2147,7 +2147,7 @@ static const CPUCaches epyc_rome_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2158,7 +2158,7 @@ static const CPUCaches epyc_rome_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2172,7 +2172,7 @@ static const CPUCaches epyc_rome_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = true,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -2188,7 +2188,7 @@ static const CPUCaches epyc_rome_v3_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2201,7 +2201,7 @@ static const CPUCaches epyc_rome_v3_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2212,7 +2212,7 @@ static const CPUCaches epyc_rome_v3_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2226,7 +2226,7 @@ static const CPUCaches epyc_rome_v3_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = false,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -2242,7 +2242,7 @@ static const CPUCaches epyc_milan_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2255,7 +2255,7 @@ static const CPUCaches epyc_milan_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2266,7 +2266,7 @@ static const CPUCaches epyc_milan_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2280,7 +2280,7 @@ static const CPUCaches epyc_milan_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = true,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -2296,7 +2296,7 @@ static const CPUCaches epyc_milan_v2_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2309,7 +2309,7 @@ static const CPUCaches epyc_milan_v2_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2320,7 +2320,7 @@ static const CPUCaches epyc_milan_v2_cache_info = {
.partitions = 1,
.sets = 1024,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2334,7 +2334,7 @@ static const CPUCaches epyc_milan_v2_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = false,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -2350,7 +2350,7 @@ static const CPUCaches epyc_genoa_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l1i_cache = &(CPUCacheInfo) {
.type = INSTRUCTION_CACHE,
@@ -2363,7 +2363,7 @@ static const CPUCaches epyc_genoa_cache_info = {
.lines_per_tag = 1,
.self_init = 1,
.no_invd_sharing = true,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l2_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2374,7 +2374,7 @@ static const CPUCaches epyc_genoa_cache_info = {
.partitions = 1,
.sets = 2048,
.lines_per_tag = 1,
- .share_level = CPU_TOPO_LEVEL_CORE,
+ .share_level = CPU_TOPOLOGY_LEVEL_CORE,
},
.l3_cache = &(CPUCacheInfo) {
.type = UNIFIED_CACHE,
@@ -2388,7 +2388,7 @@ static const CPUCaches epyc_genoa_cache_info = {
.self_init = true,
.inclusive = true,
.complex_indexing = false,
- .share_level = CPU_TOPO_LEVEL_DIE,
+ .share_level = CPU_TOPOLOGY_LEVEL_DIE,
},
};
@@ -6512,7 +6512,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
/* Share the cache at package level. */
*eax |= max_thread_ids_for_cache(&topo_info,
- CPU_TOPO_LEVEL_PACKAGE) << 14;
+ CPU_TOPOLOGY_LEVEL_SOCKET) << 14;
}
}
} else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) {
@@ -7998,10 +7998,10 @@ static void x86_cpu_init_default_topo(X86CPU *cpu)
env->nr_modules = 1;
env->nr_dies = 1;
- /* SMT, core and package levels are set by default. */
- set_bit(CPU_TOPO_LEVEL_SMT, env->avail_cpu_topo);
- set_bit(CPU_TOPO_LEVEL_CORE, env->avail_cpu_topo);
- set_bit(CPU_TOPO_LEVEL_PACKAGE, env->avail_cpu_topo);
+ /* thread, core and socket levels are set by default. */
+ set_bit(CPU_TOPOLOGY_LEVEL_THREAD, env->avail_cpu_topo);
+ set_bit(CPU_TOPOLOGY_LEVEL_CORE, env->avail_cpu_topo);
+ set_bit(CPU_TOPOLOGY_LEVEL_SOCKET, env->avail_cpu_topo);
}
static void x86_cpu_initfn(Object *obj)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 74886d1580f4..abb75019ca61 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1666,7 +1666,7 @@ typedef struct CPUCacheInfo {
* Used to encode CPUID[4].EAX[bits 25:14] or
* CPUID[0x8000001D].EAX[bits 25:14].
*/
- enum CPUTopoLevel share_level;
+ CpuTopologyLevel share_level;
} CPUCacheInfo;
@@ -1999,7 +1999,7 @@ typedef struct CPUArchState {
unsigned nr_modules;
/* Bitmap of available CPU topology levels for this CPU. */
- DECLARE_BITMAP(avail_cpu_topo, CPU_TOPO_LEVEL_MAX);
+ DECLARE_BITMAP(avail_cpu_topo, CPU_TOPOLOGY_LEVEL__MAX);
} CPUX86State;
struct kvm_msrs;
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 3/9] qapi/qom: Define cache enumeration and properties for machine
2024-10-22 13:51 [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
2024-10-22 13:51 ` [PATCH v4 1/9] i386/cpu: Don't enumerate the "invalid" CPU topology level Zhao Liu
2024-10-22 13:51 ` [PATCH v4 2/9] hw/core: Make CPU topology enumeration arch-agnostic Zhao Liu
@ 2024-10-22 13:51 ` Zhao Liu
2024-10-22 13:51 ` [PATCH v4 4/9] hw/core: Check smp cache topology support " Zhao Liu
` (6 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Zhao Liu @ 2024-10-22 13:51 UTC (permalink / raw)
To: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
Michael S . Tsirkin, Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Jonathan Cameron, Sia Jee Heng, Alireza Sanaee
Cc: qemu-devel, kvm, qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi,
Zhao Liu, Yongwei Ma
The x86 and ARM need to allow user to configure cache properties
(current only topology):
* For x86, the default cache topology model (of max/host CPU) does not
always match the Host's real physical cache topology. Performance can
increase when the configured virtual topology is closer to the
physical topology than a default topology would be.
* For ARM, QEMU can't get the cache topology information from the CPU
registers, then user configuration is necessary. Additionally, the
cache information is also needed for MPAM emulation (for TCG) to
build the right PPTT.
Define smp-cache related enumeration and properties in QAPI, so that
user could configure cache properties for SMP system through -machine in
the subsequent patch.
Cache enumeration (CacheLevelAndType) is implemented as the combination
of cache level (level 1/2/3) and cache type (data/instruction/unified).
Currently, separated L1 cache (L1 data cache and L1 instruction cache)
with unified higher-level cache (e.g., unified L2 and L3 caches), is the
most common cache architectures.
Therefore, enumerate the L1 D-cache, L1 I-cache, L2 cache and L3 cache
with smp-cache object to add the basic cache topology support. Other
kinds of caches (e.g., L1 unified or L2/L3 separated caches) can be
added directly into CacheLevelAndType if necessary.
Cache properties (SmpCacheProperties) currently only contains cache
topology information, and other cache properties can be added in it
if necessary.
Note, define cache topology based on CPU topology level with two
reasons:
1. In practice, a cache will always be bound to the CPU container
(either private in the CPU container or shared among multiple
containers), and CPU container is often expressed in terms of CPU
topology level.
2. The x86's cache-related CPUIDs encode cache topology based on APIC
ID's CPU topology layout. And the ACPI PPTT table that ARM/RISCV
relies on also requires CPU containers to help indicate the private
shared hierarchy of the cache. Therefore, for SMP systems, it is
natural to use the CPU topology hierarchy directly in QEMU to define
the cache topology.
With smp-cache QAPI support, add smp cache topology for machine by
parsing the smp-cache object list.
Also add the helper to access/update cache topology level of machine.
Suggested-by: Daniel P. Berrange <berrange@redhat.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Suggested by credit:
* Referred to Daniel's suggestion to introduce cache object list.
---
Changes since Patch v3:
* Dropped "invalid" level check since now we don't enumerate it in
QAPI. (Daniel)
* Added a helper to update MachineState.smp_cache (
machine_set_cache_topo_level).
---
hw/core/machine-smp.c | 37 +++++++++++++++++++++++++++++
hw/core/machine.c | 44 +++++++++++++++++++++++++++++++++++
include/hw/boards.h | 12 ++++++++++
qapi/machine-common.json | 50 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 143 insertions(+)
diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
index 5d8d7edcbd3f..c6d90cd6d413 100644
--- a/hw/core/machine-smp.c
+++ b/hw/core/machine-smp.c
@@ -261,6 +261,31 @@ void machine_parse_smp_config(MachineState *ms,
}
}
+bool machine_parse_smp_cache(MachineState *ms,
+ const SmpCachePropertiesList *caches,
+ Error **errp)
+{
+ const SmpCachePropertiesList *node;
+ DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX);
+
+ for (node = caches; node; node = node->next) {
+ /* Prohibit users from repeating settings. */
+ if (test_bit(node->value->cache, caches_bitmap)) {
+ error_setg(errp,
+ "Invalid cache properties: %s. "
+ "The cache properties are duplicated",
+ CacheLevelAndType_str(node->value->cache));
+ return false;
+ }
+
+ machine_set_cache_topo_level(ms, node->value->cache,
+ node->value->topology);
+ set_bit(node->value->cache, caches_bitmap);
+ }
+
+ return true;
+}
+
unsigned int machine_topo_get_cores_per_socket(const MachineState *ms)
{
return ms->smp.cores * ms->smp.modules * ms->smp.clusters * ms->smp.dies;
@@ -270,3 +295,15 @@ unsigned int machine_topo_get_threads_per_socket(const MachineState *ms)
{
return ms->smp.threads * machine_topo_get_cores_per_socket(ms);
}
+
+CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms,
+ CacheLevelAndType cache)
+{
+ return ms->smp_cache.props[cache].topology;
+}
+
+void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache,
+ CpuTopologyLevel level)
+{
+ ms->smp_cache.props[cache].topology = level;
+}
diff --git a/hw/core/machine.c b/hw/core/machine.c
index adaba17ebac1..518beb9f883a 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -932,6 +932,40 @@ static void machine_set_smp(Object *obj, Visitor *v, const char *name,
machine_parse_smp_config(ms, config, errp);
}
+static void machine_get_smp_cache(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ MachineState *ms = MACHINE(obj);
+ SmpCache *cache = &ms->smp_cache;
+ SmpCachePropertiesList *head = NULL;
+ SmpCachePropertiesList **tail = &head;
+
+ for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) {
+ SmpCacheProperties *node = g_new(SmpCacheProperties, 1);
+
+ node->cache = cache->props[i].cache;
+ node->topology = cache->props[i].topology;
+ QAPI_LIST_APPEND(tail, node);
+ }
+
+ visit_type_SmpCachePropertiesList(v, name, &head, errp);
+ qapi_free_SmpCachePropertiesList(head);
+}
+
+static void machine_set_smp_cache(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ MachineState *ms = MACHINE(obj);
+ SmpCachePropertiesList *caches;
+
+ if (!visit_type_SmpCachePropertiesList(v, name, &caches, errp)) {
+ return;
+ }
+
+ machine_parse_smp_cache(ms, caches, errp);
+ qapi_free_SmpCachePropertiesList(caches);
+}
+
static void machine_get_boot(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -1057,6 +1091,11 @@ static void machine_class_init(ObjectClass *oc, void *data)
object_class_property_set_description(oc, "smp",
"CPU topology");
+ object_class_property_add(oc, "smp-cache", "SmpCachePropertiesWrapper",
+ machine_get_smp_cache, machine_set_smp_cache, NULL, NULL);
+ object_class_property_set_description(oc, "smp-cache",
+ "Cache properties list for SMP machine");
+
object_class_property_add(oc, "phandle-start", "int",
machine_get_phandle_start, machine_set_phandle_start,
NULL, NULL);
@@ -1195,6 +1234,11 @@ static void machine_initfn(Object *obj)
ms->smp.cores = 1;
ms->smp.threads = 1;
+ for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) {
+ ms->smp_cache.props[i].cache = (CacheLevelAndType)i;
+ ms->smp_cache.props[i].topology = CPU_TOPOLOGY_LEVEL_DEFAULT;
+ }
+
machine_copy_boot_config(ms, &(BootConfiguration){ 0 });
}
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 5966069baab3..f7591d54a3d3 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -44,8 +44,15 @@ void machine_set_cpu_numa_node(MachineState *machine,
Error **errp);
void machine_parse_smp_config(MachineState *ms,
const SMPConfiguration *config, Error **errp);
+bool machine_parse_smp_cache(MachineState *ms,
+ const SmpCachePropertiesList *caches,
+ Error **errp);
unsigned int machine_topo_get_cores_per_socket(const MachineState *ms);
unsigned int machine_topo_get_threads_per_socket(const MachineState *ms);
+CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms,
+ CacheLevelAndType cache);
+void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache,
+ CpuTopologyLevel level);
void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size);
/**
@@ -369,6 +376,10 @@ typedef struct CpuTopology {
unsigned int max_cpus;
} CpuTopology;
+typedef struct SmpCache {
+ SmpCacheProperties props[CACHE_LEVEL_AND_TYPE__MAX];
+} SmpCache;
+
/**
* MachineState:
*/
@@ -419,6 +430,7 @@ struct MachineState {
AccelState *accelerator;
CPUArchIdList *possible_cpus;
CpuTopology smp;
+ SmpCache smp_cache;
struct NVDIMMState *nvdimms_state;
struct NumaState *numa_state;
};
diff --git a/qapi/machine-common.json b/qapi/machine-common.json
index 1a5687fb99fc..298e51f373a3 100644
--- a/qapi/machine-common.json
+++ b/qapi/machine-common.json
@@ -60,3 +60,53 @@
{ 'enum': 'CpuTopologyLevel',
'data': [ 'thread', 'core', 'module', 'cluster', 'die',
'socket', 'book', 'drawer', 'default' ] }
+
+##
+# @CacheLevelAndType:
+#
+# Caches a system may have. The enumeration value here is the
+# combination of cache level and cache type.
+#
+# @l1d: L1 data cache.
+#
+# @l1i: L1 instruction cache.
+#
+# @l2: L2 (unified) cache.
+#
+# @l3: L3 (unified) cache
+#
+# Since: 9.2
+##
+{ 'enum': 'CacheLevelAndType',
+ 'data': [ 'l1d', 'l1i', 'l2', 'l3' ] }
+
+##
+# @SmpCacheProperties:
+#
+# Cache information for SMP system.
+#
+# @cache: Cache name, which is the combination of cache level
+# and cache type.
+#
+# @topology: Cache topology level. It accepts the CPU topology
+# enumeration as the parameter, i.e., CPUs in the same
+# topology container share the same cache.
+#
+# Since: 9.2
+##
+{ 'struct': 'SmpCacheProperties',
+ 'data': {
+ 'cache': 'CacheLevelAndType',
+ 'topology': 'CpuTopologyLevel' } }
+
+##
+# @SmpCachePropertiesWrapper:
+#
+# List wrapper of SmpCacheProperties.
+#
+# @caches: the list of SmpCacheProperties.
+#
+# Since 9.2
+##
+{ 'struct': 'SmpCachePropertiesWrapper',
+ 'data': { 'caches': ['SmpCacheProperties'] } }
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 4/9] hw/core: Check smp cache topology support for machine
2024-10-22 13:51 [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
` (2 preceding siblings ...)
2024-10-22 13:51 ` [PATCH v4 3/9] qapi/qom: Define cache enumeration and properties for machine Zhao Liu
@ 2024-10-22 13:51 ` Zhao Liu
2024-10-22 13:51 ` [PATCH v4 5/9] hw/core: Add a helper to check the cache topology level Zhao Liu
` (5 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Zhao Liu @ 2024-10-22 13:51 UTC (permalink / raw)
To: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
Michael S . Tsirkin, Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Jonathan Cameron, Sia Jee Heng, Alireza Sanaee
Cc: qemu-devel, kvm, qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi,
Zhao Liu, Yongwei Ma
Add cache_supported flags in SMPCompatProps to allow machines to
configure various caches support.
And check the compatibility of the cache properties with the
machine support in machine_parse_smp_cache().
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Changes since Patch v3:
* Dropped cache level check because if some fields is marked as
default, then we can't guarentee the hierarchies are correct.
(Daniel)
---
hw/core/machine-smp.c | 41 +++++++++++++++++++++++++++++++++++++++++
include/hw/boards.h | 3 +++
2 files changed, 44 insertions(+)
diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
index c6d90cd6d413..ebb7a134a7be 100644
--- a/hw/core/machine-smp.c
+++ b/hw/core/machine-smp.c
@@ -261,10 +261,32 @@ void machine_parse_smp_config(MachineState *ms,
}
}
+static bool machine_check_topo_support(MachineState *ms,
+ CpuTopologyLevel topo,
+ Error **errp)
+{
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
+
+ if ((topo == CPU_TOPOLOGY_LEVEL_MODULE && !mc->smp_props.modules_supported) ||
+ (topo == CPU_TOPOLOGY_LEVEL_CLUSTER && !mc->smp_props.clusters_supported) ||
+ (topo == CPU_TOPOLOGY_LEVEL_DIE && !mc->smp_props.dies_supported) ||
+ (topo == CPU_TOPOLOGY_LEVEL_BOOK && !mc->smp_props.books_supported) ||
+ (topo == CPU_TOPOLOGY_LEVEL_DRAWER && !mc->smp_props.drawers_supported)) {
+ error_setg(errp,
+ "Invalid topology level: %s. "
+ "The topology level is not supported by this machine",
+ CpuTopologyLevel_str(topo));
+ return false;
+ }
+
+ return true;
+}
+
bool machine_parse_smp_cache(MachineState *ms,
const SmpCachePropertiesList *caches,
Error **errp)
{
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
const SmpCachePropertiesList *node;
DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX);
@@ -283,6 +305,25 @@ bool machine_parse_smp_cache(MachineState *ms,
set_bit(node->value->cache, caches_bitmap);
}
+ for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) {
+ const SmpCacheProperties *props = &ms->smp_cache.props[i];
+
+ /*
+ * Reject non "default" topology level if the cache isn't
+ * supported by the machine.
+ */
+ if (props->topology != CPU_TOPOLOGY_LEVEL_DEFAULT &&
+ !mc->smp_props.cache_supported[props->cache]) {
+ error_setg(errp,
+ "%s cache topology not supported by this machine",
+ CacheLevelAndType_str(node->value->cache));
+ return false;
+ }
+
+ if (!machine_check_topo_support(ms, props->topology, errp)) {
+ return false;
+ }
+ }
return true;
}
diff --git a/include/hw/boards.h b/include/hw/boards.h
index f7591d54a3d3..3d6cb5acd6c7 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -153,6 +153,8 @@ typedef struct {
* @books_supported - whether books are supported by the machine
* @drawers_supported - whether drawers are supported by the machine
* @modules_supported - whether modules are supported by the machine
+ * @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are
+ * supported by the machine
*/
typedef struct {
bool prefer_sockets;
@@ -162,6 +164,7 @@ typedef struct {
bool books_supported;
bool drawers_supported;
bool modules_supported;
+ bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX];
} SMPCompatProps;
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 5/9] hw/core: Add a helper to check the cache topology level
2024-10-22 13:51 [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
` (3 preceding siblings ...)
2024-10-22 13:51 ` [PATCH v4 4/9] hw/core: Check smp cache topology support " Zhao Liu
@ 2024-10-22 13:51 ` Zhao Liu
2024-10-22 14:44 ` Jonathan Cameron via
2024-10-22 13:51 ` [PATCH v4 6/9] i386/cpu: Support thread and module level cache topology Zhao Liu
` (4 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Zhao Liu @ 2024-10-22 13:51 UTC (permalink / raw)
To: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
Michael S . Tsirkin, Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Jonathan Cameron, Sia Jee Heng, Alireza Sanaee
Cc: qemu-devel, kvm, qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi,
Zhao Liu
Currently, we have no way to expose the arch-specific default cache
model because the cache model is sometimes related to the CPU model
(e.g., i386).
Since the user might configure "default" level, any comparison with
"default" is meaningless before the machine knows the specific level
that "default" refers to.
We can only check the correctness of the cache topology after the arch
loads the user-configured cache model from MachineState.smp_cache and
consumes the special "default" level by replacing it with the specific
level.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes since Patch v3:
* New commit to make cache topology check as a separate helper, so that
arch-specific code could use this helper to check cache topology.
---
hw/core/machine-smp.c | 48 +++++++++++++++++++++++++++++++++++++++++++
include/hw/boards.h | 1 +
2 files changed, 49 insertions(+)
diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
index ebb7a134a7be..640b2114b429 100644
--- a/hw/core/machine-smp.c
+++ b/hw/core/machine-smp.c
@@ -348,3 +348,51 @@ void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache,
{
ms->smp_cache.props[cache].topology = level;
}
+
+/*
+ * When both cache1 and cache2 are configured with specific topology levels
+ * (not default level), is cache1's topology level higher than cache2?
+ */
+static bool smp_cache_topo_cmp(const SmpCache *smp_cache,
+ CacheLevelAndType cache1,
+ CacheLevelAndType cache2)
+{
+ /*
+ * Before comparing, the "default" topology level should be replaced
+ * with the specific level.
+ */
+ assert(smp_cache->props[cache1].topology != CPU_TOPOLOGY_LEVEL_DEFAULT);
+
+ return smp_cache->props[cache1].topology > smp_cache->props[cache2].topology;
+}
+
+/*
+ * Currently, we have no way to expose the arch-specific default cache model
+ * because the cache model is sometimes related to the CPU model (e.g., i386).
+ *
+ * We can only check the correctness of the cache topology after the arch loads
+ * the user-configured cache model from MachineState and consumes the special
+ * "default" level by replacing it with the specific level.
+ */
+bool machine_check_smp_cache(const MachineState *ms, Error **errp)
+{
+ if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1D,
+ CACHE_LEVEL_AND_TYPE_L2) ||
+ smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L1I,
+ CACHE_LEVEL_AND_TYPE_L2)) {
+ error_setg(errp,
+ "Invalid smp cache topology. "
+ "L2 cache topology level shouldn't be lower than L1 cache");
+ return false;
+ }
+
+ if (smp_cache_topo_cmp(&ms->smp_cache, CACHE_LEVEL_AND_TYPE_L2,
+ CACHE_LEVEL_AND_TYPE_L3)) {
+ error_setg(errp,
+ "Invalid smp cache topology. "
+ "L3 cache topology level shouldn't be lower than L2 cache");
+ return false;
+ }
+
+ return true;
+}
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 3d6cb5acd6c7..192f78539a6e 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -53,6 +53,7 @@ CpuTopologyLevel machine_get_cache_topo_level(const MachineState *ms,
CacheLevelAndType cache);
void machine_set_cache_topo_level(MachineState *ms, CacheLevelAndType cache,
CpuTopologyLevel level);
+bool machine_check_smp_cache(const MachineState *ms, Error **errp);
void machine_memory_devices_init(MachineState *ms, hwaddr base, uint64_t size);
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 6/9] i386/cpu: Support thread and module level cache topology
2024-10-22 13:51 [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
` (4 preceding siblings ...)
2024-10-22 13:51 ` [PATCH v4 5/9] hw/core: Add a helper to check the cache topology level Zhao Liu
@ 2024-10-22 13:51 ` Zhao Liu
2024-10-22 13:51 ` [PATCH v4 7/9] i386/cpu: Update cache topology with machine's configuration Zhao Liu
` (3 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Zhao Liu @ 2024-10-22 13:51 UTC (permalink / raw)
To: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
Michael S . Tsirkin, Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Jonathan Cameron, Sia Jee Heng, Alireza Sanaee
Cc: qemu-devel, kvm, qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi,
Zhao Liu, Yongwei Ma
Allow cache to be defined at the thread and module level. This
increases flexibility for x86 users to customize their cache topology.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
target/i386/cpu.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f1cbcaf9f4ad..3a5b5557f74b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -240,9 +240,15 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info,
uint32_t num_ids = 0;
switch (share_level) {
+ case CPU_TOPOLOGY_LEVEL_THREAD:
+ num_ids = 1;
+ break;
case CPU_TOPOLOGY_LEVEL_CORE:
num_ids = 1 << apicid_core_offset(topo_info);
break;
+ case CPU_TOPOLOGY_LEVEL_MODULE:
+ num_ids = 1 << apicid_module_offset(topo_info);
+ break;
case CPU_TOPOLOGY_LEVEL_DIE:
num_ids = 1 << apicid_die_offset(topo_info);
break;
@@ -250,10 +256,6 @@ static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info,
num_ids = 1 << apicid_pkg_offset(topo_info);
break;
default:
- /*
- * Currently there is no use case for THREAD and MODULE, so use
- * assert directly to facilitate debugging.
- */
g_assert_not_reached();
}
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 7/9] i386/cpu: Update cache topology with machine's configuration
2024-10-22 13:51 [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
` (5 preceding siblings ...)
2024-10-22 13:51 ` [PATCH v4 6/9] i386/cpu: Support thread and module level cache topology Zhao Liu
@ 2024-10-22 13:51 ` Zhao Liu
2024-10-22 13:51 ` [PATCH v4 8/9] i386/pc: Support cache topology in -machine for PC machine Zhao Liu
` (2 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Zhao Liu @ 2024-10-22 13:51 UTC (permalink / raw)
To: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
Michael S . Tsirkin, Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Jonathan Cameron, Sia Jee Heng, Alireza Sanaee
Cc: qemu-devel, kvm, qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi,
Zhao Liu, Yongwei Ma
User will configure smp cache topology via -machine smp-cache.
For this case, update the x86 CPUs' cache topology with user's
configuration in MachineState.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Changes since Patch v3:
* Updated MachineState.smp_cache to consume "default" level and did a
check to ensure topological hierarchical relationships are correct.
---
target/i386/cpu.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3a5b5557f74b..b6e12b46c9cc 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7602,6 +7602,64 @@ static void x86_cpu_hyperv_realize(X86CPU *cpu)
cpu->hyperv_limits[2] = 0;
}
+#ifndef CONFIG_USER_ONLY
+static bool x86_cpu_update_smp_cache_topo(MachineState *ms, X86CPU *cpu,
+ Error **errp)
+{
+ CPUX86State *env = &cpu->env;
+ CpuTopologyLevel level;
+
+ level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D);
+ if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) {
+ env->cache_info_cpuid4.l1d_cache->share_level = level;
+ env->cache_info_amd.l1d_cache->share_level = level;
+ } else {
+ machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D,
+ env->cache_info_cpuid4.l1d_cache->share_level);
+ machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1D,
+ env->cache_info_amd.l1d_cache->share_level);
+ }
+
+ level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I);
+ if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) {
+ env->cache_info_cpuid4.l1i_cache->share_level = level;
+ env->cache_info_amd.l1i_cache->share_level = level;
+ } else {
+ machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I,
+ env->cache_info_cpuid4.l1i_cache->share_level);
+ machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L1I,
+ env->cache_info_amd.l1i_cache->share_level);
+ }
+
+ level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2);
+ if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) {
+ env->cache_info_cpuid4.l2_cache->share_level = level;
+ env->cache_info_amd.l2_cache->share_level = level;
+ } else {
+ machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2,
+ env->cache_info_cpuid4.l2_cache->share_level);
+ machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L2,
+ env->cache_info_amd.l2_cache->share_level);
+ }
+
+ level = machine_get_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3);
+ if (level != CPU_TOPOLOGY_LEVEL_DEFAULT) {
+ env->cache_info_cpuid4.l3_cache->share_level = level;
+ env->cache_info_amd.l3_cache->share_level = level;
+ } else {
+ machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3,
+ env->cache_info_cpuid4.l3_cache->share_level);
+ machine_set_cache_topo_level(ms, CACHE_LEVEL_AND_TYPE_L3,
+ env->cache_info_amd.l3_cache->share_level);
+ }
+
+ if (!machine_check_smp_cache(ms, errp)) {
+ return false;
+ }
+ return true;
+}
+#endif
+
static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
@@ -7826,6 +7884,15 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
#ifndef CONFIG_USER_ONLY
MachineState *ms = MACHINE(qdev_get_machine());
+
+ /*
+ * TODO: Add a SMPCompatProps.has_caches flag to avoid useless updates
+ * if user didn't set smp_cache.
+ */
+ if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) {
+ return;
+ }
+
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 8/9] i386/pc: Support cache topology in -machine for PC machine
2024-10-22 13:51 [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
` (6 preceding siblings ...)
2024-10-22 13:51 ` [PATCH v4 7/9] i386/cpu: Update cache topology with machine's configuration Zhao Liu
@ 2024-10-22 13:51 ` Zhao Liu
2024-10-22 13:51 ` [PATCH v4 9/9] i386/cpu: add has_caches flag to check smp_cache configuration Zhao Liu
2024-10-28 9:07 ` [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
9 siblings, 0 replies; 16+ messages in thread
From: Zhao Liu @ 2024-10-22 13:51 UTC (permalink / raw)
To: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
Michael S . Tsirkin, Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Jonathan Cameron, Sia Jee Heng, Alireza Sanaee
Cc: qemu-devel, kvm, qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi,
Zhao Liu, Yongwei Ma
Allow user to configure l1d, l1i, l2 and l3 cache topologies for PC
machine.
Additionally, add the document of "-machine smp-cache" in
qemu-options.hx.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Changes since Patch v3:
* Described the omitting cache will use "default" level and described
the default cache topology model of i386 PC machine. (Daniel)
---
hw/i386/pc.c | 4 ++++
qemu-options.hx | 31 ++++++++++++++++++++++++++++++-
2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 2047633e4cf7..8aea2308dcb9 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1791,6 +1791,10 @@ static void pc_machine_class_init(ObjectClass *oc, void *data)
mc->nvdimm_supported = true;
mc->smp_props.dies_supported = true;
mc->smp_props.modules_supported = true;
+ mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1D] = true;
+ mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L1I] = true;
+ mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L2] = true;
+ mc->smp_props.cache_supported[CACHE_LEVEL_AND_TYPE_L3] = true;
mc->default_ram_id = "pc.ram";
pcmc->default_smbios_ep_type = SMBIOS_ENTRY_POINT_TYPE_AUTO;
diff --git a/qemu-options.hx b/qemu-options.hx
index daae49414740..fe39973d97a5 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -39,7 +39,8 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \
" memory-encryption=@var{} memory encryption object to use (default=none)\n"
" hmat=on|off controls ACPI HMAT support (default=off)\n"
" memory-backend='backend-id' specifies explicitly provided backend for main RAM (default=none)\n"
- " cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n",
+ " cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n"
+ " smp-cache.0.cache=cachename,smp-cache.0.topology=topologylevel\n",
QEMU_ARCH_ALL)
SRST
``-machine [type=]name[,prop=value[,...]]``
@@ -159,6 +160,34 @@ SRST
::
-machine cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=128G,cxl-fmw.0.interleave-granularity=512
+
+ ``smp-cache.0.cache=cachename,smp-cache.0.topology=topologylevel``
+ Define cache properties for SMP system.
+
+ ``cache=cachename`` specifies the cache that the properties will be
+ applied on. This field is the combination of cache level and cache
+ type. It supports ``l1d`` (L1 data cache), ``l1i`` (L1 instruction
+ cache), ``l2`` (L2 unified cache) and ``l3`` (L3 unified cache).
+
+ ``topology=topologylevel`` sets the cache topology level. It accepts
+ CPU topology levels including ``thread``, ``core``, ``module``,
+ ``cluster``, ``die``, ``socket``, ``book``, ``drawer`` and a special
+ value ``default``. If ``default`` is set, then the cache topology will
+ follow the architecture's default cache topology model. If another
+ topology level is set, the cache will be shared at corresponding CPU
+ topology level. For example, ``topology=core`` makes the cache shared
+ by all threads within a core. The omitting cache will default to using
+ the ``default`` level.
+
+ The default cache topology model for an i386 PC machine is as follows:
+ ``l1d``, ``l1i``, and ``l2`` caches are per ``core``, while the ``l3``
+ cache is per ``die``.
+
+ Example:
+
+ ::
+
+ -machine smp-cache.0.cache=l1d,smp-cache.0.topology=core,smp-cache.1.cache=l1i,smp-cache.1.topology=core
ERST
DEF("M", HAS_ARG, QEMU_OPTION_M,
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 9/9] i386/cpu: add has_caches flag to check smp_cache configuration
2024-10-22 13:51 [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
` (7 preceding siblings ...)
2024-10-22 13:51 ` [PATCH v4 8/9] i386/pc: Support cache topology in -machine for PC machine Zhao Liu
@ 2024-10-22 13:51 ` Zhao Liu
2024-10-28 9:07 ` [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
9 siblings, 0 replies; 16+ messages in thread
From: Zhao Liu @ 2024-10-22 13:51 UTC (permalink / raw)
To: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
Michael S . Tsirkin, Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Jonathan Cameron, Sia Jee Heng, Alireza Sanaee
Cc: qemu-devel, kvm, qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi,
Zhao Liu
From: Alireza Sanaee <alireza.sanaee@huawei.com>
Add has_caches flag to SMPCompatProps, which helps in avoiding
extra checks for every single layer of caches in x86 (and ARM in
future).
Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Note: Picked from Alireza's series with the changes:
* Moved the flag to SMPCompatProps with a new name "has_caches".
This way, it remains consistent with the function and style of
"has_clusters" in SMPCompatProps.
* Dropped my previous TODO with the new flag.
---
Changes since Patch v2:
* Picked a new patch frome Alireza's ARM smp-cache series.
---
hw/core/machine-smp.c | 2 ++
include/hw/boards.h | 3 +++
target/i386/cpu.c | 11 +++++------
3 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c
index 640b2114b429..6ae7c4765402 100644
--- a/hw/core/machine-smp.c
+++ b/hw/core/machine-smp.c
@@ -324,6 +324,8 @@ bool machine_parse_smp_cache(MachineState *ms,
return false;
}
}
+
+ mc->smp_props.has_caches = true;
return true;
}
diff --git a/include/hw/boards.h b/include/hw/boards.h
index 192f78539a6e..e6680701eec3 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -156,6 +156,8 @@ typedef struct {
* @modules_supported - whether modules are supported by the machine
* @cache_supported - whether cache (l1d, l1i, l2 and l3) configuration are
* supported by the machine
+ * @has_caches - whether cache properties are explicitly specified in the
+ * user provided smp-cache configuration
*/
typedef struct {
bool prefer_sockets;
@@ -166,6 +168,7 @@ typedef struct {
bool drawers_supported;
bool modules_supported;
bool cache_supported[CACHE_LEVEL_AND_TYPE__MAX];
+ bool has_caches;
} SMPCompatProps;
/**
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b6e12b46c9cc..9a81402e71c4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7884,13 +7884,12 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
#ifndef CONFIG_USER_ONLY
MachineState *ms = MACHINE(qdev_get_machine());
+ MachineClass *mc = MACHINE_GET_CLASS(ms);
- /*
- * TODO: Add a SMPCompatProps.has_caches flag to avoid useless updates
- * if user didn't set smp_cache.
- */
- if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) {
- return;
+ if (mc->smp_props.has_caches) {
+ if (!x86_cpu_update_smp_cache_topo(ms, cpu, errp)) {
+ return;
+ }
}
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v4 1/9] i386/cpu: Don't enumerate the "invalid" CPU topology level
2024-10-22 13:51 ` [PATCH v4 1/9] i386/cpu: Don't enumerate the "invalid" CPU topology level Zhao Liu
@ 2024-10-22 14:43 ` Jonathan Cameron via
0 siblings, 0 replies; 16+ messages in thread
From: Jonathan Cameron via @ 2024-10-22 14:43 UTC (permalink / raw)
To: Zhao Liu
Cc: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
Michael S.Tsirkin , Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Sia Jee Heng, Alireza Sanaee, qemu-devel, kvm,
qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi
Resend. Claws-mail is still chewing up the to list for unknown reasons
and I forgot to fix it by hand.
On Tue, 22 Oct 2024 21:51:43 +0800
Zhao Liu <zhao1.liu@intel.com> wrote:
> In the follow-up change, the CPU topology enumeration will be moved to
> QAPI. And considerring "invalid" should not be exposed to QAPI as an
> unsettable item, so, as a preparation for future changes, remove
> "invalid" level from the current CPU topology enumeration structure
> and define it by a macro instead.
>
> Due to the removal of the enumeration of "invalid", bit 0 of
> CPUX86State.avail_cpu_topo bitmap will no longer correspond to "invalid"
> level, but will start at the SMT level. Therefore, to honor this change,
> update the encoding rule for CPUID[0x1F].
>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
The drop of the invalid level == 0 seems reasonable to me
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 5/9] hw/core: Add a helper to check the cache topology level
2024-10-22 13:51 ` [PATCH v4 5/9] hw/core: Add a helper to check the cache topology level Zhao Liu
@ 2024-10-22 14:44 ` Jonathan Cameron via
0 siblings, 0 replies; 16+ messages in thread
From: Jonathan Cameron via @ 2024-10-22 14:44 UTC (permalink / raw)
To: Zhao Liu
Cc: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
Michael S.Tsirkin , Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Sia Jee Heng, Alireza Sanaee, qemu-devel, kvm,
qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi
Resend. Claws-mail is still chewing up the to list for unknown reasons
and I forgot to fix it by hand.
On Tue, 22 Oct 2024 21:51:47 +0800
Zhao Liu <zhao1.liu@intel.com> wrote:
> Currently, we have no way to expose the arch-specific default cache
> model because the cache model is sometimes related to the CPU model
> (e.g., i386).
>
> Since the user might configure "default" level, any comparison with
> "default" is meaningless before the machine knows the specific level
> that "default" refers to.
>
> We can only check the correctness of the cache topology after the arch
> loads the user-configured cache model from MachineState.smp_cache and
> consumes the special "default" level by replacing it with the specific
> level.
>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Looks like useful sanity check code to me.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 0/9] Introduce SMP Cache Topology
2024-10-22 13:51 [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
` (8 preceding siblings ...)
2024-10-22 13:51 ` [PATCH v4 9/9] i386/cpu: add has_caches flag to check smp_cache configuration Zhao Liu
@ 2024-10-28 9:07 ` Zhao Liu
9 siblings, 0 replies; 16+ messages in thread
From: Zhao Liu @ 2024-10-28 9:07 UTC (permalink / raw)
To: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Philippe Mathieu-Daudé, Yanan Wang,
Michael S . Tsirkin, Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Jonathan Cameron, Sia Jee Heng, Alireza Sanaee
Cc: qemu-devel, kvm, qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi
Kindly Ping.
(Hi miantainers, all the patches have received Jonathan's review. Could
this series be accepted?)
Thanks,
Zhao
On Tue, Oct 22, 2024 at 09:51:42PM +0800, Zhao Liu wrote:
> Date: Tue, 22 Oct 2024 21:51:42 +0800
> From: Zhao Liu <zhao1.liu@intel.com>
> Subject: [PATCH v4 0/9] Introduce SMP Cache Topology
> X-Mailer: git-send-email 2.34.1
>
> Hi all,
>
> Compared with v3 [1], the v4 mainly changes these places:
>
> * Don't expose "invalid" enumeration in QAPI and define it by a
> macro instead. (new patch 1, and updated patch 2)
>
> * Check cache topology after the arch machine loads the user-
> configured cache model from MachineState.smp_cache and consumes
> the special "default" level by replacing it with the specific level.
> (new patch 5, and updated patch 7)
>
> * Describ the omitting cache will use "default" level and describ
> the default cache topology model of i386 PC machine. (updated
> patch 8)
>
> All the above changes are tested and the interface design has remained
> stable.
>
> Meanwhile, ARM side has also worked a lot on the smp-cache based on
> this series [2].
>
> This series is based on the commit cc5adbbd50d8 ("Merge tag
> 'pull-tpm-2024-10-18-1' of https://github.com/stefanberger/qemu-tpm into
> staging").
>
> Welcome your feedback, and I appreciate your reviews. Hope our series
> can catch up with the 9.2 cycle. :)
>
>
> Background
> ==========
>
> The x86 and ARM (RISCV) need to allow user to configure cache properties
> (current only topology):
> * For x86, the default cache topology model (of max/host CPU) does not
> always match the Host's real physical cache topology. Performance can
> increase when the configured virtual topology is closer to the
> physical topology than a default topology would be.
> * For ARM, QEMU can't get the cache topology information from the CPU
> registers, then user configuration is necessary. Additionally, the
> cache information is also needed for MPAM emulation (for TCG) to
> build the right PPTT. (Originally from Jonathan)
>
>
> About smp-cache
> ===============
>
> The API design has been discussed heavily in [3].
>
> Now, smp-cache is implemented as a array integrated in -machine. Though
> -machine currently can't support JSON format, this is the one of the
> directions of future.
>
> An example is as follows:
>
> smp_cache=smp-cache.0.cache=l1i,smp-cache.0.topology=core,smp-cache.1.cache=l1d,smp-cache.1.topology=core,smp-cache.2.cache=l2,smp-cache.2.topology=module,smp-cache.3.cache=l3,smp-cache.3.topology=die
>
> "cache" specifies the cache that the properties will be applied on. This
> field is the combination of cache level and cache type. Now it supports
> "l1d" (L1 data cache), "l1i" (L1 instruction cache), "l2" (L2 unified
> cache) and "l3" (L3 unified cache).
>
> "topology" field accepts CPU topology levels including "thread", "core",
> "module", "cluster", "die", "socket", "book", "drawer" and a special
> value "default".
>
> The "default" is introduced to make it easier for libvirt to set a
> default parameter value without having to care about the specific
> machine (because currently there is no proper way for machine to
> expose supported topology levels and caches).
>
> If "default" is set, then the cache topology will follow the
> architecture's default cache topology model. If other CPU topology level
> is set, the cache will be shared at corresponding CPU topology level.
>
> Welcome your feedback and review!
>
> [1]: Patch v3: https://lore.kernel.org/qemu-devel/20241012104429.1048908-1-zhao1.liu@intel.com/
> [2]: ARM smp-cache: https://lore.kernel.org/qemu-devel/20241010111822.345-1-alireza.sanaee@huawei.com/
> [3]: API disscussion: https://lore.kernel.org/qemu-devel/8734ndj33j.fsf@pond.sub.org/
>
> Thanks and Best Regards,
> Zhao
> ---
> Changelog:
>
> Main changes since Patch v3:
> * Stopped exposing "invalid" enumeration in QAPI and define it by a
> macro instead. (Dainel)
> * Checked cache topology after the arch machine loads the
> user-configured cache model from MachineState.smp_cache and consumes
> the special "default" level by replacing it with the specific level.
> (Daniel)
> * Described the omitting cache will use "default" level and described
> the default cache topology model of i386 PC machine. (Daniel)
>
> Main changes since Patch v2:
> * Updated version of new QAPI structures to v9.2. (Jonathan)
> * Merged the QAPI change and smp-cache property support of machine
> into one commit. (Jonathan)
> * Picked Alireza's patch to add a has_caches flag.
> * Polished english and coding style. (Jonathan)
>
> Main changes since Patch v1:
> * Dropped handwriten smp-cache object and integrated cache properties
> list into MachineState and used -machine to configure SMP cache
> properties. (Markus)
> * Dropped prefix of CpuTopologyLevel enumeration. (Markus)
> * Rename CPU_TOPO_LEVEL_* to CPU_TOPOLOGY_LEVEL_* to match the QAPI's
> generated code. (Markus)
> * Renamed SMPCacheProperty/SMPCacheProperties (QAPI structures) to
> SmpCacheProperties/SmpCachePropertiesWrapper. (Markus)
> * Renamed SMPCacheName (QAPI structure) to SmpCacheLevelAndType and
> dropped prefix. (Markus)
> * Renamed 'name' field in SmpCacheProperties to 'cache', since the
> type and level of the cache in SMP system could be able to specify
> all of these kinds of cache explicitly enough.
> * Renamed 'topo' field in SmpCacheProperties to 'topology'. (Markus)
> * Returned error information when user repeats setting cache
> properties. (Markus)
> * Renamed SmpCacheLevelAndType to CacheLevelAndType, since this
> representation is general across SMP or hybrid system.
> * Dropped machine_check_smp_cache_support() and did the check when
> -machine parses smp-cache in machine_parse_smp_cache().
>
> Main changes since RFC v2:
> * Dropped cpu-topology.h and cpu-topology.c since QAPI has the helper
> (CpuTopologyLevel_str) to convert enum to string. (Markus)
> * Fixed text format in machine.json (CpuTopologyLevel naming, 2 spaces
> between sentences). (Markus)
> * Added a new level "default" to de-compatibilize some arch-specific
> topo settings. (Daniel)
> * Moved CpuTopologyLevel to qapi/machine-common.json, at where the
> cache enumeration and smp-cache object would be added.
> - If smp-cache object is defined in qapi/machine.json, storage-daemon
> will complain about the qmp cmds in qapi/machine.json during
> compiling.
> * Referred to Daniel's suggestion to introduce cache JSON list, though
> as a standalone object since -smp/-machine can't support JSON.
> * Linked machine's smp_cache to smp-cache object instead of a builtin
> structure. This is to get around the fact that the keyval format of
> -machine can't support JSON.
> * Wrapped the cache topology level access into a helper.
> * Split as a separate commit to just include compatibility checking and
> topology checking.
> * Allow setting "default" topology level even though the cache
> isn't supported by machine. (Daniel)
> * Rewrote the document of smp-cache object.
>
> Main changes since RFC v1:
> * Split CpuTopology renaimg out of this RFC.
> * Use QAPI to enumerate CPU topology levels.
> * Drop string_to_cpu_topo() since QAPI will help to parse the topo
> levels.
> * Set has_*_cache field in machine_get_smp(). (JeeHeng)
> * Use "*_cache=topo_level" as -smp example as the original "level"
> term for a cache has a totally different meaning. (Jonathan)
> ---
> Alireza Sanaee (1):
> i386/cpu: add has_caches flag to check smp_cache configuration
>
> Zhao Liu (8):
> i386/cpu: Don't enumerate the "invalid" CPU topology level
> hw/core: Make CPU topology enumeration arch-agnostic
> qapi/qom: Define cache enumeration and properties for machine
> hw/core: Check smp cache topology support for machine
> hw/core: Add a helper to check the cache topology level
> i386/cpu: Support thread and module level cache topology
> i386/cpu: Update cache topology with machine's configuration
> i386/pc: Support cache topology in -machine for PC machine
>
> hw/core/machine-smp.c | 128 +++++++++++++++++++++
> hw/core/machine.c | 44 ++++++++
> hw/i386/pc.c | 4 +
> hw/i386/x86-common.c | 4 +-
> include/hw/boards.h | 19 ++++
> include/hw/i386/topology.h | 22 +---
> qapi/machine-common.json | 94 +++++++++++++++-
> qemu-options.hx | 31 ++++-
> target/i386/cpu.c | 225 ++++++++++++++++++++++++-------------
> target/i386/cpu.h | 4 +-
> 10 files changed, 474 insertions(+), 101 deletions(-)
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 2/9] hw/core: Make CPU topology enumeration arch-agnostic
2024-10-22 13:51 ` [PATCH v4 2/9] hw/core: Make CPU topology enumeration arch-agnostic Zhao Liu
@ 2024-10-29 20:10 ` Philippe Mathieu-Daudé
2024-11-01 2:38 ` Zhao Liu
0 siblings, 1 reply; 16+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-29 20:10 UTC (permalink / raw)
To: Zhao Liu, Daniel P . Berrangé, Igor Mammedov,
Eduardo Habkost, Marcel Apfelbaum, Yanan Wang,
Michael S . Tsirkin, Paolo Bonzini, Richard Henderson, Eric Blake,
Markus Armbruster, Marcelo Tosatti, Alex Bennée,
Peter Maydell, Jonathan Cameron, Sia Jee Heng, Alireza Sanaee
Cc: qemu-devel, kvm, qemu-riscv, qemu-arm, Zhenyu Wang, Dapeng Mi,
Yongwei Ma
On 22/10/24 10:51, Zhao Liu wrote:
> Cache topology needs to be defined based on CPU topology levels. Thus,
> define CPU topology enumeration in qapi/machine.json to make it generic
> for all architectures.
>
> To match the general topology naming style, rename CPU_TOPO_LEVEL_* to
> CPU_TOPOLOGY_LEVEL_*, and rename SMT and package levels to thread and
> socket.
>
> Also, enumerate additional topology levels for non-i386 arches, and add
> a CPU_TOPOLOGY_LEVEL_DEFAULT to help future smp-cache object to work
> with compatibility requirement of arch-specific cache topology models.
>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> Tested-by: Yongwei Ma <yongwei.ma@intel.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> Changes since Patch v3:
> * Dropped "invalid" level to avoid an unsettable option. (Daniel)
> ---
> hw/i386/x86-common.c | 4 +-
> include/hw/i386/topology.h | 23 ++----
> qapi/machine-common.json | 44 +++++++++++-
> target/i386/cpu.c | 144 ++++++++++++++++++-------------------
> target/i386/cpu.h | 4 +-
> 5 files changed, 123 insertions(+), 96 deletions(-)
>
> diff --git a/hw/i386/x86-common.c b/hw/i386/x86-common.c
> index b86c38212eab..bc360a9ea44b 100644
> --- a/hw/i386/x86-common.c
> +++ b/hw/i386/x86-common.c
> @@ -273,12 +273,12 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
>
> if (ms->smp.modules > 1) {
> env->nr_modules = ms->smp.modules;
> - set_bit(CPU_TOPO_LEVEL_MODULE, env->avail_cpu_topo);
> + set_bit(CPU_TOPOLOGY_LEVEL_MODULE, env->avail_cpu_topo);
> }
>
> if (ms->smp.dies > 1) {
> env->nr_dies = ms->smp.dies;
> - set_bit(CPU_TOPO_LEVEL_DIE, env->avail_cpu_topo);
> + set_bit(CPU_TOPOLOGY_LEVEL_DIE, env->avail_cpu_topo);
> }
>
> /*
> diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h
> index 48b43edc5a90..b2c8bf2de158 100644
> --- a/include/hw/i386/topology.h
> +++ b/include/hw/i386/topology.h
> @@ -39,7 +39,7 @@
> * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width().
> */
>
> -
> +#include "qapi/qapi-types-machine-common.h"
> #include "qemu/bitops.h"
>
> /*
> @@ -62,22 +62,7 @@ typedef struct X86CPUTopoInfo {
> unsigned threads_per_core;
> } X86CPUTopoInfo;
>
> -#define CPU_TOPO_LEVEL_INVALID CPU_TOPO_LEVEL_MAX
> -
> -/*
> - * CPUTopoLevel is the general i386 topology hierarchical representation,
> - * ordered by increasing hierarchical relationship.
> - * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F])
> - * or AMD (CPUID[0x80000026]).
> - */
> -enum CPUTopoLevel {
> - CPU_TOPO_LEVEL_SMT,
> - CPU_TOPO_LEVEL_CORE,
> - CPU_TOPO_LEVEL_MODULE,
> - CPU_TOPO_LEVEL_DIE,
> - CPU_TOPO_LEVEL_PACKAGE,
> - CPU_TOPO_LEVEL_MAX,
> -};
> +#define CPU_TOPOLOGY_LEVEL_INVALID CPU_TOPOLOGY_LEVEL__MAX
> @@ -341,18 +341,18 @@ static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info,
> return 0;
> }
>
> -static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level)
> +static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level)
> {
> switch (topo_level) {
> - case CPU_TOPO_LEVEL_INVALID:
> + case CPU_TOPOLOGY_LEVEL_INVALID:
Since we use an enum, I'd rather directly use CPU_TOPOLOGY_LEVEL__MAX.
Or maybe in this case ...
> return CPUID_1F_ECX_TOPO_LEVEL_INVALID;
> - case CPU_TOPO_LEVEL_SMT:
> + case CPU_TOPOLOGY_LEVEL_THREAD:
> return CPUID_1F_ECX_TOPO_LEVEL_SMT;
> - case CPU_TOPO_LEVEL_CORE:
> + case CPU_TOPOLOGY_LEVEL_CORE:
> return CPUID_1F_ECX_TOPO_LEVEL_CORE;
> - case CPU_TOPO_LEVEL_MODULE:
> + case CPU_TOPOLOGY_LEVEL_MODULE:
> return CPUID_1F_ECX_TOPO_LEVEL_MODULE;
> - case CPU_TOPO_LEVEL_DIE:
> + case CPU_TOPOLOGY_LEVEL_DIE:
> return CPUID_1F_ECX_TOPO_LEVEL_DIE;
> default:
/* Other types are not supported in QEMU. */
g_assert_not_reached();
... return CPUID_1F_ECX_TOPO_LEVEL_INVALID as default.
Can be cleaned on top, so:
Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 2/9] hw/core: Make CPU topology enumeration arch-agnostic
2024-10-29 20:10 ` Philippe Mathieu-Daudé
@ 2024-11-01 2:38 ` Zhao Liu
2024-11-01 7:47 ` Zhao Liu
0 siblings, 1 reply; 16+ messages in thread
From: Zhao Liu @ 2024-11-01 2:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Daniel P . Berrangé, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Yanan Wang, Michael S . Tsirkin, Paolo Bonzini,
Richard Henderson, Eric Blake, Markus Armbruster, Marcelo Tosatti,
Alex Bennée, Peter Maydell, Jonathan Cameron, Sia Jee Heng,
Alireza Sanaee, qemu-devel, kvm, qemu-riscv, qemu-arm,
Zhenyu Wang, Dapeng Mi, Yongwei Ma
Hi Phil,
> > -static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level)
> > +static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level)
> > {
> > switch (topo_level) {
> > - case CPU_TOPO_LEVEL_INVALID:
> > + case CPU_TOPOLOGY_LEVEL_INVALID:
>
> Since we use an enum, I'd rather directly use CPU_TOPOLOGY_LEVEL__MAX.
>
> Or maybe in this case ...
>
> > return CPUID_1F_ECX_TOPO_LEVEL_INVALID;
> > - case CPU_TOPO_LEVEL_SMT:
> > + case CPU_TOPOLOGY_LEVEL_THREAD:
> > return CPUID_1F_ECX_TOPO_LEVEL_SMT;
> > - case CPU_TOPO_LEVEL_CORE:
> > + case CPU_TOPOLOGY_LEVEL_CORE:
> > return CPUID_1F_ECX_TOPO_LEVEL_CORE;
> > - case CPU_TOPO_LEVEL_MODULE:
> > + case CPU_TOPOLOGY_LEVEL_MODULE:
> > return CPUID_1F_ECX_TOPO_LEVEL_MODULE;
> > - case CPU_TOPO_LEVEL_DIE:
> > + case CPU_TOPOLOGY_LEVEL_DIE:
> > return CPUID_1F_ECX_TOPO_LEVEL_DIE;
> > default:
> /* Other types are not supported in QEMU. */
> g_assert_not_reached();
>
> ... return CPUID_1F_ECX_TOPO_LEVEL_INVALID as default.
I prefer the first way you mentioned since I want "default" to keep
to detact unimplemented levels.
> Can be cleaned on top, so:
Yes, I'll rebase (now there's the conflict) with this fixed.
> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Thanks!
Regards,
Zhao
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 2/9] hw/core: Make CPU topology enumeration arch-agnostic
2024-11-01 2:38 ` Zhao Liu
@ 2024-11-01 7:47 ` Zhao Liu
0 siblings, 0 replies; 16+ messages in thread
From: Zhao Liu @ 2024-11-01 7:47 UTC (permalink / raw)
To: Philippe Mathieu-Daud�
Cc: Daniel P . Berrang�, Igor Mammedov, Eduardo Habkost,
Marcel Apfelbaum, Yanan Wang, Michael S . Tsirkin, Paolo Bonzini,
Richard Henderson, Eric Blake, Markus Armbruster, Marcelo Tosatti,
Alex Benn�e, Peter Maydell, Jonathan Cameron, Sia Jee Heng,
Alireza Sanaee, qemu-devel, kvm, qemu-riscv, qemu-arm,
Zhenyu Wang, Dapeng Mi
On Fri, Nov 01, 2024 at 10:38:56AM +0800, Zhao Liu wrote:
> Date: Fri, 1 Nov 2024 10:38:56 +0800
> From: Zhao Liu <zhao1.liu@intel.com>
> Subject: Re: [PATCH v4 2/9] hw/core: Make CPU topology enumeration
> arch-agnostic
>
> Hi Phil,
>
> > > -static uint32_t cpuid1f_topo_type(enum CPUTopoLevel topo_level)
> > > +static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level)
> > > {
> > > switch (topo_level) {
> > > - case CPU_TOPO_LEVEL_INVALID:
> > > + case CPU_TOPOLOGY_LEVEL_INVALID:
> >
> > Since we use an enum, I'd rather directly use CPU_TOPOLOGY_LEVEL__MAX.
> >
> > Or maybe in this case ...
> >
> > > return CPUID_1F_ECX_TOPO_LEVEL_INVALID;
> > > - case CPU_TOPO_LEVEL_SMT:
> > > + case CPU_TOPOLOGY_LEVEL_THREAD:
> > > return CPUID_1F_ECX_TOPO_LEVEL_SMT;
> > > - case CPU_TOPO_LEVEL_CORE:
> > > + case CPU_TOPOLOGY_LEVEL_CORE:
> > > return CPUID_1F_ECX_TOPO_LEVEL_CORE;
> > > - case CPU_TOPO_LEVEL_MODULE:
> > > + case CPU_TOPOLOGY_LEVEL_MODULE:
> > > return CPUID_1F_ECX_TOPO_LEVEL_MODULE;
> > > - case CPU_TOPO_LEVEL_DIE:
> > > + case CPU_TOPOLOGY_LEVEL_DIE:
> > > return CPUID_1F_ECX_TOPO_LEVEL_DIE;
> > > default:
> > /* Other types are not supported in QEMU. */
> > g_assert_not_reached();
> >
> > ... return CPUID_1F_ECX_TOPO_LEVEL_INVALID as default.
>
> I prefer the first way you mentioned since I want "default" to keep
> to detact unimplemented levels.
>
Ah, when I started working on it, I realized that clearing
CPU_TOPOLOGY_LEVEL_INVALID would reduce the readability of the
encode_topo_cpuid1f(). The encoding rules for the 0x1f leaf are somewhat
complex, so I want the topology (and names) in encode_topo_cpuid1f() to
be as consistent with the spec as possible. Therefore, I will keep this
name! :)
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2024-11-01 7:31 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-22 13:51 [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
2024-10-22 13:51 ` [PATCH v4 1/9] i386/cpu: Don't enumerate the "invalid" CPU topology level Zhao Liu
2024-10-22 14:43 ` Jonathan Cameron via
2024-10-22 13:51 ` [PATCH v4 2/9] hw/core: Make CPU topology enumeration arch-agnostic Zhao Liu
2024-10-29 20:10 ` Philippe Mathieu-Daudé
2024-11-01 2:38 ` Zhao Liu
2024-11-01 7:47 ` Zhao Liu
2024-10-22 13:51 ` [PATCH v4 3/9] qapi/qom: Define cache enumeration and properties for machine Zhao Liu
2024-10-22 13:51 ` [PATCH v4 4/9] hw/core: Check smp cache topology support " Zhao Liu
2024-10-22 13:51 ` [PATCH v4 5/9] hw/core: Add a helper to check the cache topology level Zhao Liu
2024-10-22 14:44 ` Jonathan Cameron via
2024-10-22 13:51 ` [PATCH v4 6/9] i386/cpu: Support thread and module level cache topology Zhao Liu
2024-10-22 13:51 ` [PATCH v4 7/9] i386/cpu: Update cache topology with machine's configuration Zhao Liu
2024-10-22 13:51 ` [PATCH v4 8/9] i386/pc: Support cache topology in -machine for PC machine Zhao Liu
2024-10-22 13:51 ` [PATCH v4 9/9] i386/cpu: add has_caches flag to check smp_cache configuration Zhao Liu
2024-10-28 9:07 ` [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).