From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Zhao Liu <zhao1.liu@intel.com>
Cc: "Daniel P . Berrangé" <berrange@redhat.com>,
"Igor Mammedov" <imammedo@redhat.com>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Michael S.Tsirkin " <mst@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Eric Blake" <eblake@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Sia Jee Heng" <jeeheng.sia@starfivetech.com>,
"Alireza Sanaee" <alireza.sanaee@huawei.com>,
qemu-devel@nongnu.org, kvm@vger.kernel.org,
qemu-riscv@nongnu.org, qemu-arm@nongnu.org,
"Zhenyu Wang" <zhenyu.z.wang@intel.com>,
"Dapeng Mi" <dapeng1.mi@linux.intel.com>
Subject: Re: [PATCH v4 1/9] i386/cpu: Don't enumerate the "invalid" CPU topology level
Date: Tue, 22 Oct 2024 15:43:52 +0100 [thread overview]
Message-ID: <20241022154352.00001a4e@Huawei.com> (raw)
In-Reply-To: <20241022135151.2052198-2-zhao1.liu@intel.com>
Resend. Claws-mail is still chewing up the to list for unknown reasons
and I forgot to fix it by hand.
On Tue, 22 Oct 2024 21:51:43 +0800
Zhao Liu <zhao1.liu@intel.com> wrote:
> In the follow-up change, the CPU topology enumeration will be moved to
> QAPI. And considerring "invalid" should not be exposed to QAPI as an
> unsettable item, so, as a preparation for future changes, remove
> "invalid" level from the current CPU topology enumeration structure
> and define it by a macro instead.
>
> Due to the removal of the enumeration of "invalid", bit 0 of
> CPUX86State.avail_cpu_topo bitmap will no longer correspond to "invalid"
> level, but will start at the SMT level. Therefore, to honor this change,
> update the encoding rule for CPUID[0x1F].
>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
The drop of the invalid level == 0 seems reasonable to me
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
next prev parent reply other threads:[~2024-10-22 14:44 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-22 13:51 [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
2024-10-22 13:51 ` [PATCH v4 1/9] i386/cpu: Don't enumerate the "invalid" CPU topology level Zhao Liu
2024-10-22 14:43 ` Jonathan Cameron via [this message]
2024-10-22 13:51 ` [PATCH v4 2/9] hw/core: Make CPU topology enumeration arch-agnostic Zhao Liu
2024-10-29 20:10 ` Philippe Mathieu-Daudé
2024-11-01 2:38 ` Zhao Liu
2024-11-01 7:47 ` Zhao Liu
2024-10-22 13:51 ` [PATCH v4 3/9] qapi/qom: Define cache enumeration and properties for machine Zhao Liu
2024-10-22 13:51 ` [PATCH v4 4/9] hw/core: Check smp cache topology support " Zhao Liu
2024-10-22 13:51 ` [PATCH v4 5/9] hw/core: Add a helper to check the cache topology level Zhao Liu
2024-10-22 14:44 ` Jonathan Cameron via
2024-10-22 13:51 ` [PATCH v4 6/9] i386/cpu: Support thread and module level cache topology Zhao Liu
2024-10-22 13:51 ` [PATCH v4 7/9] i386/cpu: Update cache topology with machine's configuration Zhao Liu
2024-10-22 13:51 ` [PATCH v4 8/9] i386/pc: Support cache topology in -machine for PC machine Zhao Liu
2024-10-22 13:51 ` [PATCH v4 9/9] i386/cpu: add has_caches flag to check smp_cache configuration Zhao Liu
2024-10-28 9:07 ` [PATCH v4 0/9] Introduce SMP Cache Topology Zhao Liu
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