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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71ec13d73b1sm5438338b3a.105.2024.10.22.20.34.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2024 20:34:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: [PULL 00/24] tcg + linux-user patch queue Date: Tue, 22 Oct 2024 20:34:08 -0700 Message-ID: <20241023033432.1353830-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The following changes since commit 6f625ce2f21d6a1243065d236298277c56f972d5: Merge tag 'pull-request-2024-10-21' of https://gitlab.com/thuth/qemu into staging (2024-10-21 17:12:59 +0100) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20241022 for you to fetch changes up to 310df7a9fe400f32cde8a7edf80daad12cd9cf02: linux-user/riscv: Fix definition of RISCV_HWPROBE_EXT_ZVFHMIN (2024-10-22 13:45:03 -0700) ---------------------------------------------------------------- tcg: Reset data_gen_ptr correctly tcg/riscv: Implement host vector support tcg/ppc: Fix tcg_out_rlw_rc target/i386: Walk NPT in guest real mode target/i386: Use probe_access_full_mmu in ptw_translate linux-user: Fix build failure caused by missing __u64 on musl linux-user: Emulate /proc/self/maps under mmap_lock linux-user/riscv: Fix definition of RISCV_HWPROBE_EXT_ZVFHMIN linux-user/ppc: Fix sigmask endianness issue in sigreturn ---------------------------------------------------------------- Alexander Graf (1): target/i386: Walk NPT in guest real mode Dani Szebenyi (1): tcg/ppc: Fix tcg_out_rlw_rc Huang Shiyuan (1): tcg/riscv: Add basic support for vector Ilya Leoshkevich (3): linux-user: Emulate /proc/self/maps under mmap_lock linux-user/ppc: Fix sigmask endianness issue in sigreturn linux-user: Trace rt_sigprocmask's sigsets Richard Henderson (6): tcg: Reset data_gen_ptr correctly disas/riscv: Fix vsetivli disassembly tcg/riscv: Accept constant first argument to sub_vec include/exec: Improve probe_access_full{, _mmu} documentation target/i386: Use probe_access_full_mmu in ptw_translate target/i386: Remove ra parameter from ptw_translate TANG Tiancheng (10): util: Add RISC-V vector extension probe in cpuinfo tcg/riscv: Implement vector mov/dup{m/i} tcg/riscv: Add support for basic vector opcodes tcg/riscv: Implement vector cmp/cmpsel ops tcg/riscv: Implement vector neg ops tcg/riscv: Implement vector sat/mul ops tcg/riscv: Implement vector min/max ops tcg/riscv: Implement vector shi/s/v ops tcg/riscv: Implement vector roti/v/x ops tcg/riscv: Enable native vector support for TCG host Yao Zi (2): linux-user: Fix build failure caused by missing __u64 on musl linux-user/riscv: Fix definition of RISCV_HWPROBE_EXT_ZVFHMIN disas/riscv.h | 2 +- host/include/riscv/host/cpuinfo.h | 2 + include/exec/exec-all.h | 29 +- include/tcg/tcg.h | 6 + linux-user/syscall_defs.h | 6 +- tcg/riscv/tcg-target-con-set.h | 9 + tcg/riscv/tcg-target-con-str.h | 3 + tcg/riscv/tcg-target.h | 78 +-- tcg/riscv/tcg-target.opc.h | 12 + disas/riscv.c | 2 +- linux-user/ppc/signal.c | 2 +- linux-user/strace.c | 88 +++- linux-user/syscall.c | 6 +- target/i386/tcg/sysemu/excp_helper.c | 45 +- tcg/tcg.c | 2 +- util/cpuinfo-riscv.c | 34 +- linux-user/strace.list | 3 +- tcg/ppc/tcg-target.c.inc | 4 +- tcg/riscv/tcg-target.c.inc | 994 ++++++++++++++++++++++++++++++++--- 19 files changed, 1152 insertions(+), 175 deletions(-) create mode 100644 tcg/riscv/tcg-target.opc.h