* [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format
@ 2024-10-28 1:57 Sia Jee Heng
2024-10-28 1:57 ` [PATCH v6 1/3] qtest: allow SPCR acpi table changes Sia Jee Heng
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Sia Jee Heng @ 2024-10-28 1:57 UTC (permalink / raw)
To: qemu-arm, qemu-devel, qemu-riscv
Cc: mst, imammedo, anisinha, peter.maydell, jeeheng.sia,
shannon.zhaosl, sunilvl, palmer, alistair.francis, bin.meng,
liwei1518, dbarboza, zhiwei_liu, gaosong, jiaxun.yang, maobibo
Update the SPCR table to accommodate the SPCR Table revision 4 [1].
The SPCR table has been modified to adhere to the revision 4 format [2].
Meanwhile, the virt SPCR golden reference file for RISC-V have been updated to
accommodate the SPCR Table revision 4.
[1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
[2]: https://github.com/acpica/acpica/pull/931
Changes in v6:
- Added Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
- Rebase and update the build_spcr() function for the LoongArch virt machine.
Changes in v5:
- Reverted the SPCR table revision history for the ARM architecture.
- Corrected the output of the SPCR Table diff.
Changes in v4:
- Remove the SPCR table revision 4 update for the ARM architecture.
Changes in v3:
- Rebased on the latest QEMU.
- Added Acked-by: Alistair Francis <alistair.francis@wdc.com>
Changes in v2:
- Utilizes a three-patch approach to modify the ACPI pre-built binary
files required by the Bios-Table-Test.
- Rebases and incorporates changes to support both ARM and RISC-V ACPI
pre-built binary files.
Sia Jee Heng (3):
qtest: allow SPCR acpi table changes
hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4
format
tests/qtest/bios-tables-test: Update virt SPCR golden reference for
RISC-V
hw/acpi/aml-build.c | 20 ++++++++++++++++----
hw/arm/virt-acpi-build.c | 8 ++++++--
hw/loongarch/acpi-build.c | 6 +++++-
hw/riscv/virt-acpi-build.c | 12 +++++++++---
include/hw/acpi/acpi-defs.h | 7 +++++--
include/hw/acpi/aml-build.h | 2 +-
tests/data/acpi/riscv64/virt/SPCR | Bin 80 -> 90 bytes
7 files changed, 42 insertions(+), 13 deletions(-)
base-commit: cea8ac78545a83e1f01c94d89d6f5a3f6b5c05d2
--
2.43.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v6 1/3] qtest: allow SPCR acpi table changes
2024-10-28 1:57 [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format Sia Jee Heng
@ 2024-10-28 1:57 ` Sia Jee Heng
2024-10-28 1:57 ` [PATCH v6 2/3] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format Sia Jee Heng
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Sia Jee Heng @ 2024-10-28 1:57 UTC (permalink / raw)
To: qemu-arm, qemu-devel, qemu-riscv
Cc: mst, imammedo, anisinha, peter.maydell, jeeheng.sia,
shannon.zhaosl, sunilvl, palmer, alistair.francis, bin.meng,
liwei1518, dbarboza, zhiwei_liu, gaosong, jiaxun.yang, maobibo
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..aae973048a 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,2 @@
/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/riscv64/virt/SPCR",
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v6 2/3] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format
2024-10-28 1:57 [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format Sia Jee Heng
2024-10-28 1:57 ` [PATCH v6 1/3] qtest: allow SPCR acpi table changes Sia Jee Heng
@ 2024-10-28 1:57 ` Sia Jee Heng
2024-10-28 2:32 ` maobibo
2024-10-28 1:57 ` [PATCH v6 3/3] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V Sia Jee Heng
` (3 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Sia Jee Heng @ 2024-10-28 1:57 UTC (permalink / raw)
To: qemu-arm, qemu-devel, qemu-riscv
Cc: mst, imammedo, anisinha, peter.maydell, jeeheng.sia,
shannon.zhaosl, sunilvl, palmer, alistair.francis, bin.meng,
liwei1518, dbarboza, zhiwei_liu, gaosong, jiaxun.yang, maobibo
Update the SPCR table to accommodate the SPCR Table revision 4 [1].
The SPCR table has been modified to adhere to the revision 4 format [2].
[1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
[2]: https://github.com/acpica/acpica/pull/931
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/acpi/aml-build.c | 20 ++++++++++++++++----
hw/arm/virt-acpi-build.c | 8 ++++++--
hw/loongarch/acpi-build.c | 6 +++++-
hw/riscv/virt-acpi-build.c | 12 +++++++++---
include/hw/acpi/acpi-defs.h | 7 +++++--
include/hw/acpi/aml-build.h | 2 +-
6 files changed, 42 insertions(+), 13 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 34e0ddbde8..69c4bdfa22 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -1995,7 +1995,7 @@ static void build_processor_hierarchy_node(GArray *tbl, uint32_t flags,
void build_spcr(GArray *table_data, BIOSLinker *linker,
const AcpiSpcrData *f, const uint8_t rev,
- const char *oem_id, const char *oem_table_id)
+ const char *oem_id, const char *oem_table_id, const char *name)
{
AcpiTable table = { .sig = "SPCR", .rev = rev, .oem_id = oem_id,
.oem_table_id = oem_table_id };
@@ -2041,9 +2041,21 @@ void build_spcr(GArray *table_data, BIOSLinker *linker,
build_append_int_noprefix(table_data, f->pci_flags, 4);
/* PCI Segment */
build_append_int_noprefix(table_data, f->pci_segment, 1);
- /* Reserved */
- build_append_int_noprefix(table_data, 0, 4);
-
+ if (rev < 4) {
+ /* Reserved */
+ build_append_int_noprefix(table_data, 0, 4);
+ } else {
+ /* UartClkFreq */
+ build_append_int_noprefix(table_data, f->uart_clk_freq, 4);
+ /* PreciseBaudrate */
+ build_append_int_noprefix(table_data, f->precise_baudrate, 4);
+ /* NameSpaceStringLength */
+ build_append_int_noprefix(table_data, f->namespace_string_length, 2);
+ /* NameSpaceStringOffset */
+ build_append_int_noprefix(table_data, f->namespace_string_offset, 2);
+ /* NamespaceString[] */
+ g_array_append_vals(table_data, name, f->namespace_string_length);
+ }
acpi_table_end(linker, &table);
}
/*
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index f76fb117ad..0b6f5f8d8d 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -464,8 +464,12 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
.pci_flags = 0,
.pci_segment = 0,
};
-
- build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id);
+ /*
+ * Passing NULL as the SPCR Table for Revision 2 doesn't support
+ * NameSpaceString.
+ */
+ build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id,
+ NULL);
}
/*
diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
index 50709bda0f..4e04f7b6c1 100644
--- a/hw/loongarch/acpi-build.c
+++ b/hw/loongarch/acpi-build.c
@@ -276,8 +276,12 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, MachineState *machine)
};
lvms = LOONGARCH_VIRT_MACHINE(machine);
+ /*
+ * Passing NULL as the SPCR Table for Revision 2 doesn't support
+ * NameSpaceString.
+ */
build_spcr(table_data, linker, &serial, 2, lvms->oem_id,
- lvms->oem_table_id);
+ lvms->oem_table_id, NULL);
}
typedef
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index 36d6a3a412..68ef15acac 100644
--- a/hw/riscv/virt-acpi-build.c
+++ b/hw/riscv/virt-acpi-build.c
@@ -200,14 +200,15 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
/*
* Serial Port Console Redirection Table (SPCR)
- * Rev: 1.07
+ * Rev: 1.10
*/
static void
spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
{
+ const char name[] = ".";
AcpiSpcrData serial = {
- .interface_type = 0, /* 16550 compatible */
+ .interface_type = 0x12, /* 16550 compatible */
.base_addr.id = AML_AS_SYSTEM_MEMORY,
.base_addr.width = 32,
.base_addr.offset = 0,
@@ -229,9 +230,14 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
.pci_function = 0,
.pci_flags = 0,
.pci_segment = 0,
+ .uart_clk_freq = 0,
+ .precise_baudrate = 0,
+ .namespace_string_length = sizeof(name),
+ .namespace_string_offset = 88,
};
- build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id);
+ build_spcr(table_data, linker, &serial, 4, s->oem_id, s->oem_table_id,
+ name);
}
/* RHCT Node[N] starts at offset 56 */
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 0e6e82b339..2e6e341998 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -112,7 +112,6 @@ typedef struct AcpiSpcrData {
uint8_t flow_control;
uint8_t terminal_type;
uint8_t language;
- uint8_t reserved1;
uint16_t pci_device_id; /* Must be 0xffff if not PCI device */
uint16_t pci_vendor_id; /* Must be 0xffff if not PCI device */
uint8_t pci_bus;
@@ -120,7 +119,11 @@ typedef struct AcpiSpcrData {
uint8_t pci_function;
uint32_t pci_flags;
uint8_t pci_segment;
- uint32_t reserved2;
+ uint32_t uart_clk_freq;
+ uint32_t precise_baudrate;
+ uint32_t namespace_string_length;
+ uint32_t namespace_string_offset;
+ char namespace_string[];
} AcpiSpcrData;
#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index a3784155cb..68c0f2dbee 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -500,5 +500,5 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
void build_spcr(GArray *table_data, BIOSLinker *linker,
const AcpiSpcrData *f, const uint8_t rev,
- const char *oem_id, const char *oem_table_id);
+ const char *oem_id, const char *oem_table_id, const char *name);
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v6 3/3] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V
2024-10-28 1:57 [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format Sia Jee Heng
2024-10-28 1:57 ` [PATCH v6 1/3] qtest: allow SPCR acpi table changes Sia Jee Heng
2024-10-28 1:57 ` [PATCH v6 2/3] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format Sia Jee Heng
@ 2024-10-28 1:57 ` Sia Jee Heng
2024-10-28 15:48 ` [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format Peter Maydell
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Sia Jee Heng @ 2024-10-28 1:57 UTC (permalink / raw)
To: qemu-arm, qemu-devel, qemu-riscv
Cc: mst, imammedo, anisinha, peter.maydell, jeeheng.sia,
shannon.zhaosl, sunilvl, palmer, alistair.francis, bin.meng,
liwei1518, dbarboza, zhiwei_liu, gaosong, jiaxun.yang, maobibo
Update the virt SPCR golden reference file for RISC-V to accommodate the
SPCR Table revision 4 [1], utilizing the iasl binary compiled from the
latest ACPICA repository. The SPCR table has been modified to
adhere to the revision 4 format [2].
[1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
[2]: https://github.com/acpica/acpica/pull/931
Diffs from iasl:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/riscv64/virt/SPCR, Wed Aug 28 18:28:19 2024
+ * Disassembly of /tmp/aml-MN0NS2, Wed Aug 28 18:28:19 2024
*
* ACPI Data Table [SPCR]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table]
-[004h 0004 4] Table Length : 00000050
-[008h 0008 1] Revision : 02
-[009h 0009 1] Checksum : B9
+[004h 0004 4] Table Length : 0000005A
+[008h 0008 1] Revision : 04
+[009h 0009 1] Checksum : 13
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
-[024h 0036 1] Interface Type : 00
+[024h 0036 1] Interface Type : 12
[025h 0037 3] Reserved : 000000
[028h 0040 12] Serial Port Register : [Generic Address Structure]
[028h 0040 1] Space ID : 00 [SystemMemory]
[029h 0041 1] Bit Width : 20
[02Ah 0042 1] Bit Offset : 00
[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8]
[02Ch 0044 8] Address : 0000000010000000
[034h 0052 1] Interrupt Type : 10
[035h 0053 1] PCAT-compatible IRQ : 00
[036h 0054 4] Interrupt : 0000000A
[03Ah 0058 1] Baud Rate : 07
[03Bh 0059 1] Parity : 00
[03Ch 0060 1] Stop Bits : 01
[03Dh 0061 1] Flow Control : 00
[03Eh 0062 1] Terminal Type : 00
[04Ch 0076 1] Reserved : 00
[040h 0064 2] PCI Device ID : FFFF
[042h 0066 2] PCI Vendor ID : FFFF
[044h 0068 1] PCI Bus : 00
[045h 0069 1] PCI Device : 00
[046h 0070 1] PCI Function : 00
[047h 0071 4] PCI Flags : 00000000
[04Bh 0075 1] PCI Segment : 00
-[04Ch 0076 4] Reserved : 00000000
+[04Ch 0076 004h] Uart Clock Freq : 00000000
+[050h 0080 004h] Precise Baud rate : 00000000
+[054h 0084 002h] NameSpaceStringLength : 0002
+[056h 0086 002h] NameSpaceStringOffset : 0058
+[058h 0088 002h] NamespaceString : "."
-Raw Table Data: Length 80 (0x50)
+Raw Table Data: Length 90 (0x5A)
- 0000: 53 50 43 52 50 00 00 00 02 B9 42 4F 43 48 53 20 // SPCRP.....BOCHS
+ 0000: 53 50 43 52 5A 00 00 00 04 13 42 4F 43 48 53 20 // SPCRZ.....BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
- 0020: 01 00 00 00 00 00 00 00 00 20 00 01 00 00 00 10 // ......... ......
+ 0020: 01 00 00 00 12 00 00 00 00 20 00 01 00 00 00 10 // ......... ......
0030: 00 00 00 00 10 00 0A 00 00 00 07 00 01 00 00 03 // ................
0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 02 00 58 00 2E 00 // ......X...
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
---
tests/data/acpi/riscv64/virt/SPCR | Bin 80 -> 90 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1 deletion(-)
diff --git a/tests/data/acpi/riscv64/virt/SPCR b/tests/data/acpi/riscv64/virt/SPCR
index 4da9daf65f71a13ac2b488d4e9728f194b569a43..09617f8793a6f7b1f08172f735b58aa748671540 100644
GIT binary patch
delta 32
mcmWHD;tCFM4vJ!6U|<oR$R))nG*MNX3&>+&Vu)bSV*mhNumqU^
delta 21
ccmazF;0g|K4hmpkU|`xgkxPn^VWO%w05v59j{pDw
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index aae973048a..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,2 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/riscv64/virt/SPCR",
--
2.43.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v6 2/3] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format
2024-10-28 1:57 ` [PATCH v6 2/3] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format Sia Jee Heng
@ 2024-10-28 2:32 ` maobibo
0 siblings, 0 replies; 8+ messages in thread
From: maobibo @ 2024-10-28 2:32 UTC (permalink / raw)
To: Sia Jee Heng, qemu-arm, qemu-devel, qemu-riscv
Cc: mst, imammedo, anisinha, peter.maydell, shannon.zhaosl, sunilvl,
palmer, alistair.francis, bin.meng, liwei1518, dbarboza,
zhiwei_liu, gaosong, jiaxun.yang
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
On 2024/10/28 上午9:57, Sia Jee Heng wrote:
> Update the SPCR table to accommodate the SPCR Table revision 4 [1].
> The SPCR table has been modified to adhere to the revision 4 format [2].
>
> [1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
> [2]: https://github.com/acpica/acpica/pull/931
>
> Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/acpi/aml-build.c | 20 ++++++++++++++++----
> hw/arm/virt-acpi-build.c | 8 ++++++--
> hw/loongarch/acpi-build.c | 6 +++++-
> hw/riscv/virt-acpi-build.c | 12 +++++++++---
> include/hw/acpi/acpi-defs.h | 7 +++++--
> include/hw/acpi/aml-build.h | 2 +-
> 6 files changed, 42 insertions(+), 13 deletions(-)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 34e0ddbde8..69c4bdfa22 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -1995,7 +1995,7 @@ static void build_processor_hierarchy_node(GArray *tbl, uint32_t flags,
>
> void build_spcr(GArray *table_data, BIOSLinker *linker,
> const AcpiSpcrData *f, const uint8_t rev,
> - const char *oem_id, const char *oem_table_id)
> + const char *oem_id, const char *oem_table_id, const char *name)
> {
> AcpiTable table = { .sig = "SPCR", .rev = rev, .oem_id = oem_id,
> .oem_table_id = oem_table_id };
> @@ -2041,9 +2041,21 @@ void build_spcr(GArray *table_data, BIOSLinker *linker,
> build_append_int_noprefix(table_data, f->pci_flags, 4);
> /* PCI Segment */
> build_append_int_noprefix(table_data, f->pci_segment, 1);
> - /* Reserved */
> - build_append_int_noprefix(table_data, 0, 4);
> -
> + if (rev < 4) {
> + /* Reserved */
> + build_append_int_noprefix(table_data, 0, 4);
> + } else {
> + /* UartClkFreq */
> + build_append_int_noprefix(table_data, f->uart_clk_freq, 4);
> + /* PreciseBaudrate */
> + build_append_int_noprefix(table_data, f->precise_baudrate, 4);
> + /* NameSpaceStringLength */
> + build_append_int_noprefix(table_data, f->namespace_string_length, 2);
> + /* NameSpaceStringOffset */
> + build_append_int_noprefix(table_data, f->namespace_string_offset, 2);
> + /* NamespaceString[] */
> + g_array_append_vals(table_data, name, f->namespace_string_length);
> + }
> acpi_table_end(linker, &table);
> }
> /*
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index f76fb117ad..0b6f5f8d8d 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -464,8 +464,12 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
> .pci_flags = 0,
> .pci_segment = 0,
> };
> -
> - build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id);
> + /*
> + * Passing NULL as the SPCR Table for Revision 2 doesn't support
> + * NameSpaceString.
> + */
> + build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id,
> + NULL);
> }
>
> /*
> diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c
> index 50709bda0f..4e04f7b6c1 100644
> --- a/hw/loongarch/acpi-build.c
> +++ b/hw/loongarch/acpi-build.c
> @@ -276,8 +276,12 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, MachineState *machine)
> };
>
> lvms = LOONGARCH_VIRT_MACHINE(machine);
> + /*
> + * Passing NULL as the SPCR Table for Revision 2 doesn't support
> + * NameSpaceString.
> + */
> build_spcr(table_data, linker, &serial, 2, lvms->oem_id,
> - lvms->oem_table_id);
> + lvms->oem_table_id, NULL);
> }
>
> typedef
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 36d6a3a412..68ef15acac 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -200,14 +200,15 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
>
> /*
> * Serial Port Console Redirection Table (SPCR)
> - * Rev: 1.07
> + * Rev: 1.10
> */
>
> static void
> spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
> {
> + const char name[] = ".";
> AcpiSpcrData serial = {
> - .interface_type = 0, /* 16550 compatible */
> + .interface_type = 0x12, /* 16550 compatible */
> .base_addr.id = AML_AS_SYSTEM_MEMORY,
> .base_addr.width = 32,
> .base_addr.offset = 0,
> @@ -229,9 +230,14 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s)
> .pci_function = 0,
> .pci_flags = 0,
> .pci_segment = 0,
> + .uart_clk_freq = 0,
> + .precise_baudrate = 0,
> + .namespace_string_length = sizeof(name),
> + .namespace_string_offset = 88,
> };
>
> - build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id);
> + build_spcr(table_data, linker, &serial, 4, s->oem_id, s->oem_table_id,
> + name);
> }
>
> /* RHCT Node[N] starts at offset 56 */
> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
> index 0e6e82b339..2e6e341998 100644
> --- a/include/hw/acpi/acpi-defs.h
> +++ b/include/hw/acpi/acpi-defs.h
> @@ -112,7 +112,6 @@ typedef struct AcpiSpcrData {
> uint8_t flow_control;
> uint8_t terminal_type;
> uint8_t language;
> - uint8_t reserved1;
> uint16_t pci_device_id; /* Must be 0xffff if not PCI device */
> uint16_t pci_vendor_id; /* Must be 0xffff if not PCI device */
> uint8_t pci_bus;
> @@ -120,7 +119,11 @@ typedef struct AcpiSpcrData {
> uint8_t pci_function;
> uint32_t pci_flags;
> uint8_t pci_segment;
> - uint32_t reserved2;
> + uint32_t uart_clk_freq;
> + uint32_t precise_baudrate;
> + uint32_t namespace_string_length;
> + uint32_t namespace_string_offset;
> + char namespace_string[];
> } AcpiSpcrData;
>
> #define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index a3784155cb..68c0f2dbee 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -500,5 +500,5 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
>
> void build_spcr(GArray *table_data, BIOSLinker *linker,
> const AcpiSpcrData *f, const uint8_t rev,
> - const char *oem_id, const char *oem_table_id);
> + const char *oem_id, const char *oem_table_id, const char *name);
> #endif
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format
2024-10-28 1:57 [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format Sia Jee Heng
` (2 preceding siblings ...)
2024-10-28 1:57 ` [PATCH v6 3/3] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V Sia Jee Heng
@ 2024-10-28 15:48 ` Peter Maydell
2024-12-02 1:30 ` JeeHeng Sia
2024-12-03 6:34 ` Alistair Francis
5 siblings, 0 replies; 8+ messages in thread
From: Peter Maydell @ 2024-10-28 15:48 UTC (permalink / raw)
To: Sia Jee Heng
Cc: qemu-arm, qemu-devel, qemu-riscv, mst, imammedo, anisinha,
shannon.zhaosl, sunilvl, palmer, alistair.francis, bin.meng,
liwei1518, dbarboza, zhiwei_liu, gaosong, jiaxun.yang, maobibo
On Mon, 28 Oct 2024 at 01:58, Sia Jee Heng <jeeheng.sia@starfivetech.com> wrote:
>
> Update the SPCR table to accommodate the SPCR Table revision 4 [1].
> The SPCR table has been modified to adhere to the revision 4 format [2].
>
> Meanwhile, the virt SPCR golden reference file for RISC-V have been updated to
> accommodate the SPCR Table revision 4.
>
> [1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
> [2]: https://github.com/acpica/acpica/pull/931
>
> Changes in v6:
> - Added Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> - Rebase and update the build_spcr() function for the LoongArch virt machine.
>
> Changes in v5:
> - Reverted the SPCR table revision history for the ARM architecture.
> - Corrected the output of the SPCR Table diff.
>
> Changes in v4:
> - Remove the SPCR table revision 4 update for the ARM architecture.
>
> Changes in v3:
> - Rebased on the latest QEMU.
> - Added Acked-by: Alistair Francis <alistair.francis@wdc.com>
>
> Changes in v2:
> - Utilizes a three-patch approach to modify the ACPI pre-built binary
> files required by the Bios-Table-Test.
> - Rebases and incorporates changes to support both ARM and RISC-V ACPI
> pre-built binary files.
>
> Sia Jee Heng (3):
> qtest: allow SPCR acpi table changes
> hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4
> format
> tests/qtest/bios-tables-test: Update virt SPCR golden reference for
> RISC-V
>
> hw/acpi/aml-build.c | 20 ++++++++++++++++----
> hw/arm/virt-acpi-build.c | 8 ++++++--
> hw/loongarch/acpi-build.c | 6 +++++-
> hw/riscv/virt-acpi-build.c | 12 +++++++++---
> include/hw/acpi/acpi-defs.h | 7 +++++--
> include/hw/acpi/aml-build.h | 2 +-
> tests/data/acpi/riscv64/virt/SPCR | Bin 80 -> 90 bytes
> 7 files changed, 42 insertions(+), 13 deletions(-)
Since this seems to be for the benefit largely of
riscv I'm assuming this will go via the riscv tree.
thanks
-- PMM
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format
2024-10-28 1:57 [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format Sia Jee Heng
` (3 preceding siblings ...)
2024-10-28 15:48 ` [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format Peter Maydell
@ 2024-12-02 1:30 ` JeeHeng Sia
2024-12-03 6:34 ` Alistair Francis
5 siblings, 0 replies; 8+ messages in thread
From: JeeHeng Sia @ 2024-12-02 1:30 UTC (permalink / raw)
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: mst@redhat.com, imammedo@redhat.com, anisinha@redhat.com,
peter.maydell@linaro.org, shannon.zhaosl@gmail.com,
sunilvl@ventanamicro.com, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, gaosong@loongson.cn,
jiaxun.yang@flygoat.com, maobibo@loongson.cn
> -----Original Message-----
> From: JeeHeng Sia <jeeheng.sia@starfivetech.com>
> Sent: Monday, 28 October, 2024 9:58 AM
> To: qemu-arm@nongnu.org; qemu-devel@nongnu.org; qemu-riscv@nongnu.org
> Cc: mst@redhat.com; imammedo@redhat.com; anisinha@redhat.com; peter.maydell@linaro.org; JeeHeng Sia
> <jeeheng.sia@starfivetech.com>; shannon.zhaosl@gmail.com; sunilvl@ventanamicro.com; palmer@dabbelt.com;
> alistair.francis@wdc.com; bin.meng@windriver.com; liwei1518@gmail.com; dbarboza@ventanamicro.com;
> zhiwei_liu@linux.alibaba.com; gaosong@loongson.cn; jiaxun.yang@flygoat.com; maobibo@loongson.cn
> Subject: [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format
>
> Update the SPCR table to accommodate the SPCR Table revision 4 [1].
> The SPCR table has been modified to adhere to the revision 4 format [2].
>
> Meanwhile, the virt SPCR golden reference file for RISC-V have been updated to
> accommodate the SPCR Table revision 4.
>
> [1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
> [2]: https://github.com/acpica/acpica/pull/931
>
> Changes in v6:
> - Added Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> - Rebase and update the build_spcr() function for the LoongArch virt machine.
>
> Changes in v5:
> - Reverted the SPCR table revision history for the ARM architecture.
> - Corrected the output of the SPCR Table diff.
>
> Changes in v4:
> - Remove the SPCR table revision 4 update for the ARM architecture.
>
> Changes in v3:
> - Rebased on the latest QEMU.
> - Added Acked-by: Alistair Francis <alistair.francis@wdc.com>
>
> Changes in v2:
> - Utilizes a three-patch approach to modify the ACPI pre-built binary
> files required by the Bios-Table-Test.
> - Rebases and incorporates changes to support both ARM and RISC-V ACPI
> pre-built binary files.
>
> Sia Jee Heng (3):
> qtest: allow SPCR acpi table changes
> hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4
> format
> tests/qtest/bios-tables-test: Update virt SPCR golden reference for
> RISC-V
>
> hw/acpi/aml-build.c | 20 ++++++++++++++++----
> hw/arm/virt-acpi-build.c | 8 ++++++--
> hw/loongarch/acpi-build.c | 6 +++++-
> hw/riscv/virt-acpi-build.c | 12 +++++++++---
> include/hw/acpi/acpi-defs.h | 7 +++++--
> include/hw/acpi/aml-build.h | 2 +-
> tests/data/acpi/riscv64/virt/SPCR | Bin 80 -> 90 bytes
> 7 files changed, 42 insertions(+), 13 deletions(-)
>
Hi Alistair,
These patches were submitted last month, and there are no further review comments from others.
May I know if there are any concerns about merging the patch series?
>
> base-commit: cea8ac78545a83e1f01c94d89d6f5a3f6b5c05d2
> --
> 2.43.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format
2024-10-28 1:57 [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format Sia Jee Heng
` (4 preceding siblings ...)
2024-12-02 1:30 ` JeeHeng Sia
@ 2024-12-03 6:34 ` Alistair Francis
5 siblings, 0 replies; 8+ messages in thread
From: Alistair Francis @ 2024-12-03 6:34 UTC (permalink / raw)
To: Sia Jee Heng
Cc: qemu-arm, qemu-devel, qemu-riscv, mst, imammedo, anisinha,
peter.maydell, shannon.zhaosl, sunilvl, palmer, alistair.francis,
bin.meng, liwei1518, dbarboza, zhiwei_liu, gaosong, jiaxun.yang,
maobibo
On Mon, Oct 28, 2024 at 10:59 AM Sia Jee Heng
<jeeheng.sia@starfivetech.com> wrote:
>
> Update the SPCR table to accommodate the SPCR Table revision 4 [1].
> The SPCR table has been modified to adhere to the revision 4 format [2].
>
> Meanwhile, the virt SPCR golden reference file for RISC-V have been updated to
> accommodate the SPCR Table revision 4.
>
> [1]: https://learn.microsoft.com/en-us/windows-hardware/drivers/serports/serial-port-console-redirection-table
> [2]: https://github.com/acpica/acpica/pull/931
>
> Changes in v6:
> - Added Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> - Rebase and update the build_spcr() function for the LoongArch virt machine.
>
> Changes in v5:
> - Reverted the SPCR table revision history for the ARM architecture.
> - Corrected the output of the SPCR Table diff.
>
> Changes in v4:
> - Remove the SPCR table revision 4 update for the ARM architecture.
>
> Changes in v3:
> - Rebased on the latest QEMU.
> - Added Acked-by: Alistair Francis <alistair.francis@wdc.com>
>
> Changes in v2:
> - Utilizes a three-patch approach to modify the ACPI pre-built binary
> files required by the Bios-Table-Test.
> - Rebases and incorporates changes to support both ARM and RISC-V ACPI
> pre-built binary files.
>
> Sia Jee Heng (3):
> qtest: allow SPCR acpi table changes
> hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4
> format
> tests/qtest/bios-tables-test: Update virt SPCR golden reference for
> RISC-V
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> hw/acpi/aml-build.c | 20 ++++++++++++++++----
> hw/arm/virt-acpi-build.c | 8 ++++++--
> hw/loongarch/acpi-build.c | 6 +++++-
> hw/riscv/virt-acpi-build.c | 12 +++++++++---
> include/hw/acpi/acpi-defs.h | 7 +++++--
> include/hw/acpi/aml-build.h | 2 +-
> tests/data/acpi/riscv64/virt/SPCR | Bin 80 -> 90 bytes
> 7 files changed, 42 insertions(+), 13 deletions(-)
>
>
> base-commit: cea8ac78545a83e1f01c94d89d6f5a3f6b5c05d2
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-12-03 6:35 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-10-28 1:57 [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format Sia Jee Heng
2024-10-28 1:57 ` [PATCH v6 1/3] qtest: allow SPCR acpi table changes Sia Jee Heng
2024-10-28 1:57 ` [PATCH v6 2/3] hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format Sia Jee Heng
2024-10-28 2:32 ` maobibo
2024-10-28 1:57 ` [PATCH v6 3/3] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V Sia Jee Heng
2024-10-28 15:48 ` [PATCH v6 0/3] Upgrade ACPI SPCR table to support SPCR table revision 4 format Peter Maydell
2024-12-02 1:30 ` JeeHeng Sia
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