* [PATCH v2 1/1] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation
@ 2024-10-29 8:53 Yong-Xuan Wang
2024-11-18 6:48 ` Alistair Francis
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Yong-Xuan Wang @ 2024-10-29 8:53 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: greentime.hu, vincent.chen, frank.chang, jim.shu, Yong-Xuan Wang,
Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
In the section "4.7 Precise effects on interrupt-pending bits"
of the RISC-V AIA specification defines that:
"If the source mode is Level1 or Level0 and the interrupt domain
is configured in MSI delivery mode (domaincfg.DM = 1):
The pending bit is cleared whenever the rectified input value is
low, when the interrupt is forwarded by MSI, or by a relevant
write to an in_clrip register or to clripnum."
Update the riscv_aplic_set_pending() to match the spec.
Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode")
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
---
v2:
- add fixes tag (Daniel)
- follow the suggestion from https://lore.kernel.org/kvm/CAAhSdy3NmwbHY9Qef9LUeXfr0iE7wC-u0d_fHzC47PXk-MzmRg@mail.gmail.com/
(Anup)
---
hw/intc/riscv_aplic.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 4a262c82f078..74c82a841101 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -248,9 +248,12 @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
(sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
- if (!aplic->msimode || (aplic->msimode && !pending)) {
+ if (!aplic->msimode) {
return;
}
+ if (aplic->msimode && !pending) {
+ goto noskip_write_pending;
+ }
if ((aplic->state[irq] & APLIC_ISTATE_INPUT) &&
(sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
return;
@@ -261,6 +264,7 @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
}
}
+noskip_write_pending:
riscv_aplic_set_pending_raw(aplic, irq, pending);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/1] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation
2024-10-29 8:53 [PATCH v2 1/1] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation Yong-Xuan Wang
@ 2024-11-18 6:48 ` Alistair Francis
2024-11-19 1:17 ` Alistair Francis
2024-12-22 8:38 ` Michael Tokarev
2 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2024-11-18 6:48 UTC (permalink / raw)
To: Yong-Xuan Wang
Cc: qemu-devel, qemu-riscv, greentime.hu, vincent.chen, frank.chang,
jim.shu, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
On Tue, Oct 29, 2024 at 6:54 PM Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote:
>
> In the section "4.7 Precise effects on interrupt-pending bits"
> of the RISC-V AIA specification defines that:
>
> "If the source mode is Level1 or Level0 and the interrupt domain
> is configured in MSI delivery mode (domaincfg.DM = 1):
> The pending bit is cleared whenever the rectified input value is
> low, when the interrupt is forwarded by MSI, or by a relevant
> write to an in_clrip register or to clripnum."
>
> Update the riscv_aplic_set_pending() to match the spec.
>
> Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode")
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> v2:
> - add fixes tag (Daniel)
> - follow the suggestion from https://lore.kernel.org/kvm/CAAhSdy3NmwbHY9Qef9LUeXfr0iE7wC-u0d_fHzC47PXk-MzmRg@mail.gmail.com/
> (Anup)
> ---
> hw/intc/riscv_aplic.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index 4a262c82f078..74c82a841101 100644
> --- a/hw/intc/riscv_aplic.c
> +++ b/hw/intc/riscv_aplic.c
> @@ -248,9 +248,12 @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
>
> if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
> (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
> - if (!aplic->msimode || (aplic->msimode && !pending)) {
> + if (!aplic->msimode) {
> return;
> }
> + if (aplic->msimode && !pending) {
> + goto noskip_write_pending;
> + }
> if ((aplic->state[irq] & APLIC_ISTATE_INPUT) &&
> (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
> return;
> @@ -261,6 +264,7 @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
> }
> }
>
> +noskip_write_pending:
> riscv_aplic_set_pending_raw(aplic, irq, pending);
> }
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/1] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation
2024-10-29 8:53 [PATCH v2 1/1] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation Yong-Xuan Wang
2024-11-18 6:48 ` Alistair Francis
@ 2024-11-19 1:17 ` Alistair Francis
2024-12-22 8:38 ` Michael Tokarev
2 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2024-11-19 1:17 UTC (permalink / raw)
To: Yong-Xuan Wang
Cc: qemu-devel, qemu-riscv, greentime.hu, vincent.chen, frank.chang,
jim.shu, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
On Tue, Oct 29, 2024 at 6:54 PM Yong-Xuan Wang <yongxuan.wang@sifive.com> wrote:
>
> In the section "4.7 Precise effects on interrupt-pending bits"
> of the RISC-V AIA specification defines that:
>
> "If the source mode is Level1 or Level0 and the interrupt domain
> is configured in MSI delivery mode (domaincfg.DM = 1):
> The pending bit is cleared whenever the rectified input value is
> low, when the interrupt is forwarded by MSI, or by a relevant
> write to an in_clrip register or to clripnum."
>
> Update the riscv_aplic_set_pending() to match the spec.
>
> Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode")
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> v2:
> - add fixes tag (Daniel)
> - follow the suggestion from https://lore.kernel.org/kvm/CAAhSdy3NmwbHY9Qef9LUeXfr0iE7wC-u0d_fHzC47PXk-MzmRg@mail.gmail.com/
> (Anup)
> ---
> hw/intc/riscv_aplic.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
> index 4a262c82f078..74c82a841101 100644
> --- a/hw/intc/riscv_aplic.c
> +++ b/hw/intc/riscv_aplic.c
> @@ -248,9 +248,12 @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
>
> if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) ||
> (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
> - if (!aplic->msimode || (aplic->msimode && !pending)) {
> + if (!aplic->msimode) {
> return;
> }
> + if (aplic->msimode && !pending) {
> + goto noskip_write_pending;
> + }
> if ((aplic->state[irq] & APLIC_ISTATE_INPUT) &&
> (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) {
> return;
> @@ -261,6 +264,7 @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic,
> }
> }
>
> +noskip_write_pending:
> riscv_aplic_set_pending_raw(aplic, irq, pending);
> }
>
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/1] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation
2024-10-29 8:53 [PATCH v2 1/1] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation Yong-Xuan Wang
2024-11-18 6:48 ` Alistair Francis
2024-11-19 1:17 ` Alistair Francis
@ 2024-12-22 8:38 ` Michael Tokarev
2025-01-02 0:34 ` Alistair Francis
2 siblings, 1 reply; 5+ messages in thread
From: Michael Tokarev @ 2024-12-22 8:38 UTC (permalink / raw)
To: Yong-Xuan Wang, qemu-devel, qemu-riscv
Cc: greentime.hu, vincent.chen, frank.chang, jim.shu, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza,
Liu Zhiwei, qemu-stable
29.10.2024 11:53, Yong-Xuan Wang wrote:
> In the section "4.7 Precise effects on interrupt-pending bits"
> of the RISC-V AIA specification defines that:
>
> "If the source mode is Level1 or Level0 and the interrupt domain
> is configured in MSI delivery mode (domaincfg.DM = 1):
> The pending bit is cleared whenever the rectified input value is
> low, when the interrupt is forwarded by MSI, or by a relevant
> write to an in_clrip register or to clripnum."
>
> Update the riscv_aplic_set_pending() to match the spec.
>
> Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode")
Is it a qemu-stable material?
Thanks,
/mjt
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/1] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation
2024-12-22 8:38 ` Michael Tokarev
@ 2025-01-02 0:34 ` Alistair Francis
0 siblings, 0 replies; 5+ messages in thread
From: Alistair Francis @ 2025-01-02 0:34 UTC (permalink / raw)
To: Michael Tokarev
Cc: Yong-Xuan Wang, qemu-devel, qemu-riscv, greentime.hu,
vincent.chen, frank.chang, jim.shu, Palmer Dabbelt,
Alistair Francis, Bin Meng, Weiwei Li, Daniel Henrique Barboza,
Liu Zhiwei, qemu-stable
On Sun, Dec 22, 2024 at 6:40 PM Michael Tokarev <mjt@tls.msk.ru> wrote:
>
> 29.10.2024 11:53, Yong-Xuan Wang wrote:
> > In the section "4.7 Precise effects on interrupt-pending bits"
> > of the RISC-V AIA specification defines that:
> >
> > "If the source mode is Level1 or Level0 and the interrupt domain
> > is configured in MSI delivery mode (domaincfg.DM = 1):
> > The pending bit is cleared whenever the rectified input value is
> > low, when the interrupt is forwarded by MSI, or by a relevant
> > write to an in_clrip register or to clripnum."
> >
> > Update the riscv_aplic_set_pending() to match the spec.
> >
> > Fixes: bf31cf06eb ("hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC MSI-mode")
>
> Is it a qemu-stable material?
Yes, I think it should be
Alistair
>
> Thanks,
>
> /mjt
>
^ permalink raw reply [flat|nested] 5+ messages in thread
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2024-10-29 8:53 [PATCH v2 1/1] hw/intc/riscv_aplic: Fix APLIC in_clrip and clripnum write emulation Yong-Xuan Wang
2024-11-18 6:48 ` Alistair Francis
2024-11-19 1:17 ` Alistair Francis
2024-12-22 8:38 ` Michael Tokarev
2025-01-02 0:34 ` Alistair Francis
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