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From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Bin Meng" <bmeng.cn@gmail.com>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>,
	"open list:SD (Secure Card)" <qemu-block@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
	<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 2/8] hw/timer/aspeed: Fix coding style
Date: Tue, 29 Oct 2024 17:17:23 +0800	[thread overview]
Message-ID: <20241029091729.3317512-3-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20241029091729.3317512-1-jamin_lin@aspeedtech.com>

Fix coding style issues from checkpatch.pl

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/timer/aspeed_timer.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index b1f860ecfb..5af268ea9e 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -276,7 +276,8 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
         old_reload = t->reload;
         t->reload = calculate_min_ticks(t, value);
 
-        /* If the reload value was not previously set, or zero, and
+        /*
+         * If the reload value was not previously set, or zero, and
          * the current value is valid, try to start the timer if it is
          * enabled.
          */
@@ -312,7 +313,8 @@ static void aspeed_timer_set_value(AspeedTimerCtrlState *s, int timer, int reg,
     }
 }
 
-/* Control register operations are broken out into helpers that can be
+/*
+ * Control register operations are broken out into helpers that can be
  * explicitly called on aspeed_timer_reset(), but also from
  * aspeed_timer_ctrl_op().
  */
@@ -396,7 +398,8 @@ static void aspeed_timer_set_ctrl(AspeedTimerCtrlState *s, uint32_t reg)
     AspeedTimer *t;
     const uint8_t enable_mask = BIT(op_enable);
 
-    /* Handle a dependency between the 'enable' and remaining three
+    /*
+     * Handle a dependency between the 'enable' and remaining three
      * configuration bits - i.e. if more than one bit in the control set has
      * changed, including the 'enable' bit, then we want either disable the
      * timer and perform configuration, or perform configuration and then
@@ -582,7 +585,6 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
     case 0x3C:
         aspeed_timer_set_ctrl(s, s->ctrl & ~tv);
         break;
-
     case 0x38:
     default:
         qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
@@ -623,7 +625,8 @@ static void aspeed_timer_reset(DeviceState *dev)
 
     for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
         AspeedTimer *t = &s->timers[i];
-        /* Explicitly call helpers to avoid any conditional behaviour through
+        /*
+         * Explicitly call helpers to avoid any conditional behaviour through
          * aspeed_timer_set_ctrl().
          */
         aspeed_timer_ctrl_enable(t, false);
-- 
2.34.1



  parent reply	other threads:[~2024-10-29  9:18 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-29  9:17 [PATCH v1 0/8] Support RTC for AST2700 Jamin Lin via
2024-10-29  9:17 ` [PATCH v1 1/8] aspeed/soc: " Jamin Lin via
2024-11-02 14:59   ` [SPAM] " Cédric Le Goater
2024-10-29  9:17 ` Jamin Lin via [this message]
2024-11-02 15:01   ` [SPAM] [PATCH v1 2/8] hw/timer/aspeed: Fix coding style Cédric Le Goater
2024-10-29  9:17 ` [PATCH v1 3/8] hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600 Jamin Lin via
2024-10-29 23:43   ` Andrew Jeffery
2024-11-02 14:59   ` [SPAM] " Cédric Le Goater
2024-10-29  9:17 ` [PATCH v1 4/8] hw/sd/sdhci: Fix coding style Jamin Lin via
2024-11-02 15:00   ` [SPAM] " Cédric Le Goater
2024-10-29  9:17 ` [PATCH v1 5/8] hw/sd/sdhci: Introduce a new Write Protected pin inverted property Jamin Lin via
2024-10-29 23:50   ` Andrew Jeffery
2024-10-30  2:10     ` Jamin Lin
2024-10-29  9:17 ` [PATCH v1 6/8] hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1 Jamin Lin via
2024-11-02 15:02   ` [SPAM] " Cédric Le Goater
2024-11-04 10:28   ` Philippe Mathieu-Daudé
2024-10-29  9:17 ` [PATCH v1 7/8] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 and AST2500 EVBs Jamin Lin via
2024-10-30  0:20   ` Andrew Jeffery
2024-10-30  2:31     ` Jamin Lin
2024-10-29  9:17 ` [PATCH v1 8/8] aspeed: Support create flash devices via command line for AST1030 Jamin Lin via
2024-11-02 15:02   ` [SPAM] " Cédric Le Goater
2024-11-02 15:03 ` [SPAM] [PATCH v1 0/8] Support RTC for AST2700 Cédric Le Goater
2024-11-04  1:16   ` Jamin Lin

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