From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Bin Meng" <bmeng.cn@gmail.com>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
"open list:SD (Secure Card)" <qemu-block@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
<yunlin.tang@aspeedtech.com>
Subject: [PATCH v1 5/8] hw/sd/sdhci: Introduce a new Write Protected pin inverted property
Date: Tue, 29 Oct 2024 17:17:26 +0800 [thread overview]
Message-ID: <20241029091729.3317512-6-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20241029091729.3317512-1-jamin_lin@aspeedtech.com>
The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24). However, some board are
design Write Protected pin active high. In other words, write enable the bit 19
should be 0 and write protected the bit 19 should be 1 at the
Present State Register (0x24). To support it, introduces a new "wp_invert"
property and set it false by default.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/sd/sdhci.c | 6 ++++++
include/hw/sd/sdhci.h | 5 +++++
2 files changed, 11 insertions(+)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index db7d547156..bdf5cbfb80 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -275,6 +275,10 @@ static void sdhci_set_readonly(DeviceState *dev, bool level)
{
SDHCIState *s = (SDHCIState *)dev;
+ if (s->wp_invert) {
+ level = !level;
+ }
+
if (level) {
s->prnsts &= ~SDHC_WRITE_PROTECT;
} else {
@@ -1551,6 +1555,8 @@ static Property sdhci_sysbus_properties[] = {
false),
DEFINE_PROP_LINK("dma", SDHCIState,
dma_mr, TYPE_MEMORY_REGION, MemoryRegion *),
+ DEFINE_PROP_BOOL("wp-invert", SDHCIState,
+ wp_invert, false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 6cd2822f1d..d68f4788e7 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -100,6 +100,11 @@ struct SDHCIState {
uint8_t sd_spec_version;
uint8_t uhs_mode;
uint8_t vendor; /* For vendor specific functionality */
+ /*
+ * Write Protect pin default active low for detecting SD card
+ * to be protected. Set wp_invert to true inverted the signal.
+ */
+ bool wp_invert;
};
typedef struct SDHCIState SDHCIState;
--
2.34.1
next prev parent reply other threads:[~2024-10-29 9:19 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-29 9:17 [PATCH v1 0/8] Support RTC for AST2700 Jamin Lin via
2024-10-29 9:17 ` [PATCH v1 1/8] aspeed/soc: " Jamin Lin via
2024-11-02 14:59 ` [SPAM] " Cédric Le Goater
2024-10-29 9:17 ` [PATCH v1 2/8] hw/timer/aspeed: Fix coding style Jamin Lin via
2024-11-02 15:01 ` [SPAM] " Cédric Le Goater
2024-10-29 9:17 ` [PATCH v1 3/8] hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600 Jamin Lin via
2024-10-29 23:43 ` Andrew Jeffery
2024-11-02 14:59 ` [SPAM] " Cédric Le Goater
2024-10-29 9:17 ` [PATCH v1 4/8] hw/sd/sdhci: Fix coding style Jamin Lin via
2024-11-02 15:00 ` [SPAM] " Cédric Le Goater
2024-10-29 9:17 ` Jamin Lin via [this message]
2024-10-29 23:50 ` [PATCH v1 5/8] hw/sd/sdhci: Introduce a new Write Protected pin inverted property Andrew Jeffery
2024-10-30 2:10 ` Jamin Lin
2024-10-29 9:17 ` [PATCH v1 6/8] hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1 Jamin Lin via
2024-11-02 15:02 ` [SPAM] " Cédric Le Goater
2024-11-04 10:28 ` Philippe Mathieu-Daudé
2024-10-29 9:17 ` [PATCH v1 7/8] hw/arm/aspeed: Invert sdhci write protected pin for AST2600 and AST2500 EVBs Jamin Lin via
2024-10-30 0:20 ` Andrew Jeffery
2024-10-30 2:31 ` Jamin Lin
2024-10-29 9:17 ` [PATCH v1 8/8] aspeed: Support create flash devices via command line for AST1030 Jamin Lin via
2024-11-02 15:02 ` [SPAM] " Cédric Le Goater
2024-11-02 15:03 ` [SPAM] [PATCH v1 0/8] Support RTC for AST2700 Cédric Le Goater
2024-11-04 1:16 ` Jamin Lin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20241029091729.3317512-6-jamin_lin@aspeedtech.com \
--to=qemu-devel@nongnu.org \
--cc=andrew@codeconstruct.com.au \
--cc=bmeng.cn@gmail.com \
--cc=clg@kaod.org \
--cc=jamin_lin@aspeedtech.com \
--cc=joel@jms.id.au \
--cc=leetroy@gmail.com \
--cc=peter.maydell@linaro.org \
--cc=philmd@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-block@nongnu.org \
--cc=steven_lee@aspeedtech.com \
--cc=troy_lee@aspeedtech.com \
--cc=yunlin.tang@aspeedtech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).