From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Sergey Makarov <s.makarov@syntacore.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 11/50] hw/intc: Don't clear pending bits on IRQ lowering
Date: Thu, 31 Oct 2024 13:52:39 +1000 [thread overview]
Message-ID: <20241031035319.731906-12-alistair.francis@wdc.com> (raw)
In-Reply-To: <20241031035319.731906-1-alistair.francis@wdc.com>
From: Sergey Makarov <s.makarov@syntacore.com>
According to PLIC specification (chapter 5), there
is only one case, when interrupt is claimed. Fix
PLIC controller to match this behavior.
Signed-off-by: Sergey Makarov <s.makarov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240918140229.124329-3-s.makarov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/sifive_plic.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 8de3a654bc..ed74490dba 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -354,8 +354,10 @@ static void sifive_plic_irq_request(void *opaque, int irq, int level)
{
SiFivePLICState *s = opaque;
- sifive_plic_set_pending(s, irq, level > 0);
- sifive_plic_update(s);
+ if (level > 0) {
+ sifive_plic_set_pending(s, irq, true);
+ sifive_plic_update(s);
+ }
}
static void sifive_plic_realize(DeviceState *dev, Error **errp)
--
2.47.0
next prev parent reply other threads:[~2024-10-31 4:01 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-31 3:52 [PULL 00/50] riscv-to-apply queue Alistair Francis
2024-10-31 3:52 ` [PULL 01/50] target/riscv/csr.c: Fix an access to VXSAT Alistair Francis
2024-10-31 3:52 ` [PULL 02/50] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI Alistair Francis
2024-10-31 3:52 ` [PULL 03/50] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 Alistair Francis
2024-10-31 3:52 ` [PULL 04/50] target/riscv: Correct SXL return value for RV32 in RV64 QEMU Alistair Francis
2024-11-05 7:27 ` Michael Tokarev
2024-11-05 23:44 ` Alistair Francis
2024-10-31 3:52 ` [PULL 05/50] target/riscv: Detect sxl to set bit width for RV32 in RV64 Alistair Francis
2024-10-31 3:52 ` [PULL 06/50] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU Alistair Francis
2024-10-31 3:52 ` [PULL 07/50] target/riscv: Enable RV32 CPU support " Alistair Francis
2024-10-31 3:52 ` [PULL 08/50] target/riscv: Add max32 CPU for " Alistair Francis
2024-10-31 3:52 ` [PULL 09/50] tests/avocado: Boot Linux for RV32 cpu on " Alistair Francis
2024-10-31 3:52 ` [PULL 10/50] hw/intc: Make zeroth priority register read-only Alistair Francis
2024-10-31 3:52 ` Alistair Francis [this message]
2024-10-31 3:52 ` [PULL 12/50] target/riscv: Set vtype.vill on CPU reset Alistair Francis
2024-10-31 3:52 ` [PULL 13/50] hw/intc/riscv_aplic: Check and update pending when write sourcecfg Alistair Francis
2024-10-31 3:52 ` [PULL 14/50] hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all Alistair Francis
2024-10-31 3:52 ` [PULL 15/50] hw/char: sifive_uart: Print uart characters async Alistair Francis
2024-11-04 14:38 ` Thomas Huth
2024-11-04 15:25 ` Philippe Mathieu-Daudé
2025-02-14 12:52 ` Clément Chigot
2025-02-21 15:26 ` Clément Chigot
2025-02-24 4:37 ` Alistair Francis
2025-02-24 10:52 ` Clément Chigot
2024-10-31 3:52 ` [PULL 16/50] target/riscv: expose *envcfg csr and priv to qemu-user as well Alistair Francis
2024-10-31 3:52 ` [PULL 17/50] target/riscv: Add zicfilp extension Alistair Francis
2024-10-31 3:52 ` [PULL 18/50] target/riscv: Introduce elp state and enabling controls for zicfilp Alistair Francis
2024-10-31 3:52 ` [PULL 19/50] target/riscv: save and restore elp state on priv transitions Alistair Francis
2024-10-31 3:52 ` [PULL 20/50] target/riscv: additional code information for sw check Alistair Francis
2024-10-31 3:52 ` [PULL 21/50] target/riscv: tracking indirect branches (fcfi) for zicfilp Alistair Francis
2024-10-31 3:52 ` [PULL 22/50] target/riscv: zicfilp `lpad` impl and branch tracking Alistair Francis
2024-10-31 3:52 ` [PULL 23/50] disas/riscv: enable `lpad` disassembly Alistair Francis
2024-10-31 3:52 ` [PULL 24/50] target/riscv: Expose zicfilp extension as a cpu property Alistair Francis
2024-10-31 3:52 ` [PULL 25/50] target/riscv: Add zicfiss extension Alistair Francis
2024-10-31 3:52 ` [PULL 26/50] target/riscv: introduce ssp and enabling controls for zicfiss Alistair Francis
2024-10-31 3:52 ` [PULL 27/50] target/riscv: tb flag for shadow stack instructions Alistair Francis
2024-10-31 3:52 ` [PULL 28/50] target/riscv: mmu changes for zicfiss shadow stack protection Alistair Francis
2024-10-31 3:52 ` [PULL 29/50] target/riscv: AMO operations always raise store/AMO fault Alistair Francis
2024-10-31 3:52 ` [PULL 30/50] target/riscv: update `decode_save_opc` to store extra word2 Alistair Francis
2024-10-31 3:52 ` [PULL 31/50] target/riscv: implement zicfiss instructions Alistair Francis
2024-10-31 3:53 ` [PULL 32/50] target/riscv: compressed encodings for sspush and sspopchk Alistair Francis
2024-10-31 3:53 ` [PULL 33/50] disas/riscv: enable disassembly for zicfiss instructions Alistair Francis
2024-10-31 3:53 ` [PULL 34/50] disas/riscv: enable disassembly for compressed sspush/sspopchk Alistair Francis
2024-10-31 3:53 ` [PULL 35/50] target/riscv: Expose zicfiss extension as a cpu property Alistair Francis
2024-10-31 3:53 ` [PULL 36/50] exec/memtxattr: add process identifier to the transaction attributes Alistair Francis
2024-10-31 3:53 ` [PULL 37/50] hw/riscv: add riscv-iommu-bits.h Alistair Francis
2024-10-31 3:53 ` [PULL 38/50] hw/riscv: add RISC-V IOMMU base emulation Alistair Francis
2024-10-31 3:53 ` [PULL 39/50] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device Alistair Francis
2024-10-31 3:53 ` [PULL 40/50] hw/riscv: add riscv-iommu-pci reference device Alistair Francis
2024-10-31 3:53 ` [PULL 41/50] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug Alistair Francis
2024-10-31 3:53 ` [PULL 42/50] test/qtest: add riscv-iommu-pci tests Alistair Francis
2024-10-31 3:53 ` [PULL 43/50] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) Alistair Francis
2024-10-31 3:53 ` [PULL 44/50] hw/riscv/riscv-iommu: add ATS support Alistair Francis
2024-10-31 3:53 ` [PULL 45/50] hw/riscv/riscv-iommu: add DBG support Alistair Francis
2024-10-31 3:53 ` [PULL 46/50] qtest/riscv-iommu-test: add init queues test Alistair Francis
2024-10-31 3:53 ` [PULL 47/50] docs/specs: add riscv-iommu Alistair Francis
2024-10-31 3:53 ` [PULL 48/50] target/riscv/kvm: set 'aia_mode' to default in error path Alistair Francis
2024-10-31 3:53 ` [PULL 49/50] target/riscv/kvm: clarify how 'riscv-aia' default works Alistair Francis
2024-10-31 3:53 ` [PULL 50/50] target/riscv: Fix vcompress with rvv_ta_all_1s Alistair Francis
2024-11-01 9:58 ` [PULL 00/50] riscv-to-apply queue Peter Maydell
2024-11-01 13:39 ` Michael Tokarev
2024-11-04 17:55 ` Daniel Henrique Barboza
2024-11-04 22:57 ` Alistair Francis
2024-11-05 7:45 ` Michael Tokarev
2024-11-05 7:55 ` Michael Tokarev
2024-11-05 23:50 ` Alistair Francis
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