From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Deepak Gupta <debug@rivosinc.com>,
Jim Shu <jim.shu@sifive.com>, Andy Chiu <andy.chiu@sifive.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 18/50] target/riscv: Introduce elp state and enabling controls for zicfilp
Date: Thu, 31 Oct 2024 13:52:46 +1000 [thread overview]
Message-ID: <20241031035319.731906-19-alistair.francis@wdc.com> (raw)
In-Reply-To: <20241031035319.731906-1-alistair.francis@wdc.com>
From: Deepak Gupta <debug@rivosinc.com>
zicfilp introduces a new state elp ("expected landing pad") in cpu.
During normal execution, elp is idle (NO_LP_EXPECTED) i.e not expecting
landing pad. On an indirect call, elp moves LP_EXPECTED. When elp is
LP_EXPECTED, only a subsquent landing pad instruction can set state back
to NO_LP_EXPECTED. On reset, elp is set to NO_LP_EXPECTED.
zicfilp is enabled via bit2 in *envcfg CSRs. Enabling control for M-mode
is in mseccfg CSR at bit position 10.
On trap, elp state is saved away in *status.
Adds elp to the migration state as well.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-4-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h | 6 ++++++
target/riscv/pmp.h | 3 ++-
target/riscv/cpu.c | 3 +++
target/riscv/csr.c | 31 +++++++++++++++++++++++++++++++
target/riscv/machine.c | 19 +++++++++++++++++++
target/riscv/pmp.c | 5 +++++
7 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b7b082833d..d68cb6e9e0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -230,6 +230,8 @@ struct CPUArchState {
target_ulong jvt;
+ /* elp state for zicfilp extension */
+ bool elp;
#ifdef CONFIG_USER_ONLY
uint32_t elf_flags;
#endif
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7e3f629356..8df6043ef1 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -552,6 +552,8 @@
#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
#define MSTATUS_TW 0x00200000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */
+#define MSTATUS_SPELP 0x00800000 /* zicfilp */
+#define MSTATUS_MPELP 0x020000000000 /* zicfilp */
#define MSTATUS_GVA 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL
@@ -582,6 +584,7 @@ typedef enum {
#define SSTATUS_XS 0x00018000
#define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */
#define SSTATUS_MXR 0x00080000
+#define SSTATUS_SPELP MSTATUS_SPELP /* zicfilp */
#define SSTATUS64_UXL 0x0000000300000000ULL
@@ -754,6 +757,7 @@ typedef enum RISCVException {
/* Execution environment configuration bits */
#define MENVCFG_FIOM BIT(0)
+#define MENVCFG_LPE BIT(2) /* zicfilp */
#define MENVCFG_CBIE (3UL << 4)
#define MENVCFG_CBCFE BIT(6)
#define MENVCFG_CBZE BIT(7)
@@ -767,11 +771,13 @@ typedef enum RISCVException {
#define MENVCFGH_STCE BIT(31)
#define SENVCFG_FIOM MENVCFG_FIOM
+#define SENVCFG_LPE MENVCFG_LPE
#define SENVCFG_CBIE MENVCFG_CBIE
#define SENVCFG_CBCFE MENVCFG_CBCFE
#define SENVCFG_CBZE MENVCFG_CBZE
#define HENVCFG_FIOM MENVCFG_FIOM
+#define HENVCFG_LPE MENVCFG_LPE
#define HENVCFG_CBIE MENVCFG_CBIE
#define HENVCFG_CBCFE MENVCFG_CBCFE
#define HENVCFG_CBZE MENVCFG_CBZE
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index f5c10ce85c..e0530a17a3 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -44,7 +44,8 @@ typedef enum {
MSECCFG_MMWP = 1 << 1,
MSECCFG_RLB = 1 << 2,
MSECCFG_USEED = 1 << 8,
- MSECCFG_SSEED = 1 << 9
+ MSECCFG_SSEED = 1 << 9,
+ MSECCFG_MLPE = 1 << 10,
} mseccfg_field_t;
typedef struct {
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6fa2689f35..27fbbd11b9 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1011,6 +1011,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
env->menvcfg = 0;
#endif
+ /* on reset elp is clear */
+ env->elp = false;
+
env->xl = riscv_cpu_mxl(env);
riscv_cpu_update_mask(env);
cs->exception_index = RISCV_EXCP_NONE;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c88ee1265e..02bcb8a23a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1598,6 +1598,11 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
}
}
+ /* If cfi lp extension is available, then apply cfi lp mask */
+ if (env_archcpu(env)->cfg.ext_zicfilp) {
+ mask |= (MSTATUS_MPELP | MSTATUS_SPELP);
+ }
+
mstatus = (mstatus & ~mask) | (val & mask);
env->mstatus = mstatus;
@@ -2344,6 +2349,10 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
(cfg->ext_sstc ? MENVCFG_STCE : 0) |
(cfg->ext_svadu ? MENVCFG_ADUE : 0);
+
+ if (env_archcpu(env)->cfg.ext_zicfilp) {
+ mask |= MENVCFG_LPE;
+ }
}
env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
@@ -2396,6 +2405,10 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
return ret;
}
+ if (env_archcpu(env)->cfg.ext_zicfilp) {
+ mask |= SENVCFG_LPE;
+ }
+
env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
return RISCV_EXCP_NONE;
}
@@ -2433,6 +2446,10 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
if (riscv_cpu_mxl(env) == MXL_RV64) {
mask |= env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE);
+
+ if (env_archcpu(env)->cfg.ext_zicfilp) {
+ mask |= HENVCFG_LPE;
+ }
}
env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
@@ -2897,6 +2914,10 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
mask |= SSTATUS64_UXL;
}
+ if (env_archcpu(env)->cfg.ext_zicfilp) {
+ mask |= SSTATUS_SPELP;
+ }
+
*val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
return RISCV_EXCP_NONE;
}
@@ -2908,6 +2929,11 @@ static RISCVException read_sstatus(CPURISCVState *env, int csrno,
if (env->xl != MXL_RV32 || env->debugger) {
mask |= SSTATUS64_UXL;
}
+
+ if (env_archcpu(env)->cfg.ext_zicfilp) {
+ mask |= SSTATUS_SPELP;
+ }
+
/* TODO: Use SXL not MXL. */
*val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
return RISCV_EXCP_NONE;
@@ -2923,6 +2949,11 @@ static RISCVException write_sstatus(CPURISCVState *env, int csrno,
mask |= SSTATUS64_UXL;
}
}
+
+ if (env_archcpu(env)->cfg.ext_zicfilp) {
+ mask |= SSTATUS_SPELP;
+ }
+
target_ulong newval = (env->mstatus & ~mask) | (val & mask);
return write_mstatus(env, CSR_MSTATUS, newval);
}
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 492c2c6d9d..c3a06c288d 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -350,6 +350,24 @@ static const VMStateDescription vmstate_jvt = {
}
};
+static bool elp_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+
+ return cpu->cfg.ext_zicfilp;
+}
+
+static const VMStateDescription vmstate_elp = {
+ .name = "cpu/elp",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = elp_needed,
+ .fields = (const VMStateField[]) {
+ VMSTATE_BOOL(env.elp, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 10,
@@ -422,6 +440,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_debug,
&vmstate_smstateen,
&vmstate_jvt,
+ &vmstate_elp,
NULL
}
};
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 5e74b7220f..a1b36664fc 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -598,6 +598,11 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
}
+ /* M-mode forward cfi to be enabled if cfi extension is implemented */
+ if (env_archcpu(env)->cfg.ext_zicfilp) {
+ val |= (val & MSECCFG_MLPE);
+ }
+
env->mseccfg = val;
}
--
2.47.0
next prev parent reply other threads:[~2024-10-31 3:54 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-31 3:52 [PULL 00/50] riscv-to-apply queue Alistair Francis
2024-10-31 3:52 ` [PULL 01/50] target/riscv/csr.c: Fix an access to VXSAT Alistair Francis
2024-10-31 3:52 ` [PULL 02/50] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI Alistair Francis
2024-10-31 3:52 ` [PULL 03/50] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 Alistair Francis
2024-10-31 3:52 ` [PULL 04/50] target/riscv: Correct SXL return value for RV32 in RV64 QEMU Alistair Francis
2024-11-05 7:27 ` Michael Tokarev
2024-11-05 23:44 ` Alistair Francis
2024-10-31 3:52 ` [PULL 05/50] target/riscv: Detect sxl to set bit width for RV32 in RV64 Alistair Francis
2024-10-31 3:52 ` [PULL 06/50] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU Alistair Francis
2024-10-31 3:52 ` [PULL 07/50] target/riscv: Enable RV32 CPU support " Alistair Francis
2024-10-31 3:52 ` [PULL 08/50] target/riscv: Add max32 CPU for " Alistair Francis
2024-10-31 3:52 ` [PULL 09/50] tests/avocado: Boot Linux for RV32 cpu on " Alistair Francis
2024-10-31 3:52 ` [PULL 10/50] hw/intc: Make zeroth priority register read-only Alistair Francis
2024-10-31 3:52 ` [PULL 11/50] hw/intc: Don't clear pending bits on IRQ lowering Alistair Francis
2024-10-31 3:52 ` [PULL 12/50] target/riscv: Set vtype.vill on CPU reset Alistair Francis
2024-10-31 3:52 ` [PULL 13/50] hw/intc/riscv_aplic: Check and update pending when write sourcecfg Alistair Francis
2024-10-31 3:52 ` [PULL 14/50] hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all Alistair Francis
2024-10-31 3:52 ` [PULL 15/50] hw/char: sifive_uart: Print uart characters async Alistair Francis
2024-11-04 14:38 ` Thomas Huth
2024-11-04 15:25 ` Philippe Mathieu-Daudé
2025-02-14 12:52 ` Clément Chigot
2025-02-21 15:26 ` Clément Chigot
2025-02-24 4:37 ` Alistair Francis
2025-02-24 10:52 ` Clément Chigot
2024-10-31 3:52 ` [PULL 16/50] target/riscv: expose *envcfg csr and priv to qemu-user as well Alistair Francis
2024-10-31 3:52 ` [PULL 17/50] target/riscv: Add zicfilp extension Alistair Francis
2024-10-31 3:52 ` Alistair Francis [this message]
2024-10-31 3:52 ` [PULL 19/50] target/riscv: save and restore elp state on priv transitions Alistair Francis
2024-10-31 3:52 ` [PULL 20/50] target/riscv: additional code information for sw check Alistair Francis
2024-10-31 3:52 ` [PULL 21/50] target/riscv: tracking indirect branches (fcfi) for zicfilp Alistair Francis
2024-10-31 3:52 ` [PULL 22/50] target/riscv: zicfilp `lpad` impl and branch tracking Alistair Francis
2024-10-31 3:52 ` [PULL 23/50] disas/riscv: enable `lpad` disassembly Alistair Francis
2024-10-31 3:52 ` [PULL 24/50] target/riscv: Expose zicfilp extension as a cpu property Alistair Francis
2024-10-31 3:52 ` [PULL 25/50] target/riscv: Add zicfiss extension Alistair Francis
2024-10-31 3:52 ` [PULL 26/50] target/riscv: introduce ssp and enabling controls for zicfiss Alistair Francis
2024-10-31 3:52 ` [PULL 27/50] target/riscv: tb flag for shadow stack instructions Alistair Francis
2024-10-31 3:52 ` [PULL 28/50] target/riscv: mmu changes for zicfiss shadow stack protection Alistair Francis
2024-10-31 3:52 ` [PULL 29/50] target/riscv: AMO operations always raise store/AMO fault Alistair Francis
2024-10-31 3:52 ` [PULL 30/50] target/riscv: update `decode_save_opc` to store extra word2 Alistair Francis
2024-10-31 3:52 ` [PULL 31/50] target/riscv: implement zicfiss instructions Alistair Francis
2024-10-31 3:53 ` [PULL 32/50] target/riscv: compressed encodings for sspush and sspopchk Alistair Francis
2024-10-31 3:53 ` [PULL 33/50] disas/riscv: enable disassembly for zicfiss instructions Alistair Francis
2024-10-31 3:53 ` [PULL 34/50] disas/riscv: enable disassembly for compressed sspush/sspopchk Alistair Francis
2024-10-31 3:53 ` [PULL 35/50] target/riscv: Expose zicfiss extension as a cpu property Alistair Francis
2024-10-31 3:53 ` [PULL 36/50] exec/memtxattr: add process identifier to the transaction attributes Alistair Francis
2024-10-31 3:53 ` [PULL 37/50] hw/riscv: add riscv-iommu-bits.h Alistair Francis
2024-10-31 3:53 ` [PULL 38/50] hw/riscv: add RISC-V IOMMU base emulation Alistair Francis
2024-10-31 3:53 ` [PULL 39/50] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device Alistair Francis
2024-10-31 3:53 ` [PULL 40/50] hw/riscv: add riscv-iommu-pci reference device Alistair Francis
2024-10-31 3:53 ` [PULL 41/50] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug Alistair Francis
2024-10-31 3:53 ` [PULL 42/50] test/qtest: add riscv-iommu-pci tests Alistair Francis
2024-10-31 3:53 ` [PULL 43/50] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) Alistair Francis
2024-10-31 3:53 ` [PULL 44/50] hw/riscv/riscv-iommu: add ATS support Alistair Francis
2024-10-31 3:53 ` [PULL 45/50] hw/riscv/riscv-iommu: add DBG support Alistair Francis
2024-10-31 3:53 ` [PULL 46/50] qtest/riscv-iommu-test: add init queues test Alistair Francis
2024-10-31 3:53 ` [PULL 47/50] docs/specs: add riscv-iommu Alistair Francis
2024-10-31 3:53 ` [PULL 48/50] target/riscv/kvm: set 'aia_mode' to default in error path Alistair Francis
2024-10-31 3:53 ` [PULL 49/50] target/riscv/kvm: clarify how 'riscv-aia' default works Alistair Francis
2024-10-31 3:53 ` [PULL 50/50] target/riscv: Fix vcompress with rvv_ta_all_1s Alistair Francis
2024-11-01 9:58 ` [PULL 00/50] riscv-to-apply queue Peter Maydell
2024-11-01 13:39 ` Michael Tokarev
2024-11-04 17:55 ` Daniel Henrique Barboza
2024-11-04 22:57 ` Alistair Francis
2024-11-05 7:45 ` Michael Tokarev
2024-11-05 7:55 ` Michael Tokarev
2024-11-05 23:50 ` Alistair Francis
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