From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Deepak Gupta <debug@rivosinc.com>,
Jim Shu <jim.shu@sifive.com>, Andy Chiu <andy.chiu@sifive.com>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 26/50] target/riscv: introduce ssp and enabling controls for zicfiss
Date: Thu, 31 Oct 2024 13:52:54 +1000 [thread overview]
Message-ID: <20241031035319.731906-27-alistair.francis@wdc.com> (raw)
In-Reply-To: <20241031035319.731906-1-alistair.francis@wdc.com>
From: Deepak Gupta <debug@rivosinc.com>
zicfiss introduces a new state ssp ("shadow stack register") in cpu.
ssp is expressed as a new unprivileged csr (CSR_SSP=0x11) and holds
virtual address for shadow stack as programmed by software.
Shadow stack (for each mode) is enabled via bit3 in *envcfg CSRs.
Shadow stack can be enabled for a mode only if it's higher privileged
mode had it enabled for itself. M mode doesn't need enabling control,
it's always available if extension is available on cpu.
This patch also implements helper bcfi function which determines if bcfi
is enabled at current privilege or not.
Adds ssp to migration state as well.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-12-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 3 +++
target/riscv/cpu_bits.h | 6 +++++
target/riscv/cpu.c | 2 ++
target/riscv/cpu_helper.c | 29 ++++++++++++++++++++++
target/riscv/csr.c | 52 +++++++++++++++++++++++++++++++++++++++
target/riscv/machine.c | 19 ++++++++++++++
6 files changed, 111 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c3a03f878b..195eac81c0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -232,6 +232,8 @@ struct CPUArchState {
/* elp state for zicfilp extension */
bool elp;
+ /* shadow stack register for zicfiss extension */
+ target_ulong ssp;
/* sw check code for sw check exception */
target_ulong sw_check_code;
#ifdef CONFIG_USER_ONLY
@@ -550,6 +552,7 @@ bool riscv_cpu_vector_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
int riscv_env_mmu_index(CPURISCVState *env, bool ifetch);
bool cpu_get_fcfien(CPURISCVState *env);
+bool cpu_get_bcfien(CPURISCVState *env);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index e7387c9b8f..8223beaceb 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -34,6 +34,9 @@
/* Control and Status Registers */
+/* zicfiss user ssp csr */
+#define CSR_SSP 0x011
+
/* User Trap Setup */
#define CSR_USTATUS 0x000
#define CSR_UIE 0x004
@@ -761,6 +764,7 @@ typedef enum RISCVException {
/* Execution environment configuration bits */
#define MENVCFG_FIOM BIT(0)
#define MENVCFG_LPE BIT(2) /* zicfilp */
+#define MENVCFG_SSE BIT(3) /* zicfiss */
#define MENVCFG_CBIE (3UL << 4)
#define MENVCFG_CBCFE BIT(6)
#define MENVCFG_CBZE BIT(7)
@@ -775,12 +779,14 @@ typedef enum RISCVException {
#define SENVCFG_FIOM MENVCFG_FIOM
#define SENVCFG_LPE MENVCFG_LPE
+#define SENVCFG_SSE MENVCFG_SSE
#define SENVCFG_CBIE MENVCFG_CBIE
#define SENVCFG_CBCFE MENVCFG_CBCFE
#define SENVCFG_CBZE MENVCFG_CBZE
#define HENVCFG_FIOM MENVCFG_FIOM
#define HENVCFG_LPE MENVCFG_LPE
+#define HENVCFG_SSE MENVCFG_SSE
#define HENVCFG_CBIE MENVCFG_CBIE
#define HENVCFG_CBCFE MENVCFG_CBCFE
#define HENVCFG_CBZE MENVCFG_CBZE
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 377661bae9..afdba29995 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1014,6 +1014,8 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
/* on reset elp is clear */
env->elp = false;
+ /* on reset ssp is set to 0 */
+ env->ssp = 0;
env->xl = riscv_cpu_mxl(env);
riscv_cpu_update_mask(env);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6a63c37083..b42abedf9e 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -91,6 +91,35 @@ bool cpu_get_fcfien(CPURISCVState *env)
}
}
+bool cpu_get_bcfien(CPURISCVState *env)
+{
+ /* no cfi extension, return false */
+ if (!env_archcpu(env)->cfg.ext_zicfiss) {
+ return false;
+ }
+
+ switch (env->priv) {
+ case PRV_U:
+ /*
+ * If S is not implemented then shadow stack for U can't be turned on
+ * It is checked in `riscv_cpu_validate_set_extensions`, so no need to
+ * check here or assert here
+ */
+ return env->senvcfg & SENVCFG_SSE;
+#ifndef CONFIG_USER_ONLY
+ case PRV_S:
+ if (env->virt_enabled) {
+ return env->henvcfg & HENVCFG_SSE;
+ }
+ return env->menvcfg & MENVCFG_SSE;
+ case PRV_M: /* M-mode shadow stack is always off */
+ return false;
+#endif
+ default:
+ g_assert_not_reached();
+ }
+}
+
void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *pflags)
{
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ec1e2af72d..9846770820 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -184,6 +184,25 @@ static RISCVException zcmt(CPURISCVState *env, int csrno)
return RISCV_EXCP_NONE;
}
+static RISCVException cfi_ss(CPURISCVState *env, int csrno)
+{
+ if (!env_archcpu(env)->cfg.ext_zicfiss) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ /* if bcfi not active for current env, access to csr is illegal */
+ if (!cpu_get_bcfien(env)) {
+#if !defined(CONFIG_USER_ONLY)
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+#endif
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
#if !defined(CONFIG_USER_ONLY)
static RISCVException mctr(CPURISCVState *env, int csrno)
{
@@ -622,6 +641,19 @@ static RISCVException seed(CPURISCVState *env, int csrno)
#endif
}
+/* zicfiss CSR_SSP read and write */
+static int read_ssp(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->ssp;
+ return RISCV_EXCP_NONE;
+}
+
+static int write_ssp(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->ssp = val;
+ return RISCV_EXCP_NONE;
+}
+
/* User Floating-Point CSRs */
static RISCVException read_fflags(CPURISCVState *env, int csrno,
target_ulong *val)
@@ -2354,6 +2386,10 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
if (env_archcpu(env)->cfg.ext_zicfilp) {
mask |= MENVCFG_LPE;
}
+
+ if (env_archcpu(env)->cfg.ext_zicfiss) {
+ mask |= MENVCFG_SSE;
+ }
}
env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
@@ -2410,6 +2446,13 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
mask |= SENVCFG_LPE;
}
+ /* Higher mode SSE must be ON for next-less mode SSE to be ON */
+ if (env_archcpu(env)->cfg.ext_zicfiss &&
+ get_field(env->menvcfg, MENVCFG_SSE) &&
+ (env->virt_enabled ? get_field(env->henvcfg, HENVCFG_SSE) : true)) {
+ mask |= SENVCFG_SSE;
+ }
+
env->senvcfg = (env->senvcfg & ~mask) | (val & mask);
return RISCV_EXCP_NONE;
}
@@ -2451,6 +2494,12 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
if (env_archcpu(env)->cfg.ext_zicfilp) {
mask |= HENVCFG_LPE;
}
+
+ /* H can light up SSE for VS only if HS had it from menvcfg */
+ if (env_archcpu(env)->cfg.ext_zicfiss &&
+ get_field(env->menvcfg, MENVCFG_SSE)) {
+ mask |= HENVCFG_SSE;
+ }
}
env->henvcfg = (env->henvcfg & ~mask) | (val & mask);
@@ -4966,6 +5015,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Zcmt Extension */
[CSR_JVT] = {"jvt", zcmt, read_jvt, write_jvt},
+ /* zicfiss Extension, shadow stack register */
+ [CSR_SSP] = { "ssp", cfi_ss, read_ssp, write_ssp },
+
#if !defined(CONFIG_USER_ONLY)
/* Machine Timers and Counters */
[CSR_MCYCLE] = { "mcycle", any, read_hpmcounter,
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index c3a06c288d..99f0af5077 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -368,6 +368,24 @@ static const VMStateDescription vmstate_elp = {
}
};
+static bool ssp_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+
+ return cpu->cfg.ext_zicfiss;
+}
+
+static const VMStateDescription vmstate_ssp = {
+ .name = "cpu/ssp",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = ssp_needed,
+ .fields = (const VMStateField[]) {
+ VMSTATE_UINTTL(env.ssp, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 10,
@@ -441,6 +459,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_smstateen,
&vmstate_jvt,
&vmstate_elp,
+ &vmstate_ssp,
NULL
}
};
--
2.47.0
next prev parent reply other threads:[~2024-10-31 4:02 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-31 3:52 [PULL 00/50] riscv-to-apply queue Alistair Francis
2024-10-31 3:52 ` [PULL 01/50] target/riscv/csr.c: Fix an access to VXSAT Alistair Francis
2024-10-31 3:52 ` [PULL 02/50] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI Alistair Francis
2024-10-31 3:52 ` [PULL 03/50] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 Alistair Francis
2024-10-31 3:52 ` [PULL 04/50] target/riscv: Correct SXL return value for RV32 in RV64 QEMU Alistair Francis
2024-11-05 7:27 ` Michael Tokarev
2024-11-05 23:44 ` Alistair Francis
2024-10-31 3:52 ` [PULL 05/50] target/riscv: Detect sxl to set bit width for RV32 in RV64 Alistair Francis
2024-10-31 3:52 ` [PULL 06/50] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU Alistair Francis
2024-10-31 3:52 ` [PULL 07/50] target/riscv: Enable RV32 CPU support " Alistair Francis
2024-10-31 3:52 ` [PULL 08/50] target/riscv: Add max32 CPU for " Alistair Francis
2024-10-31 3:52 ` [PULL 09/50] tests/avocado: Boot Linux for RV32 cpu on " Alistair Francis
2024-10-31 3:52 ` [PULL 10/50] hw/intc: Make zeroth priority register read-only Alistair Francis
2024-10-31 3:52 ` [PULL 11/50] hw/intc: Don't clear pending bits on IRQ lowering Alistair Francis
2024-10-31 3:52 ` [PULL 12/50] target/riscv: Set vtype.vill on CPU reset Alistair Francis
2024-10-31 3:52 ` [PULL 13/50] hw/intc/riscv_aplic: Check and update pending when write sourcecfg Alistair Francis
2024-10-31 3:52 ` [PULL 14/50] hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all Alistair Francis
2024-10-31 3:52 ` [PULL 15/50] hw/char: sifive_uart: Print uart characters async Alistair Francis
2024-11-04 14:38 ` Thomas Huth
2024-11-04 15:25 ` Philippe Mathieu-Daudé
2025-02-14 12:52 ` Clément Chigot
2025-02-21 15:26 ` Clément Chigot
2025-02-24 4:37 ` Alistair Francis
2025-02-24 10:52 ` Clément Chigot
2024-10-31 3:52 ` [PULL 16/50] target/riscv: expose *envcfg csr and priv to qemu-user as well Alistair Francis
2024-10-31 3:52 ` [PULL 17/50] target/riscv: Add zicfilp extension Alistair Francis
2024-10-31 3:52 ` [PULL 18/50] target/riscv: Introduce elp state and enabling controls for zicfilp Alistair Francis
2024-10-31 3:52 ` [PULL 19/50] target/riscv: save and restore elp state on priv transitions Alistair Francis
2024-10-31 3:52 ` [PULL 20/50] target/riscv: additional code information for sw check Alistair Francis
2024-10-31 3:52 ` [PULL 21/50] target/riscv: tracking indirect branches (fcfi) for zicfilp Alistair Francis
2024-10-31 3:52 ` [PULL 22/50] target/riscv: zicfilp `lpad` impl and branch tracking Alistair Francis
2024-10-31 3:52 ` [PULL 23/50] disas/riscv: enable `lpad` disassembly Alistair Francis
2024-10-31 3:52 ` [PULL 24/50] target/riscv: Expose zicfilp extension as a cpu property Alistair Francis
2024-10-31 3:52 ` [PULL 25/50] target/riscv: Add zicfiss extension Alistair Francis
2024-10-31 3:52 ` Alistair Francis [this message]
2024-10-31 3:52 ` [PULL 27/50] target/riscv: tb flag for shadow stack instructions Alistair Francis
2024-10-31 3:52 ` [PULL 28/50] target/riscv: mmu changes for zicfiss shadow stack protection Alistair Francis
2024-10-31 3:52 ` [PULL 29/50] target/riscv: AMO operations always raise store/AMO fault Alistair Francis
2024-10-31 3:52 ` [PULL 30/50] target/riscv: update `decode_save_opc` to store extra word2 Alistair Francis
2024-10-31 3:52 ` [PULL 31/50] target/riscv: implement zicfiss instructions Alistair Francis
2024-10-31 3:53 ` [PULL 32/50] target/riscv: compressed encodings for sspush and sspopchk Alistair Francis
2024-10-31 3:53 ` [PULL 33/50] disas/riscv: enable disassembly for zicfiss instructions Alistair Francis
2024-10-31 3:53 ` [PULL 34/50] disas/riscv: enable disassembly for compressed sspush/sspopchk Alistair Francis
2024-10-31 3:53 ` [PULL 35/50] target/riscv: Expose zicfiss extension as a cpu property Alistair Francis
2024-10-31 3:53 ` [PULL 36/50] exec/memtxattr: add process identifier to the transaction attributes Alistair Francis
2024-10-31 3:53 ` [PULL 37/50] hw/riscv: add riscv-iommu-bits.h Alistair Francis
2024-10-31 3:53 ` [PULL 38/50] hw/riscv: add RISC-V IOMMU base emulation Alistair Francis
2024-10-31 3:53 ` [PULL 39/50] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device Alistair Francis
2024-10-31 3:53 ` [PULL 40/50] hw/riscv: add riscv-iommu-pci reference device Alistair Francis
2024-10-31 3:53 ` [PULL 41/50] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug Alistair Francis
2024-10-31 3:53 ` [PULL 42/50] test/qtest: add riscv-iommu-pci tests Alistair Francis
2024-10-31 3:53 ` [PULL 43/50] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) Alistair Francis
2024-10-31 3:53 ` [PULL 44/50] hw/riscv/riscv-iommu: add ATS support Alistair Francis
2024-10-31 3:53 ` [PULL 45/50] hw/riscv/riscv-iommu: add DBG support Alistair Francis
2024-10-31 3:53 ` [PULL 46/50] qtest/riscv-iommu-test: add init queues test Alistair Francis
2024-10-31 3:53 ` [PULL 47/50] docs/specs: add riscv-iommu Alistair Francis
2024-10-31 3:53 ` [PULL 48/50] target/riscv/kvm: set 'aia_mode' to default in error path Alistair Francis
2024-10-31 3:53 ` [PULL 49/50] target/riscv/kvm: clarify how 'riscv-aia' default works Alistair Francis
2024-10-31 3:53 ` [PULL 50/50] target/riscv: Fix vcompress with rvv_ta_all_1s Alistair Francis
2024-11-01 9:58 ` [PULL 00/50] riscv-to-apply queue Peter Maydell
2024-11-01 13:39 ` Michael Tokarev
2024-11-04 17:55 ` Daniel Henrique Barboza
2024-11-04 22:57 ` Alistair Francis
2024-11-05 7:45 ` Michael Tokarev
2024-11-05 7:55 ` Michael Tokarev
2024-11-05 23:50 ` Alistair Francis
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