* [PULL 01/14] target/mips: Migrate TLB MemoryMapID register
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 02/14] target/mips: Enable MSA ASE for mips32r6-generic Philippe Mathieu-Daudé
` (13 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel
Cc: Yongbok Kim, Aleksandar Markovic, Aleksandar Rakic,
Aleksandar Rikalo, Philippe Mathieu-Daudé
From: Yongbok Kim <yongbok.kim@mips.com>
Include CP0 MemoryMapID register in migration state.
Fixes: 99029be1c28 ("target/mips: Add implementation of GINVT instruction")
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com>
Message-ID: <AM9PR09MB4851FB6034EDB7FA191BA47E84402@AM9PR09MB4851.eurprd09.prod.outlook.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/sysemu/machine.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c
index 213fd637fcb..91cd9f19002 100644
--- a/target/mips/sysemu/machine.c
+++ b/target/mips/sysemu/machine.c
@@ -142,6 +142,7 @@ static int get_tlb(QEMUFile *f, void *pv, size_t size,
qemu_get_betls(f, &v->VPN);
qemu_get_be32s(f, &v->PageMask);
qemu_get_be16s(f, &v->ASID);
+ qemu_get_be32s(f, &v->MMID);
qemu_get_be16s(f, &flags);
v->G = (flags >> 10) & 1;
v->C0 = (flags >> 7) & 3;
@@ -167,6 +168,7 @@ static int put_tlb(QEMUFile *f, void *pv, size_t size,
r4k_tlb_t *v = pv;
uint16_t asid = v->ASID;
+ uint32_t mmid = v->MMID;
uint16_t flags = ((v->EHINV << 15) |
(v->RI1 << 14) |
(v->RI0 << 13) |
@@ -183,6 +185,7 @@ static int put_tlb(QEMUFile *f, void *pv, size_t size,
qemu_put_betls(f, &v->VPN);
qemu_put_be32s(f, &v->PageMask);
qemu_put_be16s(f, &asid);
+ qemu_put_be32s(f, &mmid);
qemu_put_be16s(f, &flags);
qemu_put_be64s(f, &v->PFN[0]);
qemu_put_be64s(f, &v->PFN[1]);
@@ -204,8 +207,8 @@ static const VMStateInfo vmstate_info_tlb = {
static const VMStateDescription vmstate_tlb = {
.name = "cpu/tlb",
- .version_id = 2,
- .minimum_version_id = 2,
+ .version_id = 3,
+ .minimum_version_id = 3,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL 02/14] target/mips: Enable MSA ASE for mips32r6-generic
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 01/14] target/mips: Migrate TLB MemoryMapID register Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 03/14] target/mips: Extract decode_64bit_enabled() helper Philippe Mathieu-Daudé
` (12 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Markovic, Faraz Shahbazker, Aleksandar Rakic,
Aleksandar Rikalo, Philippe Mathieu-Daudé
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Enable MSA ASE for mips32r6-generic CPU.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.rakic@htecgroup.com>
Reviewed-by: Aleksandar Rikalo <arikalo@gmail.com>
Message-ID: <AM9PR09MB485153B7CB706E188DED763484402@AM9PR09MB4851.eurprd09.prod.outlook.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/cpu-defs.c.inc | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index fbf787d8ce1..1ab026c57e7 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -478,14 +478,15 @@ const mips_def_t mips_defs[] =
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
(0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_MSAP) |
+ (1 << CP0C3_BP) | (1 << CP0C3_BI) |
(2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
(1 << CP0C3_RXI) | (1U << CP0C3_M),
.CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
(3 << CP0C4_IE) | (1U << CP0C4_M),
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
- .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
- (1 << CP0C5_UFE),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
+ (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 0,
.SYNCI_Step = 32,
@@ -499,6 +500,7 @@ const mips_def_t mips_defs[] =
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
.CP1_fcr31_rw_bitmask = 0x0103FFFF,
+ .MSAIR = 0x03 << MSAIR_ProcID,
.SEGBITS = 32,
.PABITS = 32,
.insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL 03/14] target/mips: Extract decode_64bit_enabled() helper
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 01/14] target/mips: Migrate TLB MemoryMapID register Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 02/14] target/mips: Enable MSA ASE for mips32r6-generic Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 04/14] target/mips: Simplify Loongson MULTU.G opcode Philippe Mathieu-Daudé
` (11 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Pierrick Bouvier
Extract the decode_64bit_enabled() helper which detects
whether CPUs can run 64-bit instructions.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241026175349.84523-2-philmd@linaro.org>
---
target/mips/tcg/translate.h | 2 ++
target/mips/tcg/translate.c | 7 ++++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 5d196e69ac4..ae6c25aa0c4 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -217,6 +217,8 @@ void msa_translate_init(void);
void mxu_translate_init(void);
bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
+bool decode_64bit_enabled(DisasContext *ctx);
+
/* decodetree generated */
bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index d92fc418edd..6c881af5618 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1645,13 +1645,18 @@ static inline void check_ps(DisasContext *ctx)
check_cp1_64bitmode(ctx);
}
+bool decode_64bit_enabled(DisasContext *ctx)
+{
+ return ctx->hflags & MIPS_HFLAG_64;
+}
+
/*
* This code generates a "reserved instruction" exception if cpu is not
* 64-bit or 64-bit instructions are not enabled.
*/
void check_mips_64(DisasContext *ctx)
{
- if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) {
+ if (unlikely((TARGET_LONG_BITS != 64) || !decode_64bit_enabled(ctx))) {
gen_reserved_instruction(ctx);
}
}
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL 04/14] target/mips: Simplify Loongson MULTU.G opcode
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2024-10-31 4:21 ` [PULL 03/14] target/mips: Extract decode_64bit_enabled() helper Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 05/14] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP Philippe Mathieu-Daudé
` (10 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Richard Henderson
Since MULTU opcodes don't record the most significant bits
of the infinite result, sign-extending the sources make no
difference in the result.
Once we remove the sign extension of source registers, MULT
and MULTU are identical (as are DMULT and DMULTU).
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241026175349.84523-3-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/translate.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 6c881af5618..6d7e913263e 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -3615,8 +3615,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
break;
case OPC_MULTU_G_2E:
case OPC_MULTU_G_2F:
- tcg_gen_ext32u_tl(t0, t0);
- tcg_gen_ext32u_tl(t1, t1);
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
break;
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL 05/14] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2024-10-31 4:21 ` [PULL 04/14] target/mips: Simplify Loongson MULTU.G opcode Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 06/14] target/mips: Convert Loongson DDIV.G opcodes to decodetree Philippe Mathieu-Daudé
` (9 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Jiaxun Yang, Richard Henderson,
Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
There is no issue having multiple enum declarations with
the same value. As we are going to remove the OPC_MULT_G_2E
definition in few commits, restore the OPC_ADDUH_QB_DSP and
OPC_MUL_PH_DSP definitions and use them where they belong.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241026175349.84523-4-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/translate.c | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 6d7e913263e..509488fdc7a 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -389,16 +389,14 @@ enum {
OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3,
OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3,
OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3,
- /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */
- /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */
+ OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3,
OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3,
/* MIPS DSP GPR-Based Shift Sub-class */
OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3,
OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3,
/* MIPS DSP Multiply Sub-class insns */
- /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */
- /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */
+ OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3,
OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3,
OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3,
/* DSP Bit/Manipulation Sub-class */
@@ -556,7 +554,6 @@ enum {
OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP,
};
-#define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
#define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
enum {
/* MIPS DSP Arithmetic Sub-class */
@@ -11587,8 +11584,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_load_gpr(v2_t, v2);
switch (op1) {
- /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
- case OPC_MULT_G_2E:
+ case OPC_ADDUH_QB_DSP:
check_dsp_r2(ctx);
switch (op2) {
case OPC_ADDUH_QB:
@@ -12271,11 +12267,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_load_gpr(v2_t, v2);
switch (op1) {
- /*
- * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
- * the same mask and op1.
- */
- case OPC_MULT_G_2E:
+ case OPC_MUL_PH_DSP:
check_dsp_r2(ctx);
switch (op2) {
case OPC_MUL_PH:
@@ -13811,7 +13803,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1.
*/
- if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) {
+ if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MUL_PH_DSP)) {
op2 = MASK_ADDUH_QB(ctx->opcode);
switch (op2) {
case OPC_ADDUH_QB:
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL 06/14] target/mips: Convert Loongson DDIV.G opcodes to decodetree
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2024-10-31 4:21 ` [PULL 05/14] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 07/14] target/mips: Convert Loongson DIV.G " Philippe Mathieu-Daudé
` (8 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Richard Henderson,
Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Introduce decode_loongson() to decode all Loongson vendor
specific opcodes. Start converting a single opcode: DDIV.G
(divide 64-bit signed integers).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20241026175349.84523-5-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/translate.h | 1 +
target/mips/tcg/godson2.decode | 16 ++++++
target/mips/tcg/loong-ext.decode | 17 ++++++
target/mips/tcg/loong_translate.c | 86 +++++++++++++++++++++++++++++++
target/mips/tcg/translate.c | 26 ++--------
target/mips/tcg/meson.build | 3 ++
6 files changed, 126 insertions(+), 23 deletions(-)
create mode 100644 target/mips/tcg/godson2.decode
create mode 100644 target/mips/tcg/loong-ext.decode
create mode 100644 target/mips/tcg/loong_translate.c
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index ae6c25aa0c4..23a489c0f38 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -223,6 +223,7 @@ bool decode_64bit_enabled(DisasContext *ctx);
bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
+bool decode_ext_loongson(DisasContext *ctx, uint32_t insn);
#if defined(TARGET_MIPS64)
bool decode_ase_lcsr(DisasContext *ctx, uint32_t insn);
bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);
diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode
new file mode 100644
index 00000000000..47ea5a1c438
--- /dev/null
+++ b/target/mips/tcg/godson2.decode
@@ -0,0 +1,16 @@
+# Godson2 64-bit Integer instructions
+#
+# Copyright (C) 2021 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# Godson-2E Software Manual
+# (Document Number: godson2e-user-manual-V0.6)
+#
+
+&muldiv rs rt rd
+
+@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
+
+DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.decode
new file mode 100644
index 00000000000..8b78ec48599
--- /dev/null
+++ b/target/mips/tcg/loong-ext.decode
@@ -0,0 +1,17 @@
+# Loongson 64-bit Extension instructions
+#
+# Copyright (C) 2021 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# STLS2F01 User Manual
+# Appendix A: new integer instructions
+# (Document Number: UM0447)
+#
+
+&muldiv rs rt rd !extern
+
+@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
+
+DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c
new file mode 100644
index 00000000000..53e4047cfa0
--- /dev/null
+++ b/target/mips/tcg/loong_translate.c
@@ -0,0 +1,86 @@
+/*
+ * MIPS Loongson 64-bit translation routines
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ * Copyright (c) 2011 Richard Henderson <rth@twiddle.net>
+ * Copyright (c) 2021 Philippe Mathieu-Daudé
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#include "qemu/osdep.h"
+#include "translate.h"
+
+/* Include the auto-generated decoder. */
+#include "decode-godson2.c.inc"
+#include "decode-loong-ext.c.inc"
+
+/*
+ * Word or double-word Fixed-point instructions.
+ * ---------------------------------------------
+ *
+ * Fixed-point multiplies and divisions write only
+ * one result into general-purpose registers.
+ */
+
+static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt)
+{
+ TCGv t0, t1;
+ TCGLabel *l1, *l2, *l3;
+
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+ l3 = gen_new_label();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
+ tcg_gen_movi_tl(cpu_gpr[rd], 0);
+ tcg_gen_br(l3);
+ gen_set_label(l1);
+
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
+ tcg_gen_mov_tl(cpu_gpr[rd], t0);
+
+ tcg_gen_br(l3);
+ gen_set_label(l2);
+ tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
+ gen_set_label(l3);
+
+ return true;
+}
+
+static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_DIV_G(s, a->rt, a->rs, a->rd);
+}
+
+bool decode_ext_loongson(DisasContext *ctx, uint32_t insn)
+{
+ if (!decode_64bit_enabled(ctx)) {
+ return false;
+ }
+ if ((ctx->insn_flags & INSN_LOONGSON2E) && decode_godson2(ctx, ctx->opcode)) {
+ return true;
+ }
+ if ((ctx->insn_flags & ASE_LEXT) && decode_loong_ext(ctx, ctx->opcode)) {
+ return true;
+ }
+ return false;
+}
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 509488fdc7a..73445dd9074 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -333,7 +333,6 @@ enum {
OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2,
- OPC_DDIV_G_2F = 0x15 | OPC_SPECIAL2,
OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2,
OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2,
OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
@@ -375,7 +374,6 @@ enum {
OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3,
OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
- OPC_DDIV_G_2E = 0x1E | OPC_SPECIAL3,
OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3,
OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
@@ -3698,25 +3696,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
case OPC_DMULTU_G_2F:
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
break;
- case OPC_DDIV_G_2E:
- case OPC_DDIV_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGLabel *l3 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l3);
- gen_set_label(l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
- tcg_gen_mov_tl(cpu_gpr[rd], t0);
- tcg_gen_br(l3);
- gen_set_label(l2);
- tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
- gen_set_label(l3);
- }
- break;
case OPC_DDIVU_G_2E:
case OPC_DDIVU_G_2F:
{
@@ -13654,7 +13633,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_DMULT_G_2F:
case OPC_DMULTU_G_2F:
- case OPC_DDIV_G_2F:
case OPC_DDIVU_G_2F:
case OPC_DMOD_G_2F:
case OPC_DMODU_G_2F:
@@ -14061,7 +14039,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DDIV_G_2E:
case OPC_DDIVU_G_2E:
case OPC_DMULT_G_2E:
case OPC_DMULTU_G_2E:
@@ -15262,6 +15239,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) {
return;
}
+ if (TARGET_LONG_BITS == 64 && decode_ext_loongson(ctx, ctx->opcode)) {
+ return;
+ }
#if defined(TARGET_MIPS64)
if (ase_lcsr_available(env) && decode_ase_lcsr(ctx, ctx->opcode)) {
return;
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index ea7fb582f2a..fd91148df74 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -1,4 +1,6 @@
gen = [
+ decodetree.process('godson2.decode', extra_args: ['--static-decode=decode_godson2']),
+ decodetree.process('loong-ext.decode', extra_args: ['--static-decode=decode_loong_ext']),
decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']),
decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'),
decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
@@ -28,6 +30,7 @@ mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
'tx79_translate.c',
'octeon_translate.c',
'lcsr_translate.c',
+ 'loong_translate.c',
), if_false: files(
'mxu_translate.c',
))
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL 07/14] target/mips: Convert Loongson DIV.G opcodes to decodetree
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2024-10-31 4:21 ` [PULL 06/14] target/mips: Convert Loongson DDIV.G opcodes to decodetree Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 08/14] target/mips: Convert Loongson [D]DIVU.G " Philippe Mathieu-Daudé
` (7 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Richard Henderson,
Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a
'is_double' argument so it can generate DIV.G (divide 32-bit
signed integers).
With this commit we explicit the template used to generate
opcode for 32/64-bit word variants. Next commits will be less
verbose by providing both variants at once.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20241026175349.84523-6-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/godson2.decode | 1 +
target/mips/tcg/loong-ext.decode | 1 +
target/mips/tcg/loong_translate.c | 28 ++++++++++++++++++++++------
target/mips/tcg/translate.c | 26 --------------------------
4 files changed, 24 insertions(+), 32 deletions(-)
diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode
index 47ea5a1c438..cbf24ed88da 100644
--- a/target/mips/tcg/godson2.decode
+++ b/target/mips/tcg/godson2.decode
@@ -13,4 +13,5 @@
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
+DIV_G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd
DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.decode
index 8b78ec48599..9397606beb6 100644
--- a/target/mips/tcg/loong-ext.decode
+++ b/target/mips/tcg/loong-ext.decode
@@ -14,4 +14,5 @@
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
+DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c
index 53e4047cfa0..7c405078795 100644
--- a/target/mips/tcg/loong_translate.c
+++ b/target/mips/tcg/loong_translate.c
@@ -25,15 +25,18 @@
* one result into general-purpose registers.
*/
-static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt)
+static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,
+ bool is_double)
{
TCGv t0, t1;
TCGLabel *l1, *l2, *l3;
- if (TARGET_LONG_BITS != 64) {
- return false;
+ if (is_double) {
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
}
- check_mips_64(s);
if (rd == 0) {
/* Treat as NOP. */
@@ -49,26 +52,39 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt)
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
+ if (!is_double) {
+ tcg_gen_ext32s_tl(t0, t0);
+ tcg_gen_ext32s_tl(t1, t1);
+ }
tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
tcg_gen_br(l3);
gen_set_label(l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS == 64
+ ? LLONG_MIN : INT_MIN, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
tcg_gen_mov_tl(cpu_gpr[rd], t0);
tcg_gen_br(l3);
gen_set_label(l2);
tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
+ if (!is_double) {
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+ }
gen_set_label(l3);
return true;
}
+static bool trans_DIV_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, false);
+}
+
static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
{
- return gen_lext_DIV_G(s, a->rt, a->rs, a->rd);
+ return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, true);
}
bool decode_ext_loongson(DisasContext *ctx, uint32_t insn)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 73445dd9074..1c38e893d31 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -332,7 +332,6 @@ enum {
OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
- OPC_DIV_G_2F = 0x14 | OPC_SPECIAL2,
OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2,
OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2,
OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
@@ -370,7 +369,6 @@ enum {
/* Loongson 2E */
OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3,
OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
- OPC_DIV_G_2E = 0x1A | OPC_SPECIAL3,
OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3,
OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
@@ -3613,28 +3611,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
break;
- case OPC_DIV_G_2E:
- case OPC_DIV_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGLabel *l3 = gen_new_label();
- tcg_gen_ext32s_tl(t0, t0);
- tcg_gen_ext32s_tl(t1, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l3);
- gen_set_label(l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
- tcg_gen_mov_tl(cpu_gpr[rd], t0);
- tcg_gen_br(l3);
- gen_set_label(l2);
- tcg_gen_div_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- gen_set_label(l3);
- }
- break;
case OPC_DIVU_G_2E:
case OPC_DIVU_G_2F:
{
@@ -13598,7 +13574,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MUL:
gen_arith(ctx, op1, rd, rs, rt);
break;
- case OPC_DIV_G_2F:
case OPC_DIVU_G_2F:
case OPC_MULT_G_2F:
case OPC_MULTU_G_2F:
@@ -13771,7 +13746,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
- case OPC_DIV_G_2E:
case OPC_DIVU_G_2E:
case OPC_MOD_G_2E:
case OPC_MODU_G_2E:
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL 08/14] target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2024-10-31 4:21 ` [PULL 07/14] target/mips: Convert Loongson DIV.G " Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 09/14] target/mips: Convert Loongson [D]MOD[U].G " Philippe Mathieu-Daudé
` (6 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Richard Henderson,
Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G
(divide 64-bit unsigned integers) opcodes to decodetree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20241026175349.84523-7-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/godson2.decode | 2 ++
target/mips/tcg/loong-ext.decode | 2 ++
target/mips/tcg/loong_translate.c | 54 +++++++++++++++++++++++++++++++
target/mips/tcg/translate.c | 37 ---------------------
4 files changed, 58 insertions(+), 37 deletions(-)
diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode
index cbf24ed88da..581cb9c8608 100644
--- a/target/mips/tcg/godson2.decode
+++ b/target/mips/tcg/godson2.decode
@@ -14,4 +14,6 @@
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
DIV_G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd
+DIVU_G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd
DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
+DDIVU_G 011111 ..... ..... ..... 00000 011111 @rs_rt_rd
diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.decode
index 9397606beb6..e222167af56 100644
--- a/target/mips/tcg/loong-ext.decode
+++ b/target/mips/tcg/loong-ext.decode
@@ -16,3 +16,5 @@
DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
+DIVU_G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd
+DDIVU_G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd
diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c
index 7c405078795..903d242e7cc 100644
--- a/target/mips/tcg/loong_translate.c
+++ b/target/mips/tcg/loong_translate.c
@@ -87,6 +87,60 @@ static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
return gen_lext_DIV_G(s, a->rt, a->rs, a->rd, true);
}
+static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
+ bool is_double)
+{
+ TCGv t0, t1;
+ TCGLabel *l1, *l2;
+
+ if (is_double) {
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
+ }
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ if (!is_double) {
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ }
+ tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
+ tcg_gen_movi_tl(cpu_gpr[rd], 0);
+
+ tcg_gen_br(l2);
+ gen_set_label(l1);
+ tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
+ if (!is_double) {
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+ }
+ gen_set_label(l2);
+
+ return true;
+}
+
+static bool trans_DIVU_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, false);
+}
+
+static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, true);
+}
+
bool decode_ext_loongson(DisasContext *ctx, uint32_t insn)
{
if (!decode_64bit_enabled(ctx)) {
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 1c38e893d31..53bbbb761f8 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -332,8 +332,6 @@ enum {
OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
- OPC_DIVU_G_2F = 0x16 | OPC_SPECIAL2,
- OPC_DDIVU_G_2F = 0x17 | OPC_SPECIAL2,
OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2,
OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2,
@@ -369,10 +367,8 @@ enum {
/* Loongson 2E */
OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3,
OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
- OPC_DIVU_G_2E = 0x1B | OPC_SPECIAL3,
OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
- OPC_DDIVU_G_2E = 0x1F | OPC_SPECIAL3,
OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3,
@@ -3611,22 +3607,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
break;
- case OPC_DIVU_G_2E:
- case OPC_DIVU_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- tcg_gen_ext32u_tl(t0, t0);
- tcg_gen_ext32u_tl(t1, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- gen_set_label(l2);
- }
- break;
case OPC_MOD_G_2E:
case OPC_MOD_G_2F:
{
@@ -3672,19 +3652,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
case OPC_DMULTU_G_2F:
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
break;
- case OPC_DDIVU_G_2E:
- case OPC_DDIVU_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);
- gen_set_label(l2);
- }
- break;
case OPC_DMOD_G_2E:
case OPC_DMOD_G_2F:
{
@@ -13574,7 +13541,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MUL:
gen_arith(ctx, op1, rd, rs, rt);
break;
- case OPC_DIVU_G_2F:
case OPC_MULT_G_2F:
case OPC_MULTU_G_2F:
case OPC_MOD_G_2F:
@@ -13608,7 +13574,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_DMULT_G_2F:
case OPC_DMULTU_G_2F:
- case OPC_DDIVU_G_2F:
case OPC_DMOD_G_2F:
case OPC_DMODU_G_2F:
check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
@@ -13746,7 +13711,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
- case OPC_DIVU_G_2E:
case OPC_MOD_G_2E:
case OPC_MODU_G_2E:
case OPC_MULT_G_2E:
@@ -14013,7 +13977,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DDIVU_G_2E:
case OPC_DMULT_G_2E:
case OPC_DMULTU_G_2E:
case OPC_DMOD_G_2E:
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL 09/14] target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2024-10-31 4:21 ` [PULL 08/14] target/mips: Convert Loongson [D]DIVU.G " Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 10/14] target/mips: Convert Loongson [D]MULT[U].G " Philippe Mathieu-Daudé
` (5 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Richard Henderson,
Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Convert the following opcodes to decodetree:
- MOD.G - mod 32-bit signed integers
- MODU.G - mod 32-bit unsigned integers
- DMOD.G - mod 64-bit signed integers
- DMODU.G - mod 64-bit unsigned integers
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20241026175349.84523-8-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/godson2.decode | 5 ++
target/mips/tcg/loong-ext.decode | 5 ++
target/mips/tcg/loong_translate.c | 111 ++++++++++++++++++++++++++++++
target/mips/tcg/translate.c | 82 ----------------------
4 files changed, 121 insertions(+), 82 deletions(-)
diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode
index 581cb9c8608..c03c8b717d9 100644
--- a/target/mips/tcg/godson2.decode
+++ b/target/mips/tcg/godson2.decode
@@ -17,3 +17,8 @@ DIV_G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd
DIVU_G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd
DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
DDIVU_G 011111 ..... ..... ..... 00000 011111 @rs_rt_rd
+
+MOD_G 011111 ..... ..... ..... 00000 100010 @rs_rt_rd
+MODU_G 011111 ..... ..... ..... 00000 100011 @rs_rt_rd
+DMOD_G 011111 ..... ..... ..... 00000 100110 @rs_rt_rd
+DMODU_G 011111 ..... ..... ..... 00000 100111 @rs_rt_rd
diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.decode
index e222167af56..f0fd36c9218 100644
--- a/target/mips/tcg/loong-ext.decode
+++ b/target/mips/tcg/loong-ext.decode
@@ -18,3 +18,8 @@ DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
DIVU_G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd
DDIVU_G 011100 ..... ..... ..... 00000 010111 @rs_rt_rd
+
+MOD_G 011100 ..... ..... ..... 00000 011100 @rs_rt_rd
+DMOD_G 011100 ..... ..... ..... 00000 011101 @rs_rt_rd
+MODU_G 011100 ..... ..... ..... 00000 011110 @rs_rt_rd
+DMODU_G 011100 ..... ..... ..... 00000 011111 @rs_rt_rd
diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c
index 903d242e7cc..76c1a8cef2d 100644
--- a/target/mips/tcg/loong_translate.c
+++ b/target/mips/tcg/loong_translate.c
@@ -141,6 +141,117 @@ static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *a)
return gen_lext_DIVU_G(s, a->rt, a->rs, a->rd, true);
}
+static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,
+ bool is_double)
+{
+ TCGv t0, t1;
+ TCGLabel *l1, *l2, *l3;
+
+ if (is_double) {
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
+ }
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+ l3 = gen_new_label();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ if (!is_double) {
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ }
+ tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS == 64
+ ? LLONG_MIN : INT_MIN, l2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
+ gen_set_label(l1);
+ tcg_gen_movi_tl(cpu_gpr[rd], 0);
+ tcg_gen_br(l3);
+ gen_set_label(l2);
+ tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
+ if (!is_double) {
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+ }
+ gen_set_label(l3);
+
+ return true;
+}
+
+static bool trans_MOD_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MOD_G(s, a->rt, a->rs, a->rd, false);
+}
+
+static bool trans_DMOD_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MOD_G(s, a->rt, a->rs, a->rd, true);
+}
+
+static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt,
+ bool is_double)
+{
+ TCGv t0, t1;
+ TCGLabel *l1, *l2;
+
+ if (is_double) {
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
+ }
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ if (!is_double) {
+ tcg_gen_ext32u_tl(t0, t0);
+ tcg_gen_ext32u_tl(t1, t1);
+ }
+ tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
+ tcg_gen_movi_tl(cpu_gpr[rd], 0);
+ tcg_gen_br(l2);
+ gen_set_label(l1);
+ tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
+ if (!is_double) {
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+ }
+ gen_set_label(l2);
+
+ return true;
+}
+
+static bool trans_MODU_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, false);
+}
+
+static bool trans_DMODU_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, true);
+}
+
bool decode_ext_loongson(DisasContext *ctx, uint32_t insn)
{
if (!decode_64bit_enabled(ctx)) {
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 53bbbb761f8..4abc30a6a5f 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -332,10 +332,6 @@ enum {
OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
- OPC_MOD_G_2F = 0x1c | OPC_SPECIAL2,
- OPC_DMOD_G_2F = 0x1d | OPC_SPECIAL2,
- OPC_MODU_G_2F = 0x1e | OPC_SPECIAL2,
- OPC_DMODU_G_2F = 0x1f | OPC_SPECIAL2,
/* Misc */
OPC_CLZ = 0x20 | OPC_SPECIAL2,
OPC_CLO = 0x21 | OPC_SPECIAL2,
@@ -369,10 +365,6 @@ enum {
OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
- OPC_MOD_G_2E = 0x22 | OPC_SPECIAL3,
- OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3,
- OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3,
- OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3,
/* MIPS DSP Load */
OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
@@ -3607,42 +3599,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
break;
- case OPC_MOD_G_2E:
- case OPC_MOD_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGLabel *l3 = gen_new_label();
- tcg_gen_ext32u_tl(t0, t0);
- tcg_gen_ext32u_tl(t1, t1);
- tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2);
- gen_set_label(l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l3);
- gen_set_label(l2);
- tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- gen_set_label(l3);
- }
- break;
- case OPC_MODU_G_2E:
- case OPC_MODU_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- tcg_gen_ext32u_tl(t0, t0);
- tcg_gen_ext32u_tl(t1, t1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- gen_set_label(l2);
- }
- break;
#if defined(TARGET_MIPS64)
case OPC_DMULT_G_2E:
case OPC_DMULT_G_2F:
@@ -3652,36 +3608,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
case OPC_DMULTU_G_2F:
tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
break;
- case OPC_DMOD_G_2E:
- case OPC_DMOD_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- TCGLabel *l3 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2);
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
- gen_set_label(l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l3);
- gen_set_label(l2);
- tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);
- gen_set_label(l3);
- }
- break;
- case OPC_DMODU_G_2E:
- case OPC_DMODU_G_2F:
- {
- TCGLabel *l1 = gen_new_label();
- TCGLabel *l2 = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);
- gen_set_label(l2);
- }
- break;
#endif
}
}
@@ -13543,8 +13469,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_MULT_G_2F:
case OPC_MULTU_G_2F:
- case OPC_MOD_G_2F:
- case OPC_MODU_G_2F:
check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
@@ -13574,8 +13498,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_DMULT_G_2F:
case OPC_DMULTU_G_2F:
- case OPC_DMOD_G_2F:
- case OPC_DMODU_G_2F:
check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
@@ -13711,8 +13633,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
- case OPC_MOD_G_2E:
- case OPC_MODU_G_2E:
case OPC_MULT_G_2E:
case OPC_MULTU_G_2E:
/*
@@ -13979,8 +13899,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
case OPC_DMULT_G_2E:
case OPC_DMULTU_G_2E:
- case OPC_DMOD_G_2E:
- case OPC_DMODU_G_2E:
check_insn(ctx, INSN_LOONGSON2E);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL 10/14] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2024-10-31 4:21 ` [PULL 09/14] target/mips: Convert Loongson [D]MOD[U].G " Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 11/14] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext Philippe Mathieu-Daudé
` (4 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Richard Henderson,
Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Convert the following opcodes to decodetree:
- MULT.G - multiply 32-bit signed integers
- MULTU.G - multiply 32-bit unsigned integers
- DMULT.G - multiply 64-bit signed integers
- DMULTU.G - multiply 64-bit unsigned integers
Now that all opcodes from the extension have been converted, we
can remove completely gen_loongson_integer() and its 2 calls in
decode_opc_special2_legacy() and decode_opc_special3_legacy().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241026175349.84523-9-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/godson2.decode | 3 ++
target/mips/tcg/loong-ext.decode | 3 ++
target/mips/tcg/loong_translate.c | 41 +++++++++++++++++
target/mips/tcg/translate.c | 73 +------------------------------
4 files changed, 49 insertions(+), 71 deletions(-)
diff --git a/target/mips/tcg/godson2.decode b/target/mips/tcg/godson2.decode
index c03c8b717d9..25b396b6822 100644
--- a/target/mips/tcg/godson2.decode
+++ b/target/mips/tcg/godson2.decode
@@ -13,6 +13,9 @@
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
+MULTu_G 011111 ..... ..... ..... 00000 01100- @rs_rt_rd
+DMULTu_G 011111 ..... ..... ..... 00000 01110- @rs_rt_rd
+
DIV_G 011111 ..... ..... ..... 00000 011010 @rs_rt_rd
DIVU_G 011111 ..... ..... ..... 00000 011011 @rs_rt_rd
DDIV_G 011111 ..... ..... ..... 00000 011110 @rs_rt_rd
diff --git a/target/mips/tcg/loong-ext.decode b/target/mips/tcg/loong-ext.decode
index f0fd36c9218..b43979d0ef5 100644
--- a/target/mips/tcg/loong-ext.decode
+++ b/target/mips/tcg/loong-ext.decode
@@ -14,6 +14,9 @@
@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &muldiv
+MULTu_G 011100 ..... ..... ..... 00000 0100-0 @rs_rt_rd
+DMULTu_G 011100 ..... ..... ..... 00000 0100-1 @rs_rt_rd
+
DIV_G 011100 ..... ..... ..... 00000 010100 @rs_rt_rd
DDIV_G 011100 ..... ..... ..... 00000 010101 @rs_rt_rd
DIVU_G 011100 ..... ..... ..... 00000 010110 @rs_rt_rd
diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c
index 76c1a8cef2d..c02e60bb15b 100644
--- a/target/mips/tcg/loong_translate.c
+++ b/target/mips/tcg/loong_translate.c
@@ -252,6 +252,47 @@ static bool trans_DMODU_G(DisasContext *s, arg_muldiv *a)
return gen_lext_MODU_G(s, a->rt, a->rs, a->rd, true);
}
+static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt,
+ bool is_double)
+{
+ TCGv t0, t1;
+
+ if (is_double) {
+ if (TARGET_LONG_BITS != 64) {
+ return false;
+ }
+ check_mips_64(s);
+ }
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+
+ tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
+ if (!is_double) {
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+ }
+
+ return true;
+}
+
+static bool trans_MULTu_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, false);
+}
+
+static bool trans_DMULTu_G(DisasContext *s, arg_muldiv *a)
+{
+ return gen_lext_MULT_G(s, a->rt, a->rs, a->rd, true);
+}
+
bool decode_ext_loongson(DisasContext *ctx, uint32_t insn)
{
if (!decode_64bit_enabled(ctx)) {
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 4abc30a6a5f..2d01f5c4a8b 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -327,11 +327,6 @@ enum {
OPC_MUL = 0x02 | OPC_SPECIAL2,
OPC_MSUB = 0x04 | OPC_SPECIAL2,
OPC_MSUBU = 0x05 | OPC_SPECIAL2,
- /* Loongson 2F */
- OPC_MULT_G_2F = 0x10 | OPC_SPECIAL2,
- OPC_DMULT_G_2F = 0x11 | OPC_SPECIAL2,
- OPC_MULTU_G_2F = 0x12 | OPC_SPECIAL2,
- OPC_DMULTU_G_2F = 0x13 | OPC_SPECIAL2,
/* Misc */
OPC_CLZ = 0x20 | OPC_SPECIAL2,
OPC_CLO = 0x21 | OPC_SPECIAL2,
@@ -360,12 +355,6 @@ enum {
OPC_RDHWR = 0x3B | OPC_SPECIAL3,
OPC_GINV = 0x3D | OPC_SPECIAL3,
- /* Loongson 2E */
- OPC_MULT_G_2E = 0x18 | OPC_SPECIAL3,
- OPC_MULTU_G_2E = 0x19 | OPC_SPECIAL3,
- OPC_DMULT_G_2E = 0x1C | OPC_SPECIAL3,
- OPC_DMULTU_G_2E = 0x1D | OPC_SPECIAL3,
-
/* MIPS DSP Load */
OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
/* MIPS DSP Arithmetic */
@@ -3572,46 +3561,6 @@ static void gen_cl(DisasContext *ctx, uint32_t opc,
}
}
-/* Godson integer instructions */
-static void gen_loongson_integer(DisasContext *ctx, uint32_t opc,
- int rd, int rs, int rt)
-{
- TCGv t0, t1;
-
- if (rd == 0) {
- /* Treat as NOP. */
- return;
- }
-
- t0 = tcg_temp_new();
- t1 = tcg_temp_new();
- gen_load_gpr(t0, rs);
- gen_load_gpr(t1, rt);
-
- switch (opc) {
- case OPC_MULT_G_2E:
- case OPC_MULT_G_2F:
- tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- break;
- case OPC_MULTU_G_2E:
- case OPC_MULTU_G_2F:
- tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- break;
-#if defined(TARGET_MIPS64)
- case OPC_DMULT_G_2E:
- case OPC_DMULT_G_2F:
- tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
- break;
- case OPC_DMULTU_G_2E:
- case OPC_DMULTU_G_2F:
- tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);
- break;
-#endif
- }
-}
-
/* Loongson multimedia instructions */
static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
{
@@ -13467,11 +13416,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MUL:
gen_arith(ctx, op1, rd, rs, rt);
break;
- case OPC_MULT_G_2F:
- case OPC_MULTU_G_2F:
- check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
- gen_loongson_integer(ctx, op1, rd, rs, rt);
- break;
case OPC_CLO:
case OPC_CLZ:
check_insn(ctx, ISA_MIPS_R1);
@@ -13496,11 +13440,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
break;
- case OPC_DMULT_G_2F:
- case OPC_DMULTU_G_2F:
- check_insn(ctx, INSN_LOONGSON2F | ASE_LEXT);
- gen_loongson_integer(ctx, op1, rd, rs, rt);
- break;
#endif
default: /* Invalid */
MIPS_INVAL("special2_legacy");
@@ -13633,10 +13572,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
- case OPC_MULT_G_2E:
- case OPC_MULTU_G_2E:
+ case OPC_MUL_PH_DSP:
/*
- * OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
+ * OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1.
*/
if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MUL_PH_DSP)) {
@@ -13667,8 +13605,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_reserved_instruction(ctx);
break;
}
- } else if (ctx->insn_flags & INSN_LOONGSON2E) {
- gen_loongson_integer(ctx, op1, rd, rs, rt);
} else {
gen_reserved_instruction(ctx);
}
@@ -13897,11 +13833,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DMULT_G_2E:
- case OPC_DMULTU_G_2E:
- check_insn(ctx, INSN_LOONGSON2E);
- gen_loongson_integer(ctx, op1, rd, rs, rt);
- break;
case OPC_ABSQ_S_QH_DSP:
op2 = MASK_ABSQ_S_QH(ctx->opcode);
switch (op2) {
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL 11/14] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2024-10-31 4:21 ` [PULL 10/14] target/mips: Convert Loongson [D]MULT[U].G " Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 12/14] target/mips: Introduce ase_3d_available() helper Philippe Mathieu-Daudé
` (3 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Richard Henderson, Pierrick Bouvier
Loongson fixed-point multiplies and divisions opcodes are
specific to 64-bit cores (Loongson-2 and Loongson-3 families).
Simplify by removing the 32-bit checks.
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241026175349.84523-10-philmd@linaro.org>
---
target/mips/tcg/loong_translate.c | 41 ++-----------------------------
1 file changed, 2 insertions(+), 39 deletions(-)
diff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c
index c02e60bb15b..a005c279a3e 100644
--- a/target/mips/tcg/loong_translate.c
+++ b/target/mips/tcg/loong_translate.c
@@ -31,13 +31,6 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,
TCGv t0, t1;
TCGLabel *l1, *l2, *l3;
- if (is_double) {
- if (TARGET_LONG_BITS != 64) {
- return false;
- }
- check_mips_64(s);
- }
-
if (rd == 0) {
/* Treat as NOP. */
return true;
@@ -61,8 +54,7 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,
tcg_gen_br(l3);
gen_set_label(l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS == 64
- ? LLONG_MIN : INT_MIN, l2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
tcg_gen_mov_tl(cpu_gpr[rd], t0);
@@ -93,13 +85,6 @@ static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,
TCGv t0, t1;
TCGLabel *l1, *l2;
- if (is_double) {
- if (TARGET_LONG_BITS != 64) {
- return false;
- }
- check_mips_64(s);
- }
-
if (rd == 0) {
/* Treat as NOP. */
return true;
@@ -147,13 +132,6 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,
TCGv t0, t1;
TCGLabel *l1, *l2, *l3;
- if (is_double) {
- if (TARGET_LONG_BITS != 64) {
- return false;
- }
- check_mips_64(s);
- }
-
if (rd == 0) {
/* Treat as NOP. */
return true;
@@ -173,8 +151,7 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,
tcg_gen_ext32u_tl(t1, t1);
}
tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
- tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double && TARGET_LONG_BITS == 64
- ? LLONG_MIN : INT_MIN, l2);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);
tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);
gen_set_label(l1);
tcg_gen_movi_tl(cpu_gpr[rd], 0);
@@ -205,13 +182,6 @@ static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt,
TCGv t0, t1;
TCGLabel *l1, *l2;
- if (is_double) {
- if (TARGET_LONG_BITS != 64) {
- return false;
- }
- check_mips_64(s);
- }
-
if (rd == 0) {
/* Treat as NOP. */
return true;
@@ -257,13 +227,6 @@ static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt,
{
TCGv t0, t1;
- if (is_double) {
- if (TARGET_LONG_BITS != 64) {
- return false;
- }
- check_mips_64(s);
- }
-
if (rd == 0) {
/* Treat as NOP. */
return true;
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL 12/14] target/mips: Introduce ase_3d_available() helper
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2024-10-31 4:21 ` [PULL 11/14] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 13/14] target/mips: Introduce disas_mt_available() Philippe Mathieu-Daudé
` (2 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Richard Henderson
Determine if the MIPS-3D ASE is implemented by checking
the state of the 3D bit in the FIR CP1 control register.
Remove the then unused ASE_MIPS3D definition.
Note, this allows using MIPS-3D on the mips64dspr2 model.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241021145832.34920-1-philmd@linaro.org>
---
target/mips/cpu.h | 6 ++++++
target/mips/mips-defs.h | 1 -
target/mips/tcg/translate.c | 8 ++++++--
target/mips/cpu-defs.c.inc | 4 ++--
target/mips/tcg/micromips_translate.c.inc | 5 ++++-
5 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index a4a46ebbe98..3dbfbfdb3d3 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1319,6 +1319,12 @@ bool cpu_type_supports_cps_smp(const char *cpu_type);
bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask);
bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
+/* Check presence of MIPS-3D ASE */
+static inline bool ase_3d_available(const CPUMIPSState *env)
+{
+ return env->active_fpu.fcr0 & (1 << FCR0_3D);
+}
+
/* Check presence of MSA implementation */
static inline bool ase_msa_available(CPUMIPSState *env)
{
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index a6cebe0265c..6b5cd0d8f53 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -26,7 +26,6 @@
* bits 24-39: MIPS ASEs
*/
#define ASE_MIPS16 0x0000000001000000ULL
-#define ASE_MIPS3D 0x0000000002000000ULL
#define ASE_MDMX 0x0000000004000000ULL
#define ASE_DSP 0x0000000008000000ULL
#define ASE_DSP_R2 0x0000000010000000ULL
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 2d01f5c4a8b..9a3ae10a919 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -14710,7 +14710,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
} else {
/* OPC_BC1ANY2 */
check_cop1x(ctx);
- check_insn(ctx, ASE_MIPS3D);
+ if (!ase_3d_available(env)) {
+ return false;
+ }
gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
(rt >> 2) & 0x7, imm << 2);
}
@@ -14725,7 +14727,9 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
check_cp1_enabled(ctx);
check_insn_opc_removed(ctx, ISA_MIPS_R6);
check_cop1x(ctx);
- check_insn(ctx, ASE_MIPS3D);
+ if (!ase_3d_available(env)) {
+ return false;
+ }
/* fall through */
case OPC_BC1:
check_cp1_enabled(ctx);
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 1ab026c57e7..09bd62d430a 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -663,7 +663,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 36,
- .insn_flags = CPU_MIPS64R1 | ASE_MIPS3D,
+ .insn_flags = CPU_MIPS64R1,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -692,7 +692,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42,
.PABITS = 36,
- .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
+ .insn_flags = CPU_MIPS64R2,
.mmu_type = MMU_TYPE_R4000,
},
{
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index 3cbf53bf2b3..c479bec1081 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -2484,7 +2484,10 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
mips32_op = OPC_BC1TANY4;
do_cp1mips3d:
check_cop1x(ctx);
- check_insn(ctx, ASE_MIPS3D);
+ if (!ase_3d_available(env)) {
+ gen_reserved_instruction(ctx);
+ break;
+ }
/* Fall through */
do_cp1branch:
if (env->CP0_Config1 & (1 << CP0C1_FP)) {
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL 13/14] target/mips: Introduce disas_mt_available()
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2024-10-31 4:21 ` [PULL 12/14] target/mips: Introduce ase_3d_available() helper Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-10-31 4:21 ` [PULL 14/14] target/mips: Remove unused CPUMIPSState::current_fpu field Philippe Mathieu-Daudé
2024-11-01 16:44 ` [PULL 00/14] MIPS patches for 2024-10-31 Peter Maydell
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Richard Henderson
Similarly to commit 17c2c320f3c ("Introduce ase_mt_available helper"),
introduce the disas_mt_available() one which takes a DisasContext
argument to determine whether Multi-Threading is available by
checking the MT bit of the CP0_Config3 register.
Remove the then unused ASE_MT definition.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241024195447.44600-1-philmd@linaro.org>
---
target/mips/mips-defs.h | 1 -
target/mips/tcg/translate.h | 5 ++
target/mips/tcg/translate.c | 136 ++++++++++++++++++------------------
target/mips/cpu-defs.c.inc | 4 +-
4 files changed, 75 insertions(+), 71 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 6b5cd0d8f53..9d4d292586c 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -30,7 +30,6 @@
#define ASE_DSP 0x0000000008000000ULL
#define ASE_DSP_R2 0x0000000010000000ULL
#define ASE_DSP_R3 0x0000000020000000ULL
-#define ASE_MT 0x0000000040000000ULL
#define ASE_SMARTMIPS 0x0000000080000000ULL
#define ASE_MICROMIPS 0x0000000100000000ULL
/*
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 23a489c0f38..1bf153d1838 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -231,6 +231,11 @@ bool decode_ext_octeon(DisasContext *ctx, uint32_t insn);
#endif
bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn);
+static inline bool disas_mt_available(DisasContext *ctx)
+{
+ return ctx->CP0_Config3 & (1 << CP0C3_MT);
+}
+
/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 9a3ae10a919..de7045874dd 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -5112,17 +5112,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Index";
break;
case CP0_REG00__MVPCONTROL:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_mvpcontrol(arg, tcg_env);
register_name = "MVPControl";
break;
case CP0_REG00__MVPCONF0:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_mvpconf0(arg, tcg_env);
register_name = "MVPConf0";
break;
case CP0_REG00__MVPCONF1:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_mvpconf1(arg, tcg_env);
register_name = "MVPConf1";
break;
@@ -5143,37 +5143,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Random";
break;
case CP0_REG01__VPECONTROL:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
register_name = "VPEControl";
break;
case CP0_REG01__VPECONF0:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
register_name = "VPEConf0";
break;
case CP0_REG01__VPECONF1:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
register_name = "VPEConf1";
break;
case CP0_REG01__YQMASK:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
case CP0_REG01__VPESCHEDULE:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case CP0_REG01__VPESCHEFBACK:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case CP0_REG01__VPEOPT:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
register_name = "VPEOpt";
break;
@@ -5200,37 +5200,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "EntryLo0";
break;
case CP0_REG02__TCSTATUS:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_tcstatus(arg, tcg_env);
register_name = "TCStatus";
break;
case CP0_REG02__TCBIND:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_tcbind(arg, tcg_env);
register_name = "TCBind";
break;
case CP0_REG02__TCRESTART:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_tcrestart(arg, tcg_env);
register_name = "TCRestart";
break;
case CP0_REG02__TCHALT:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_tchalt(arg, tcg_env);
register_name = "TCHalt";
break;
case CP0_REG02__TCCONTEXT:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_tccontext(arg, tcg_env);
register_name = "TCContext";
break;
case CP0_REG02__TCSCHEDULE:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_tcschedule(arg, tcg_env);
register_name = "TCSchedule";
break;
case CP0_REG02__TCSCHEFBACK:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_tcschefback(arg, tcg_env);
register_name = "TCScheFBack";
break;
@@ -5869,17 +5869,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Index";
break;
case CP0_REG00__MVPCONTROL:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_mvpcontrol(tcg_env, arg);
register_name = "MVPControl";
break;
case CP0_REG00__MVPCONF0:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
/* ignored */
register_name = "MVPConf0";
break;
case CP0_REG00__MVPCONF1:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
/* ignored */
register_name = "MVPConf1";
break;
@@ -5899,39 +5899,39 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Random";
break;
case CP0_REG01__VPECONTROL:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_vpecontrol(tcg_env, arg);
register_name = "VPEControl";
break;
case CP0_REG01__VPECONF0:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_vpeconf0(tcg_env, arg);
register_name = "VPEConf0";
break;
case CP0_REG01__VPECONF1:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_vpeconf1(tcg_env, arg);
register_name = "VPEConf1";
break;
case CP0_REG01__YQMASK:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_yqmask(tcg_env, arg);
register_name = "YQMask";
break;
case CP0_REG01__VPESCHEDULE:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case CP0_REG01__VPESCHEFBACK:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case CP0_REG01__VPEOPT:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_vpeopt(tcg_env, arg);
register_name = "VPEOpt";
break;
@@ -5946,37 +5946,37 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "EntryLo0";
break;
case CP0_REG02__TCSTATUS:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tcstatus(tcg_env, arg);
register_name = "TCStatus";
break;
case CP0_REG02__TCBIND:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tcbind(tcg_env, arg);
register_name = "TCBind";
break;
case CP0_REG02__TCRESTART:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tcrestart(tcg_env, arg);
register_name = "TCRestart";
break;
case CP0_REG02__TCHALT:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tchalt(tcg_env, arg);
register_name = "TCHalt";
break;
case CP0_REG02__TCCONTEXT:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tccontext(tcg_env, arg);
register_name = "TCContext";
break;
case CP0_REG02__TCSCHEDULE:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tcschedule(tcg_env, arg);
register_name = "TCSchedule";
break;
case CP0_REG02__TCSCHEFBACK:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tcschefback(tcg_env, arg);
register_name = "TCScheFBack";
break;
@@ -6619,17 +6619,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Index";
break;
case CP0_REG00__MVPCONTROL:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_mvpcontrol(arg, tcg_env);
register_name = "MVPControl";
break;
case CP0_REG00__MVPCONF0:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_mvpconf0(arg, tcg_env);
register_name = "MVPConf0";
break;
case CP0_REG00__MVPCONF1:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_mvpconf1(arg, tcg_env);
register_name = "MVPConf1";
break;
@@ -6650,40 +6650,40 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Random";
break;
case CP0_REG01__VPECONTROL:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
register_name = "VPEControl";
break;
case CP0_REG01__VPECONF0:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
register_name = "VPEConf0";
break;
case CP0_REG01__VPECONF1:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
register_name = "VPEConf1";
break;
case CP0_REG01__YQMASK:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
case CP0_REG01__VPESCHEDULE:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case CP0_REG01__VPESCHEFBACK:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
tcg_gen_ld_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case CP0_REG01__VPEOPT:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
register_name = "VPEOpt";
break;
@@ -6699,37 +6699,37 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "EntryLo0";
break;
case CP0_REG02__TCSTATUS:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_tcstatus(arg, tcg_env);
register_name = "TCStatus";
break;
case CP0_REG02__TCBIND:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mfc0_tcbind(arg, tcg_env);
register_name = "TCBind";
break;
case CP0_REG02__TCRESTART:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_dmfc0_tcrestart(arg, tcg_env);
register_name = "TCRestart";
break;
case CP0_REG02__TCHALT:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_dmfc0_tchalt(arg, tcg_env);
register_name = "TCHalt";
break;
case CP0_REG02__TCCONTEXT:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_dmfc0_tccontext(arg, tcg_env);
register_name = "TCContext";
break;
case CP0_REG02__TCSCHEDULE:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_dmfc0_tcschedule(arg, tcg_env);
register_name = "TCSchedule";
break;
case CP0_REG02__TCSCHEFBACK:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_dmfc0_tcschefback(arg, tcg_env);
register_name = "TCScheFBack";
break;
@@ -7336,17 +7336,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Index";
break;
case CP0_REG00__MVPCONTROL:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_mvpcontrol(tcg_env, arg);
register_name = "MVPControl";
break;
case CP0_REG00__MVPCONF0:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
/* ignored */
register_name = "MVPConf0";
break;
case CP0_REG00__MVPCONF1:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
/* ignored */
register_name = "MVPConf1";
break;
@@ -7366,39 +7366,39 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "Random";
break;
case CP0_REG01__VPECONTROL:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_vpecontrol(tcg_env, arg);
register_name = "VPEControl";
break;
case CP0_REG01__VPECONF0:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_vpeconf0(tcg_env, arg);
register_name = "VPEConf0";
break;
case CP0_REG01__VPECONF1:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_vpeconf1(tcg_env, arg);
register_name = "VPEConf1";
break;
case CP0_REG01__YQMASK:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_yqmask(tcg_env, arg);
register_name = "YQMask";
break;
case CP0_REG01__VPESCHEDULE:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case CP0_REG01__VPESCHEFBACK:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
tcg_gen_st_tl(arg, tcg_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case CP0_REG01__VPEOPT:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_vpeopt(tcg_env, arg);
register_name = "VPEOpt";
break;
@@ -7413,37 +7413,37 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
register_name = "EntryLo0";
break;
case CP0_REG02__TCSTATUS:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tcstatus(tcg_env, arg);
register_name = "TCStatus";
break;
case CP0_REG02__TCBIND:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tcbind(tcg_env, arg);
register_name = "TCBind";
break;
case CP0_REG02__TCRESTART:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tcrestart(tcg_env, arg);
register_name = "TCRestart";
break;
case CP0_REG02__TCHALT:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tchalt(tcg_env, arg);
register_name = "TCHalt";
break;
case CP0_REG02__TCCONTEXT:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tccontext(tcg_env, arg);
register_name = "TCContext";
break;
case CP0_REG02__TCSCHEDULE:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tcschedule(tcg_env, arg);
register_name = "TCSchedule";
break;
case CP0_REG02__TCSCHEFBACK:
- CP0_CHECK(ctx->insn_flags & ASE_MT);
+ CP0_CHECK(disas_mt_available(ctx));
gen_helper_mtc0_tcschefback(tcg_env, arg);
register_name = "TCScheFBack";
break;
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 09bd62d430a..922fc39138d 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -314,7 +314,7 @@ const mips_def_t mips_defs[] =
(0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
+ .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -543,7 +543,7 @@ const mips_def_t mips_defs[] =
.SEGBITS = 32,
.PABITS = 32,
.insn_flags = CPU_MIPS32R6 | ISA_NANOMIPS32 |
- ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | ASE_MT,
+ ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3,
.mmu_type = MMU_TYPE_R4000,
},
#if defined(TARGET_MIPS64)
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PULL 14/14] target/mips: Remove unused CPUMIPSState::current_fpu field
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2024-10-31 4:21 ` [PULL 13/14] target/mips: Introduce disas_mt_available() Philippe Mathieu-Daudé
@ 2024-10-31 4:21 ` Philippe Mathieu-Daudé
2024-11-01 16:44 ` [PULL 00/14] MIPS patches for 2024-10-31 Peter Maydell
14 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-10-31 4:21 UTC (permalink / raw)
To: qemu-devel
Cc: Philippe Mathieu-Daudé, Pierrick Bouvier, Richard Henderson
The 'current_fpu' field is unused since commit f01be154589
("Move the active FPU registers into env again, and use more
TCG registers to access them").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241021151253.36443-1-philmd@linaro.org>
---
target/mips/cpu.h | 1 -
target/mips/sysemu/machine.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 3dbfbfdb3d3..f6877ece8b4 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -530,7 +530,6 @@ typedef struct CPUArchState {
CPUMIPSFPUContext active_fpu;
uint32_t current_tc;
- uint32_t current_fpu;
uint32_t SEGBITS;
uint32_t PABITS;
diff --git a/target/mips/sysemu/machine.c b/target/mips/sysemu/machine.c
index 91cd9f19002..8af11fd896b 100644
--- a/target/mips/sysemu/machine.c
+++ b/target/mips/sysemu/machine.c
@@ -242,7 +242,7 @@ const VMStateDescription vmstate_mips_cpu = {
/* CPU metastate */
VMSTATE_UINT32(env.current_tc, MIPSCPU),
- VMSTATE_UINT32(env.current_fpu, MIPSCPU),
+ VMSTATE_UNUSED(sizeof(uint32_t)), /* was current_fpu */
VMSTATE_INT32(env.error_code, MIPSCPU),
VMSTATE_UINTTL(env.btarget, MIPSCPU),
VMSTATE_UINTTL(env.bcond, MIPSCPU),
--
2.45.2
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PULL 00/14] MIPS patches for 2024-10-31
2024-10-31 4:21 [PULL 00/14] MIPS patches for 2024-10-31 Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2024-10-31 4:21 ` [PULL 14/14] target/mips: Remove unused CPUMIPSState::current_fpu field Philippe Mathieu-Daudé
@ 2024-11-01 16:44 ` Peter Maydell
2024-11-04 10:46 ` Philippe Mathieu-Daudé
14 siblings, 1 reply; 19+ messages in thread
From: Peter Maydell @ 2024-11-01 16:44 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel
On Thu, 31 Oct 2024 at 04:22, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>
> The following changes since commit 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29:
>
> Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-10-29 14:00:43 +0000)
>
> are available in the Git repository at:
>
> https://github.com/philmd/qemu.git tags/mips-20241031
>
> for you to fetch changes up to dcc3c68c844fef7bc018ab53f0993b8d44137d77:
>
> target/mips: Remove unused CPUMIPSState::current_fpu field (2024-10-31 00:48:45 -0300)
>
> ----------------------------------------------------------------
> MIPS patches queue
>
> - Migrate missing CP0 TLB MemoryMapID register (Yongbok)
> - Enable MSA ASE for mips32r6-generic (Aleksandar)
> - Convert Loongson LEXT opcodes to decodetree (Phil)
> - Introduce ase_3d_available and disas_mt_available helpers (Phil)
>
> ----------------------------------------------------------------
Hi; it looks like this breaks the foolong2e functional test:
https://gitlab.com/qemu-project/qemu/-/jobs/8249048723
12/15 qemu:func-thorough+func-mips64el-thorough+thorough /
func-mips64el-mips64el_fuloong2e ERROR 2.54s
Guest kernel panics rather than booting.
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PULL 00/14] MIPS patches for 2024-10-31
2024-11-01 16:44 ` [PULL 00/14] MIPS patches for 2024-10-31 Peter Maydell
@ 2024-11-04 10:46 ` Philippe Mathieu-Daudé
2024-11-04 11:32 ` BALATON Zoltan
0 siblings, 1 reply; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-11-04 10:46 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel, Huacai Chen, Jiaxun Yang, BALATON Zoltan
Hi,
TL;DR: I will repost the PR will the typo fixed.
On 1/11/24 13:44, Peter Maydell wrote:
> On Thu, 31 Oct 2024 at 04:22, Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
>>
>> The following changes since commit 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29:
>>
>> Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging (2024-10-29 14:00:43 +0000)
>>
>> are available in the Git repository at:
>>
>> https://github.com/philmd/qemu.git tags/mips-20241031
>>
>> for you to fetch changes up to dcc3c68c844fef7bc018ab53f0993b8d44137d77:
>>
>> target/mips: Remove unused CPUMIPSState::current_fpu field (2024-10-31 00:48:45 -0300)
>>
>> ----------------------------------------------------------------
>> MIPS patches queue
>>
>> - Migrate missing CP0 TLB MemoryMapID register (Yongbok)
>> - Enable MSA ASE for mips32r6-generic (Aleksandar)
>> - Convert Loongson LEXT opcodes to decodetree (Phil)
>> - Introduce ase_3d_available and disas_mt_available helpers (Phil)
>>
>> ----------------------------------------------------------------
>
> Hi; it looks like this breaks the foolong2e functional test:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/8249048723
>
> 12/15 qemu:func-thorough+func-mips64el-thorough+thorough /
> func-mips64el-mips64el_fuloong2e ERROR 2.54s
>
> Guest kernel panics rather than booting.
Oops. At least we have a test. I suppose I missed it because the job
isn't run by default and has been renamed due to the avocado ->
functional conversion.
The bug is a due to a typo:
-- >8 --
--- a/target/mips/tcg/loong_translate.c
+++ b/target/mips/tcg/loong_translate.c
@@ -68,7 +68,7 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd,
int rs, int rt)
static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
{
- return gen_lext_DIV_G(s, a->rt, a->rs, a->rd);
+ return gen_lext_DIV_G(s, a->rd, a->rs, a->rt);
}
---
But then the test fail later:
$ ninja qemu-system-mips64el && ./qemu-system-mips64el -kernel
boot/vmlinux-3.16.0-6-loongson-2e -machine fuloong2e -append
'console=ttyS0' -serial mon:stdio -d int -trace pci\*
...
[ 0.000000] Kernel command line: console=ttyS0
[ 0.436000] PCI host bridge to bus 0000:00
[ 0.436000] pci_bus 0000:00: root bus resource [mem
0x14000000-0x1c000000]
[ 0.440000] pci_bus 0000:00: root bus resource [io 0x4000-0xffff]
[ 0.440000] pci_bus 0000:00: No busn resource found for root bus,
will use [bus 00-ff]
...
pci_cfg_read ati-vga 00:06.0 @0x0 -> 0x51591002
pci_cfg_read ati-vga 00:06.0 @0xc -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x8 -> 0x3000000
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x3c -> 0x100
pci_cfg_read ati-vga 00:06.0 @0x3c -> 0x100
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x10 -> 0x8
pci_cfg_write ati-vga 00:06.0 @0x10 <- 0xffffffff
pci_cfg_read ati-vga 00:06.0 @0x10 -> 0xff000008
pci_cfg_write ati-vga 00:06.0 @0x10 <- 0x8
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x14 -> 0x1
pci_cfg_write ati-vga 00:06.0 @0x14 <- 0xffffffff
pci_cfg_read ati-vga 00:06.0 @0x14 -> 0xffffff01
pci_cfg_write ati-vga 00:06.0 @0x14 <- 0x1
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x18 -> 0x0
pci_cfg_write ati-vga 00:06.0 @0x18 <- 0xffffffff
pci_cfg_read ati-vga 00:06.0 @0x18 -> 0xffffc000
pci_cfg_write ati-vga 00:06.0 @0x18 <- 0x0
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x1c -> 0x0
pci_cfg_write ati-vga 00:06.0 @0x1c <- 0xffffffff
pci_cfg_read ati-vga 00:06.0 @0x1c -> 0x0
pci_cfg_write ati-vga 00:06.0 @0x1c <- 0x0
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x20 -> 0x0
pci_cfg_write ati-vga 00:06.0 @0x20 <- 0xffffffff
pci_cfg_read ati-vga 00:06.0 @0x20 -> 0x0
pci_cfg_write ati-vga 00:06.0 @0x20 <- 0x0
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x24 -> 0x0
pci_cfg_write ati-vga 00:06.0 @0x24 <- 0xffffffff
pci_cfg_read ati-vga 00:06.0 @0x24 -> 0x0
pci_cfg_write ati-vga 00:06.0 @0x24 <- 0x0
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x30 -> 0x0
pci_cfg_write ati-vga 00:06.0 @0x30 <- 0xfffff800
pci_cfg_read ati-vga 00:06.0 @0x30 -> 0xffff0000
pci_cfg_write ati-vga 00:06.0 @0x30 <- 0x0
pci_cfg_read ati-vga 00:06.0 @0x2c -> 0x11001af4
pci_cfg_read ati-vga 00:06.0 @0x2c -> 0x11001af4
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
[ 0.464000] vgaarb: device added:
PCI:0000:00:06.0,decodes=io+mem,owns=none,locks=none
...
[ 0.472000] pci 0000:00:06.0: BAR 0: assigned [mem
0x14000000-0x14ffffff pref]
pci_cfg_write ati-vga 00:06.0 @0x10 <- 0x14000008
pci_cfg_read ati-vga 00:06.0 @0x10 -> 0x14000008
[ 0.472000] pci 0000:00:07.0: BAR 6: assigned [mem
0x15000000-0x1503ffff pref]
[ 0.472000] pci 0000:00:06.0: BAR 6: assigned [mem
0x15040000-0x1504ffff pref]
[ 0.472000] pci 0000:00:06.0: BAR 2: assigned [mem 0x15050000-0x15053fff]
pci_cfg_write ati-vga 00:06.0 @0x18 <- 0x15050000
pci_cfg_read ati-vga 00:06.0 @0x18 -> 0x15050000
[ 0.472000] pci 0000:00:05.5: BAR 0: assigned [io 0x4000-0x40ff]
...
[ 0.476000] pci 0000:00:06.0: BAR 1: assigned [io 0x4400-0x44ff]
pci_cfg_write ati-vga 00:06.0 @0x14 <- 0x4401
pci_cfg_read ati-vga 00:06.0 @0x14 -> 0x4401
...
pci_cfg_read ati-vga 00:06.0 @0x3c -> 0x100
pci_cfg_read ati-vga 00:06.0 @0x3c -> 0x100
pci_cfg_write ati-vga 00:06.0 @0x3c <- 0x13a
...
pci_cfg_read ati-vga 00:06.0 @0xc -> 0x0
...
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
[ 0.864000] PCI: Enabling device 0000:00:06.0 (0000 -> 0003)
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
pci_cfg_write ati-vga 00:06.0 @0x4 <- 0x3
pci_update_mappings_add ati-vga 00:06.0 0,0x14000000+0x1000000
pci_update_mappings_add ati-vga 00:06.0 1,0x4400+0x100
pci_update_mappings_add ati-vga 00:06.0 2,0x15050000+0x4000
pci_cfg_read ati-vga 00:06.0 @0x3c -> 0x13a
pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x3
do_raise_exception_err: 28 (data bus error) 0
mips_cpu_do_interrupt enter: PC ffffffff8045aed8 EPC ffffffff8043ae88
data bus error exception
mips_cpu_do_interrupt: PC ffffffff80000180 EPC ffffffff8045aed8 cause 7
S 1400a4e3 C 0000001c A c000000000010000 D 0000000000000000
[ 0.868000] Data bus error, epc == ffffffff8045aed8, ra ==
ffffffff8045aeb8
[ 0.868000] Oops[#1]:
[ 0.868000] CPU: 0 PID: 1 Comm: swapper Not tainted
3.16.0-6-loongson-2e #1 Debian 3.16.56-1+deb8u1
[ 0.868000] task: 980000000e06f580 ti: 980000000e078000 task.ti:
980000000e078000
[ 0.868000] $ 0 : 0000000000000000 ffffffff80428db0
9000000000000000 0000000015050000
[ 0.868000] $ 4 : 9000000015050000 ffffffff80430000
0000000015053fff 0000000000000070
[ 0.868000] $ 8 : 0000000000000000 ffffffff8079b190
0000000000000001 fffffffffffffff8
[ 0.868000] $12 : 0000000000000000 ffffffff803fd67c
0000000000000000 0000000000000082
[ 0.868000] $16 : 980000000e278000 980000000e336000
980000000e336428 0000000000000000
[ 0.868000] $20 : ffffffff8087f918 0000000000000000
ffffffff80929cf0 ffffffff80800000
[ 0.868000] $24 : 0000000000000018 0000000000000000
[ 0.868000] $28 : 980000000e078000 980000000e07bbc0
0000000000000074 ffffffff8045aeb8
[ 0.868000] Hi : 0000000000d2f000
[ 0.868000] Lo : 0000000000fa7d00
[ 0.868000] epc : ffffffff8045aed8 radeonfb_pci_register+0x1b0/0x1ad0
[ 0.868000] Not tainted
[ 0.868000] ra : ffffffff8045aeb8 radeonfb_pci_register+0x190/0x1ad0
[ 0.868000] Status: 1400a4e3 KX SX UX KERNEL EXL IE
[ 0.868000] Cause : 0000001c
[ 0.868000] PrId : 00006302 (ICT Loongson-2)
[ 0.868000] Modules linked in:
[ 0.868000] Process swapper (pid: 1, threadinfo=980000000e078000,
task=980000000e06f580, tls=0000000000000000)
[ 0.868000] Stack : 980000000e336748 980000000e278090
000000001400a4e1 ffffffff8087f670
ffffffff8087f918 0000000000000000 980000000e278090 ffffffff8087f6d8
980000000e278000 ffffffff8087f670 ffffffff8087f918 0000000000000000
ffffffff80929cf0 ffffffff80800000 0000000000000074 ffffffff8042e718
980000000e278090 ffffffff809b0000 980000000e2780f0 ffffffff8087f6d8
ffffffff809b0000 ffffffff804a3dcc 980000000e355380 980000000e278090
ffffffff8087f6d8 980000000e2780f0 0000000000000000 ffffffff80810000
0000000000000000 ffffffff804a4238 0000000000000000 ffffffff8087f6d8
ffffffff804a4168 ffffffff804a1a04 980000000e1c6090 980000000e1cbde0
ffffffff8087f6d8 980000000e355380 ffffffff8087e8f0 ffffffff804a3218
...
[ 0.868000] Call Trace:
[ 0.868000] [<ffffffff8045aed8>] radeonfb_pci_register+0x1b0/0x1ad0
[ 0.868000] [<ffffffff8042e718>] pci_device_probe+0xb8/0x130
[ 0.868000] [<ffffffff804a3dcc>] driver_probe_device+0xdc/0x400
[ 0.868000] [<ffffffff804a4238>] __driver_attach+0xd0/0xd8
[ 0.868000] [<ffffffff804a1a04>] bus_for_each_dev+0x7c/0xc8
[ 0.868000] [<ffffffff804a3218>] bus_add_driver+0x1a0/0x288
[ 0.868000] [<ffffffff804a4c10>] driver_register+0x90/0x138
[ 0.868000] [<ffffffff808e2444>] radeonfb_init+0x60/0x230
[ 0.868000] [<ffffffff801005c0>] do_one_initcall+0x110/0x220
[ 0.868000] [<ffffffff808b8e3c>] kernel_init_freeable+0x194/0x250
[ 0.868000] [<ffffffff80661f98>] kernel_init+0x20/0x118
[ 0.868000] [<ffffffff80103ed0>] ret_from_kernel_thread+0x14/0x1c
[ 0.868000]
[ 0.868000]
Code: 0082202d 108005ae fe440368 <8c850148> 924207d8 00052c00
0005283c 0005283e fe450378
[ 0.888000] ---[ end trace 2fdf3be6a36f9b46 ]---
[ 0.892000] Kernel panic - not syncing: Attempted to kill init!
exitcode=0x0000000b
[ 0.892000]
[ 0.892000] ---[ end Kernel panic - not syncing: Attempted to kill
init! exitcode=0x0000000b
[ 0.892000]
I don't recall this failure. Zoltan, does it ring a bell?
Anyway I'll open a gitlab issue to track it, and will repost the
PR will the typo fixed.
Regards,
Phil.
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PULL 00/14] MIPS patches for 2024-10-31
2024-11-04 10:46 ` Philippe Mathieu-Daudé
@ 2024-11-04 11:32 ` BALATON Zoltan
0 siblings, 0 replies; 19+ messages in thread
From: BALATON Zoltan @ 2024-11-04 11:32 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, qemu-devel, Huacai Chen, Jiaxun Yang
[-- Attachment #1: Type: text/plain, Size: 10991 bytes --]
On Mon, 4 Nov 2024, Philippe Mathieu-Daudé wrote:
> Hi,
>
> TL;DR: I will repost the PR will the typo fixed.
>
> On 1/11/24 13:44, Peter Maydell wrote:
>> On Thu, 31 Oct 2024 at 04:22, Philippe Mathieu-Daudé <philmd@linaro.org>
>> wrote:
>>>
>>> The following changes since commit
>>> 58d49b5895f2e0b5cfe4b2901bf24f3320b74f29:
>>>
>>> Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into
>>> staging (2024-10-29 14:00:43 +0000)
>>>
>>> are available in the Git repository at:
>>>
>>> https://github.com/philmd/qemu.git tags/mips-20241031
>>>
>>> for you to fetch changes up to dcc3c68c844fef7bc018ab53f0993b8d44137d77:
>>>
>>> target/mips: Remove unused CPUMIPSState::current_fpu field (2024-10-31
>>> 00:48:45 -0300)
>>>
>>> ----------------------------------------------------------------
>>> MIPS patches queue
>>>
>>> - Migrate missing CP0 TLB MemoryMapID register (Yongbok)
>>> - Enable MSA ASE for mips32r6-generic (Aleksandar)
>>> - Convert Loongson LEXT opcodes to decodetree (Phil)
>>> - Introduce ase_3d_available and disas_mt_available helpers (Phil)
>>>
>>> ----------------------------------------------------------------
>>
>> Hi; it looks like this breaks the foolong2e functional test:
>>
>> https://gitlab.com/qemu-project/qemu/-/jobs/8249048723
>>
>> 12/15 qemu:func-thorough+func-mips64el-thorough+thorough /
>> func-mips64el-mips64el_fuloong2e ERROR 2.54s
>>
>> Guest kernel panics rather than booting.
>
> Oops. At least we have a test. I suppose I missed it because the job
> isn't run by default and has been renamed due to the avocado ->
> functional conversion.
>
> The bug is a due to a typo:
>
> -- >8 --
> --- a/target/mips/tcg/loong_translate.c
> +++ b/target/mips/tcg/loong_translate.c
> @@ -68,7 +68,7 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs,
> int rt)
>
> static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)
> {
> - return gen_lext_DIV_G(s, a->rt, a->rs, a->rd);
> + return gen_lext_DIV_G(s, a->rd, a->rs, a->rt);
> }
> ---
>
> But then the test fail later:
>
> $ ninja qemu-system-mips64el && ./qemu-system-mips64el -kernel
> boot/vmlinux-3.16.0-6-loongson-2e -machine fuloong2e -append 'console=ttyS0'
> -serial mon:stdio -d int -trace pci\*
> ...
> [ 0.000000] Kernel command line: console=ttyS0
> [ 0.436000] PCI host bridge to bus 0000:00
> [ 0.436000] pci_bus 0000:00: root bus resource [mem 0x14000000-0x1c000000]
> [ 0.440000] pci_bus 0000:00: root bus resource [io 0x4000-0xffff]
> [ 0.440000] pci_bus 0000:00: No busn resource found for root bus, will use
> [bus 00-ff]
> ...
> pci_cfg_read ati-vga 00:06.0 @0x0 -> 0x51591002
> pci_cfg_read ati-vga 00:06.0 @0xc -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x8 -> 0x3000000
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x3c -> 0x100
> pci_cfg_read ati-vga 00:06.0 @0x3c -> 0x100
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x10 -> 0x8
> pci_cfg_write ati-vga 00:06.0 @0x10 <- 0xffffffff
> pci_cfg_read ati-vga 00:06.0 @0x10 -> 0xff000008
> pci_cfg_write ati-vga 00:06.0 @0x10 <- 0x8
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x14 -> 0x1
> pci_cfg_write ati-vga 00:06.0 @0x14 <- 0xffffffff
> pci_cfg_read ati-vga 00:06.0 @0x14 -> 0xffffff01
> pci_cfg_write ati-vga 00:06.0 @0x14 <- 0x1
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x18 -> 0x0
> pci_cfg_write ati-vga 00:06.0 @0x18 <- 0xffffffff
> pci_cfg_read ati-vga 00:06.0 @0x18 -> 0xffffc000
> pci_cfg_write ati-vga 00:06.0 @0x18 <- 0x0
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x1c -> 0x0
> pci_cfg_write ati-vga 00:06.0 @0x1c <- 0xffffffff
> pci_cfg_read ati-vga 00:06.0 @0x1c -> 0x0
> pci_cfg_write ati-vga 00:06.0 @0x1c <- 0x0
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x20 -> 0x0
> pci_cfg_write ati-vga 00:06.0 @0x20 <- 0xffffffff
> pci_cfg_read ati-vga 00:06.0 @0x20 -> 0x0
> pci_cfg_write ati-vga 00:06.0 @0x20 <- 0x0
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x24 -> 0x0
> pci_cfg_write ati-vga 00:06.0 @0x24 <- 0xffffffff
> pci_cfg_read ati-vga 00:06.0 @0x24 -> 0x0
> pci_cfg_write ati-vga 00:06.0 @0x24 <- 0x0
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x30 -> 0x0
> pci_cfg_write ati-vga 00:06.0 @0x30 <- 0xfffff800
> pci_cfg_read ati-vga 00:06.0 @0x30 -> 0xffff0000
> pci_cfg_write ati-vga 00:06.0 @0x30 <- 0x0
> pci_cfg_read ati-vga 00:06.0 @0x2c -> 0x11001af4
> pci_cfg_read ati-vga 00:06.0 @0x2c -> 0x11001af4
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> [ 0.464000] vgaarb: device added:
> PCI:0000:00:06.0,decodes=io+mem,owns=none,locks=none
> ...
> [ 0.472000] pci 0000:00:06.0: BAR 0: assigned [mem 0x14000000-0x14ffffff
> pref]
> pci_cfg_write ati-vga 00:06.0 @0x10 <- 0x14000008
> pci_cfg_read ati-vga 00:06.0 @0x10 -> 0x14000008
> [ 0.472000] pci 0000:00:07.0: BAR 6: assigned [mem 0x15000000-0x1503ffff
> pref]
> [ 0.472000] pci 0000:00:06.0: BAR 6: assigned [mem 0x15040000-0x1504ffff
> pref]
> [ 0.472000] pci 0000:00:06.0: BAR 2: assigned [mem 0x15050000-0x15053fff]
> pci_cfg_write ati-vga 00:06.0 @0x18 <- 0x15050000
> pci_cfg_read ati-vga 00:06.0 @0x18 -> 0x15050000
> [ 0.472000] pci 0000:00:05.5: BAR 0: assigned [io 0x4000-0x40ff]
> ...
> [ 0.476000] pci 0000:00:06.0: BAR 1: assigned [io 0x4400-0x44ff]
> pci_cfg_write ati-vga 00:06.0 @0x14 <- 0x4401
> pci_cfg_read ati-vga 00:06.0 @0x14 -> 0x4401
> ...
> pci_cfg_read ati-vga 00:06.0 @0x3c -> 0x100
> pci_cfg_read ati-vga 00:06.0 @0x3c -> 0x100
> pci_cfg_write ati-vga 00:06.0 @0x3c <- 0x13a
> ...
> pci_cfg_read ati-vga 00:06.0 @0xc -> 0x0
> ...
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> [ 0.864000] PCI: Enabling device 0000:00:06.0 (0000 -> 0003)
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x0
> pci_cfg_write ati-vga 00:06.0 @0x4 <- 0x3
> pci_update_mappings_add ati-vga 00:06.0 0,0x14000000+0x1000000
> pci_update_mappings_add ati-vga 00:06.0 1,0x4400+0x100
> pci_update_mappings_add ati-vga 00:06.0 2,0x15050000+0x4000
> pci_cfg_read ati-vga 00:06.0 @0x3c -> 0x13a
> pci_cfg_read ati-vga 00:06.0 @0x4 -> 0x3
> do_raise_exception_err: 28 (data bus error) 0
> mips_cpu_do_interrupt enter: PC ffffffff8045aed8 EPC ffffffff8043ae88 data
> bus error exception
> mips_cpu_do_interrupt: PC ffffffff80000180 EPC ffffffff8045aed8 cause 7
> S 1400a4e3 C 0000001c A c000000000010000 D 0000000000000000
> [ 0.868000] Data bus error, epc == ffffffff8045aed8, ra ==
> ffffffff8045aeb8
> [ 0.868000] Oops[#1]:
> [ 0.868000] CPU: 0 PID: 1 Comm: swapper Not tainted 3.16.0-6-loongson-2e
> #1 Debian 3.16.56-1+deb8u1
> [ 0.868000] task: 980000000e06f580 ti: 980000000e078000 task.ti:
> 980000000e078000
> [ 0.868000] $ 0 : 0000000000000000 ffffffff80428db0 9000000000000000
> 0000000015050000
> [ 0.868000] $ 4 : 9000000015050000 ffffffff80430000 0000000015053fff
> 0000000000000070
> [ 0.868000] $ 8 : 0000000000000000 ffffffff8079b190 0000000000000001
> fffffffffffffff8
> [ 0.868000] $12 : 0000000000000000 ffffffff803fd67c 0000000000000000
> 0000000000000082
> [ 0.868000] $16 : 980000000e278000 980000000e336000 980000000e336428
> 0000000000000000
> [ 0.868000] $20 : ffffffff8087f918 0000000000000000 ffffffff80929cf0
> ffffffff80800000
> [ 0.868000] $24 : 0000000000000018 0000000000000000
> [ 0.868000] $28 : 980000000e078000 980000000e07bbc0 0000000000000074
> ffffffff8045aeb8
> [ 0.868000] Hi : 0000000000d2f000
> [ 0.868000] Lo : 0000000000fa7d00
> [ 0.868000] epc : ffffffff8045aed8 radeonfb_pci_register+0x1b0/0x1ad0
> [ 0.868000] Not tainted
> [ 0.868000] ra : ffffffff8045aeb8 radeonfb_pci_register+0x190/0x1ad0
> [ 0.868000] Status: 1400a4e3 KX SX UX KERNEL EXL IE
> [ 0.868000] Cause : 0000001c
> [ 0.868000] PrId : 00006302 (ICT Loongson-2)
> [ 0.868000] Modules linked in:
> [ 0.868000] Process swapper (pid: 1, threadinfo=980000000e078000,
> task=980000000e06f580, tls=0000000000000000)
> [ 0.868000] Stack : 980000000e336748 980000000e278090 000000001400a4e1
> ffffffff8087f670
> ffffffff8087f918 0000000000000000 980000000e278090 ffffffff8087f6d8
> 980000000e278000 ffffffff8087f670 ffffffff8087f918 0000000000000000
> ffffffff80929cf0 ffffffff80800000 0000000000000074 ffffffff8042e718
> 980000000e278090 ffffffff809b0000 980000000e2780f0 ffffffff8087f6d8
> ffffffff809b0000 ffffffff804a3dcc 980000000e355380 980000000e278090
> ffffffff8087f6d8 980000000e2780f0 0000000000000000 ffffffff80810000
> 0000000000000000 ffffffff804a4238 0000000000000000 ffffffff8087f6d8
> ffffffff804a4168 ffffffff804a1a04 980000000e1c6090 980000000e1cbde0
> ffffffff8087f6d8 980000000e355380 ffffffff8087e8f0 ffffffff804a3218
> ...
> [ 0.868000] Call Trace:
> [ 0.868000] [<ffffffff8045aed8>] radeonfb_pci_register+0x1b0/0x1ad0
> [ 0.868000] [<ffffffff8042e718>] pci_device_probe+0xb8/0x130
> [ 0.868000] [<ffffffff804a3dcc>] driver_probe_device+0xdc/0x400
> [ 0.868000] [<ffffffff804a4238>] __driver_attach+0xd0/0xd8
> [ 0.868000] [<ffffffff804a1a04>] bus_for_each_dev+0x7c/0xc8
> [ 0.868000] [<ffffffff804a3218>] bus_add_driver+0x1a0/0x288
> [ 0.868000] [<ffffffff804a4c10>] driver_register+0x90/0x138
> [ 0.868000] [<ffffffff808e2444>] radeonfb_init+0x60/0x230
> [ 0.868000] [<ffffffff801005c0>] do_one_initcall+0x110/0x220
> [ 0.868000] [<ffffffff808b8e3c>] kernel_init_freeable+0x194/0x250
> [ 0.868000] [<ffffffff80661f98>] kernel_init+0x20/0x118
> [ 0.868000] [<ffffffff80103ed0>] ret_from_kernel_thread+0x14/0x1c
> [ 0.868000]
> [ 0.868000]
> Code: 0082202d 108005ae fe440368 <8c850148> 924207d8 00052c00 0005283c
> 0005283e fe450378
> [ 0.888000] ---[ end trace 2fdf3be6a36f9b46 ]---
> [ 0.892000] Kernel panic - not syncing: Attempted to kill init!
> exitcode=0x0000000b
> [ 0.892000]
> [ 0.892000] ---[ end Kernel panic - not syncing: Attempted to kill init!
> exitcode=0x0000000b
> [ 0.892000]
>
> I don't recall this failure. Zoltan, does it ring a bell?
> Anyway I'll open a gitlab issue to track it, and will repost the
> PR will the typo fixed.
Hello,
No, I haven't seen this before. There were no changes to ati-vga for a
long time so it's unlikely it was broken by that recently. The ati-vga
does have a 60Hz vblank interrupt added in b7105d280cab so maybe you could
try disabling that for testing to see if this has anything to do with the
above but if it broke recently maybe it's more related to some MIPS change
than ati-vga.
Regards,
BALATON Zoltan
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