From: Tao Su <tao1.su@linux.intel.com>
To: qemu-devel@nongnu.org
Cc: pbonzini@redhat.com, mtosatti@redhat.com, xiaoyao.li@intel.com,
zhao1.liu@intel.com, xuelian.guo@intel.com,
tao1.su@linux.intel.com
Subject: [PATCH v3 3/8] target/i386: return bool from x86_cpu_filter_features
Date: Thu, 31 Oct 2024 16:52:28 +0800 [thread overview]
Message-ID: <20241031085233.425388-4-tao1.su@linux.intel.com> (raw)
In-Reply-To: <20241031085233.425388-1-tao1.su@linux.intel.com>
From: Paolo Bonzini <pbonzini@redhat.com>
Prepare for filtering non-boolean features such as AVX10 version.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
---
target/i386/cpu.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f8b5c28caf..8fbbf1fd9e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5818,7 +5818,7 @@ static void x86_cpu_parse_featurestr(const char *typename, char *features,
}
}
-static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
+static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose);
/* Build a list with the name of all features on a feature word array */
static void x86_cpu_list_feature_names(FeatureWordArray features,
@@ -7523,9 +7523,9 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
* Finishes initialization of CPUID data, filters CPU feature
* words based on host availability of each feature.
*
- * Returns: 0 if all flags are supported by the host, non-zero otherwise.
+ * Returns: true if any flag is not supported by the host, false otherwise.
*/
-static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
+static bool x86_cpu_filter_features(X86CPU *cpu, bool verbose)
{
CPUX86State *env = &cpu->env;
FeatureWord w;
@@ -7577,6 +7577,8 @@ static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
}
}
+
+ return x86_cpu_have_filtered_features(cpu);
}
static void x86_cpu_hyperv_realize(X86CPU *cpu)
@@ -7674,14 +7676,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
}
}
- x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
-
- if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
- error_setg(&local_err,
- accel_uses_host_cpuid() ?
+ if (x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid)) {
+ if (cpu->enforce_cpuid) {
+ error_setg(&local_err,
+ accel_uses_host_cpuid() ?
"Host doesn't support requested features" :
"TCG doesn't support requested features");
- goto out;
+ goto out;
+ }
}
/* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
--
2.34.1
next prev parent reply other threads:[~2024-10-31 9:00 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-31 8:52 [PATCH v3 0/8] Add AVX10.1 CPUID support and GraniteRapids-v2 model Tao Su
2024-10-31 8:52 ` [PATCH v3 1/8] target/i386: cpu: set correct supported XCR0 features for TCG Tao Su
2024-10-31 8:52 ` [PATCH v3 2/8] target/i386: do not rely on ExtSaveArea for accelerator-supported XCR0 bits Tao Su
2024-10-31 8:52 ` Tao Su [this message]
2024-10-31 8:52 ` [PATCH v3 4/8] target/i386: add AVX10 feature and AVX10 version property Tao Su
2024-10-31 16:52 ` Zhao Liu
2024-11-01 2:09 ` Tao Su
2024-11-01 2:44 ` Zhao Liu
2024-11-01 2:31 ` Tao Su
2024-11-01 2:57 ` Zhao Liu
2024-10-31 8:52 ` [PATCH v3 5/8] target/i386: add CPUID.24 features for AVX10 Tao Su
2024-10-31 8:52 ` [PATCH v3 6/8] target/i386: Add feature dependencies " Tao Su
2024-10-31 8:52 ` [PATCH v3 7/8] target/i386: Add AVX512 state when AVX10 is supported Tao Su
2024-10-31 8:52 ` [PATCH v3 8/8] target/i386: Introduce GraniteRapids-v2 model Tao Su
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