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Date: Mon, 4 Nov 2024 21:51:04 +0000 Message-Id: <20241104-b4-ctr_upstream_v3-v3-0-32fd3c48205f@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Change-ID: 20241029-b4-ctr_upstream_v3-7ab764c68bf1 X-Mailer: b4 0.14.2 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=rkanwal@rivosinc.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series enables Control Transfer Records extension support on riscv=0D platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.=0D The Extension has been stable and this series is based on v1.0_rc6 [0]=0D =0D CTR extension depends on both the implementation of S-mode and Sscsrind=0D extension v1.0.0 [1]. CTR access ctrsource, ctrtartget and ctrdata CSRs usi= ng=0D sscsrind extension.=0D =0D The series is based on Smcdeleg/Ssccfg counter delegation extension [2]=0D patches [3]. CTR itself doesn't depend on counter delegation support. This= =0D rebase is basically to include the Smcsrind patches.=0D =0D Here is the link to a quick start guide [4] to setup and run a basic perf d= emo=0D on Linux to use CTR Ext.=0D =0D Qemu patches can be found here:=0D https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v3=0D =0D Opensbi patch can be found here:=0D https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2=0D =0D Linux kernel patches can be found here:=0D https://github.com/rajnesh-kanwal/linux/tree/b4/ctr_upstream_v2=0D =0D [0]: https://github.com/riscv/riscv-control-transfer-records/releases/tag/v= 1.0_rc6=0D [1]: https://github.com/riscvarchive/riscv-indirect-csr-access/releases/tag= /v1.0.0=0D [2]: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.= 0.0=0D [3]: https://lore.kernel.org/all/20240217000134.3634191-1-atishp@rivosinc.c= om/=0D [4]: https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on= -QEMU-RISC%E2%80%90V-Virt-machine=0D =0D Changelog:=0D v3: Improvements based on Jason Chien and Frank Chang's feedback.=0D - Created single set of MACROs for CTR CSRs in cpu_bit.h=0D - Some fixes in riscv_ctr_add_entry.=0D - Return zero for vs/sireg4-6 for CTR 0x200 to 0x2ff range.=0D - Improved extension dependency check.=0D - Fixed invalid ctrctl csr selection bug in riscv_ctr_freeze.=0D - Added implied rules for Smctr and Ssctr.=0D - Added missing SMSTATEEN0_CTR bit in mstateen0 and hstateen0 write ops.= =0D - Some more cosmetic changes.=0D =0D v2: Lots of improvements based on Jason Chien's feedback including:=0D - Added CTR recording for cm.jalt, cm.jt, cm.popret, cm.popretz.=0D - Fixed and added more CTR extension enable checks.=0D - Fixed CTR CSR predicate functions.=0D - Fixed external trap xTE bit checks.=0D - One fix in freeze function for VS-mode.=0D - Lots of minor code improvements.=0D - Added checks in sctrclr instruction helper.=0D - https://lore.kernel.org/qemu-riscv/20240619152708.135991-1-rkanwal@rivo= sinc.com/=0D =0D v1:=0D - https://lore.kernel.org/qemu-riscv/20240529160950.132754-1-rkanwal@rivo= sinc.com/=0D =0D ---=0D Rajnesh Kanwal (6):=0D target/riscv: Remove obsolete sfence.vm instruction=0D target/riscv: Add Control Transfer Records CSR definitions.=0D target/riscv: Add support for Control Transfer Records extension CSRs= .=0D target/riscv: Add support to record CTR entries.=0D target/riscv: Add CTR sctrclr instruction.=0D target/riscv: Add support to access ctrsource, ctrtarget, ctrdata reg= s.=0D =0D target/riscv/cpu.c | 26 ++-=0D target/riscv/cpu.h | 13 ++=0D target/riscv/cpu_bits.h | 94 ++++++++=0D target/riscv/cpu_cfg.h | 2 +=0D target/riscv/cpu_helper.c | 266 +++++++++++++++++++++= +=0D target/riscv/csr.c | 294 +++++++++++++++++++++= +++-=0D target/riscv/helper.h | 9 +-=0D target/riscv/insn32.decode | 2 +-=0D target/riscv/insn_trans/trans_privileged.c.inc | 22 +-=0D target/riscv/insn_trans/trans_rvi.c.inc | 31 +++=0D target/riscv/insn_trans/trans_rvzce.c.inc | 20 ++=0D target/riscv/op_helper.c | 155 ++++++++++++-=0D target/riscv/tcg/tcg-cpu.c | 11 +=0D target/riscv/translate.c | 10 +=0D 14 files changed, 941 insertions(+), 14 deletions(-)=0D ---=0D base-commit: 27dec0a099f70f309d89b43122409aeb003d5702=0D change-id: 20241029-b4-ctr_upstream_v3-7ab764c68bf1=0D -- =0D Regards,=0D Rajnesh Kanwal=0D =0D