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From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
	qemu-ppc@nongnu.org, "Harsh Prateek Bora" <harshpb@linux.ibm.com>,
	"Cédric Le Goater" <clg@kaod.org>,
	"Cédric Le Goater" <clg@redhat.com>
Subject: [PULL 25/67] ppc/spapr: remove deprecated machine pseries-2.9
Date: Mon,  4 Nov 2024 10:18:14 +1000	[thread overview]
Message-ID: <20241104001900.682660-26-npiggin@gmail.com> (raw)
In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com>

From: Harsh Prateek Bora <harshpb@linux.ibm.com>

Commit 1392617d3576 intended to tag pseries-2.1 - 2.11 machines as
deprecated with reasons mentioned in its commit log.
Removing pseries-2.9 specific code with this patch for now.

While at it, also remove the pre-2.10 migration hacks which now become
obsolete.

Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 hw/intc/xics.c         |  16 -------
 hw/ppc/spapr.c         | 104 -----------------------------------------
 include/hw/ppc/spapr.h |   1 -
 migration/savevm.c     |  19 --------
 target/ppc/cpu.h       |   1 -
 target/ppc/cpu_init.c  |   2 -
 target/ppc/machine.c   |   2 +-
 7 files changed, 1 insertion(+), 144 deletions(-)

diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 6f4d5271ea..e893363dc9 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -335,22 +335,6 @@ static void icp_realize(DeviceState *dev, Error **errp)
             return;
         }
     }
-    /*
-     * The way that pre_2_10_icp is handling is really, really hacky.
-     * We used to have here this call:
-     *
-     * vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
-     *
-     * But we were doing:
-     *     pre_2_10_vmstate_register_dummy_icp()
-     *     this vmstate_register()
-     *     pre_2_10_vmstate_unregister_dummy_icp()
-     *
-     * So for a short amount of time we had to vmstate entries with
-     * the same name.  This fixes it.
-     */
-    vmstate_replace_hack_for_ppc(NULL, icp->cs->cpu_index,
-                                 &vmstate_icp_server, icp);
 }
 
 static void icp_unrealize(DeviceState *dev)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 93decfcbeb..14a1314af6 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -132,61 +132,6 @@ static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr,
     return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
 }
 
-static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
-{
-    /* Dummy entries correspond to unused ICPState objects in older QEMUs,
-     * and newer QEMUs don't even have them. In both cases, we don't want
-     * to send anything on the wire.
-     */
-    return false;
-}
-
-static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
-    /*
-     * Hack ahead.  We can't have two devices with the same name and
-     * instance id.  So I rename this to pass make check.
-     * Real help from people who knows the hardware is needed.
-     */
-    .name = "icp/server",
-    .version_id = 1,
-    .minimum_version_id = 1,
-    .needed = pre_2_10_vmstate_dummy_icp_needed,
-    .fields = (const VMStateField[]) {
-        VMSTATE_UNUSED(4), /* uint32_t xirr */
-        VMSTATE_UNUSED(1), /* uint8_t pending_priority */
-        VMSTATE_UNUSED(1), /* uint8_t mfrr */
-        VMSTATE_END_OF_LIST()
-    },
-};
-
-/*
- * See comment in hw/intc/xics.c:icp_realize()
- *
- * You have to remove vmstate_replace_hack_for_ppc() when you remove
- * the machine types that need the following function.
- */
-static void pre_2_10_vmstate_register_dummy_icp(int i)
-{
-    vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
-                     (void *)(uintptr_t) i);
-}
-
-/*
- * See comment in hw/intc/xics.c:icp_realize()
- *
- * You have to remove vmstate_replace_hack_for_ppc() when you remove
- * the machine types that need the following function.
- */
-static void pre_2_10_vmstate_unregister_dummy_icp(int i)
-{
-    /*
-     * This used to be:
-     *
-     *    vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
-     *                      (void *)(uintptr_t) i);
-     */
-}
-
 int spapr_max_server_number(SpaprMachineState *spapr)
 {
     MachineState *ms = MACHINE(spapr);
@@ -2711,7 +2656,6 @@ static void spapr_init_cpus(SpaprMachineState *spapr)
 {
     MachineState *machine = MACHINE(spapr);
     MachineClass *mc = MACHINE_GET_CLASS(machine);
-    SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
     const char *type = spapr_get_cpu_core_type(machine->cpu_type);
     const CPUArchIdList *possible_cpus;
     unsigned int smp_cpus = machine->smp.cpus;
@@ -2740,15 +2684,6 @@ static void spapr_init_cpus(SpaprMachineState *spapr)
         boot_cores_nr = possible_cpus->len;
     }
 
-    if (smc->pre_2_10_has_unused_icps) {
-        for (i = 0; i < spapr_max_server_number(spapr); i++) {
-            /* Dummy entries get deregistered when real ICPState objects
-             * are registered during CPU core hotplug.
-             */
-            pre_2_10_vmstate_register_dummy_icp(i);
-        }
-    }
-
     for (i = 0; i < possible_cpus->len; i++) {
         int core_id = i * smp_threads;
 
@@ -3914,21 +3849,9 @@ void spapr_core_release(DeviceState *dev)
 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
 {
     MachineState *ms = MACHINE(hotplug_dev);
-    SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
     CPUCore *cc = CPU_CORE(dev);
     CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
 
-    if (smc->pre_2_10_has_unused_icps) {
-        SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
-        int i;
-
-        for (i = 0; i < cc->nr_threads; i++) {
-            CPUState *cs = CPU(sc->threads[i]);
-
-            pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
-        }
-    }
-
     assert(core_slot);
     core_slot->cpu = NULL;
     qdev_unrealize(dev);
@@ -4009,7 +3932,6 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev)
 {
     SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
     MachineClass *mc = MACHINE_GET_CLASS(spapr);
-    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
     SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev));
     CPUCore *cc = CPU_CORE(dev);
     SpaprDrc *drc;
@@ -4059,12 +3981,6 @@ static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev)
         }
     }
 
-    if (smc->pre_2_10_has_unused_icps) {
-        for (i = 0; i < cc->nr_threads; i++) {
-            CPUState *cs = CPU(core->threads[i]);
-            pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
-        }
-    }
 }
 
 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
@@ -5165,26 +5081,6 @@ static void spapr_machine_2_10_class_options(MachineClass *mc)
 
 DEFINE_SPAPR_MACHINE(2, 10);
 
-/*
- * pseries-2.9
- */
-
-static void spapr_machine_2_9_class_options(MachineClass *mc)
-{
-    SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
-    static GlobalProperty compat[] = {
-        { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" },
-    };
-
-    spapr_machine_2_10_class_options(mc);
-    compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
-    compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat));
-    smc->pre_2_10_has_unused_icps = true;
-    smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
-}
-
-DEFINE_SPAPR_MACHINE(2, 9);
-
 static void spapr_machine_register_types(void)
 {
     type_register_static(&spapr_machine_info);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 6e9e62386c..af4aa1cb0f 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -143,7 +143,6 @@ struct SpaprMachineClass {
     /*< public >*/
     bool dr_phb_enabled;       /* enable dynamic-reconfig/hotplug of PHBs */
     bool update_dt_enabled;    /* enable KVMPPC_H_UPDATE_DT */
-    bool pre_2_10_has_unused_icps;
     bool legacy_irq_allocation;
     uint32_t nr_xirqs;
     bool broken_host_serial_model; /* present real host info to the guest */
diff --git a/migration/savevm.c b/migration/savevm.c
index 7e1e27182a..839a34402b 100644
--- a/migration/savevm.c
+++ b/migration/savevm.c
@@ -860,25 +860,6 @@ static void vmstate_check(const VMStateDescription *vmsd)
     }
 }
 
-/*
- * See comment in hw/intc/xics.c:icp_realize()
- *
- * This function can be removed when
- * pre_2_10_vmstate_register_dummy_icp() is removed.
- */
-int vmstate_replace_hack_for_ppc(VMStateIf *obj, int instance_id,
-                                 const VMStateDescription *vmsd,
-                                 void *opaque)
-{
-    SaveStateEntry *se = find_se(vmsd->name, instance_id);
-
-    if (se) {
-        savevm_state_handler_remove(se);
-        g_free(se->compat);
-        g_free(se);
-    }
-    return vmstate_register(obj, instance_id, vmsd, opaque);
-}
 
 int vmstate_register_with_alias_id(VMStateIf *obj, uint32_t instance_id,
                                    const VMStateDescription *vmsd,
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 30dba050f6..faa610197d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1457,7 +1457,6 @@ struct ArchCPU {
     opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
 
     /* Fields related to migration compatibility hacks */
-    bool pre_2_10_migration;
     bool pre_3_0_migration;
     int32_t mig_slb_nr;
 };
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 7768392986..39c19e6674 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7452,8 +7452,6 @@ static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
 }
 
 static Property ppc_cpu_properties[] = {
-    DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
-                     false),
     DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
                      false),
     DEFINE_PROP_END_OF_LIST(),
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 21bed7c7c8..47495b68b1 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -630,7 +630,7 @@ static bool compat_needed(void *opaque)
     PowerPCCPU *cpu = opaque;
 
     assert(!(cpu->compat_pvr && !cpu->vhyp));
-    return !cpu->pre_2_10_migration && cpu->compat_pvr != 0;
+    return cpu->compat_pvr != 0;
 }
 
 static const VMStateDescription vmstate_compat = {
-- 
2.45.2



  parent reply	other threads:[~2024-11-04  0:21 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-04  0:17 [PULL 00/67] ppc-for-9.2-1 queue Nicholas Piggin
2024-11-04  0:17 ` [PULL 01/67] target/ppc: Set ctx->opcode for decode_insn32() Nicholas Piggin
2024-11-04  0:17 ` [PULL 02/67] target/ppc: Make divd[u] handler method decodetree compatible Nicholas Piggin
2024-11-05 15:33   ` Michael Tokarev
2024-11-05 18:01     ` Ilya Leoshkevich
2024-11-05 18:45       ` Michael Tokarev
2024-11-04  0:17 ` [PULL 03/67] ppc/pnv: Fix LPC serirq routing calculation Nicholas Piggin
2024-11-04  0:17 ` [PULL 04/67] ppc/pnv: Fix LPC POWER8 register sanity check Nicholas Piggin
2024-11-04  0:17 ` [PULL 05/67] target/ppc: Fix mtDPDES targeting SMT siblings Nicholas Piggin
2024-11-04  0:17 ` [PULL 06/67] target/ppc: PMIs are level triggered Nicholas Piggin
2024-11-04  0:17 ` [PULL 07/67] target/ppc: Fix doorbell delivery to threads in powersave Nicholas Piggin
2024-11-04  0:17 ` [PULL 08/67] target/ppc: Fix HFSCR facility checks Nicholas Piggin
2024-11-05 15:50   ` Michael Tokarev
2024-11-08  2:34     ` Nicholas Piggin
2024-11-04  0:17 ` [PULL 09/67] target/ppc: Fix VRMA to not check virtual page class key protection Nicholas Piggin
2024-11-04  0:17 ` [PULL 10/67] ppc/pnv: ADU fix possible buffer overrun with invalid size Nicholas Piggin
2024-11-04  0:18 ` [PULL 11/67] MAINTAINERS: Cover PowerPC SPI model in PowerNV section Nicholas Piggin
2024-11-04  0:18 ` [PULL 12/67] hw/ssi/pnv_spi: Match _xfer_buffer_free() with _xfer_buffer_new() Nicholas Piggin
2024-11-04  0:18 ` [PULL 13/67] hw/ssi/pnv_spi: Return early in transfer() Nicholas Piggin
2024-11-04  0:18 ` [PULL 14/67] hw/ssi/pnv_spi: Fixes Coverity CID 1558831 Nicholas Piggin
2024-11-04  0:18 ` [PULL 15/67] tests/tcg: Replace -mpower8-vector with -mcpu=power8 Nicholas Piggin
2024-11-04  0:18 ` [PULL 16/67] hw/ppc: fix decrementer with BookE timers Nicholas Piggin
2024-11-04  0:18 ` [PULL 17/67] ppc/spapr: remove deprecated machine pseries-2.1 Nicholas Piggin
2024-11-04  0:18 ` [PULL 18/67] ppc/spapr: remove deprecated machine pseries-2.2 Nicholas Piggin
2024-11-04  0:18 ` [PULL 19/67] ppc/spapr: remove deprecated machine pseries-2.3 Nicholas Piggin
2024-11-04  0:18 ` [PULL 20/67] ppc/spapr: remove deprecated machine pseries-2.4 Nicholas Piggin
2024-11-04  0:18 ` [PULL 21/67] ppc/spapr: remove deprecated machine pseries-2.5 Nicholas Piggin
2024-11-04  0:18 ` [PULL 22/67] ppc/spapr: remove deprecated machine pseries-2.6 Nicholas Piggin
2024-11-04  0:18 ` [PULL 23/67] ppc/spapr: remove deprecated machine pseries-2.7 Nicholas Piggin
2024-11-04  0:18 ` [PULL 24/67] ppc/spapr: remove deprecated machine pseries-2.8 Nicholas Piggin
2024-11-04  0:18 ` Nicholas Piggin [this message]
2024-11-04  0:18 ` [PULL 26/67] ppc/spapr: remove deprecated machine pseries-2.10 Nicholas Piggin
2024-11-04  0:18 ` [PULL 27/67] ppc/spapr: remove deprecated machine pseries-2.11 Nicholas Piggin
2024-11-04  0:18 ` [PULL 28/67] ppc/spapr: remove deprecated machine pseries-2.12-sxxm Nicholas Piggin
2024-11-04  0:18 ` [PULL 29/67] ppc/spapr: remove deprecated machine pseries-2.12 Nicholas Piggin
2024-11-04  0:18 ` [PULL 30/67] target/ppc: Reduce code duplication across Power9/10 init code Nicholas Piggin
2024-11-04  0:18 ` [PULL 31/67] target/ppc: Introduce 'PowerPCCPUClass::spapr_logical_pvr' Nicholas Piggin
2024-11-04  0:18 ` [PULL 32/67] target/ppc: Fix regression due to Power10 and Power11 having same PCR Nicholas Piggin
2024-11-04  0:18 ` [PULL 33/67] target/ppc: Add Power11 DD2.0 processor Nicholas Piggin
2024-11-04  0:18 ` [PULL 34/67] ppc/pseries: Add Power11 cpu type Nicholas Piggin
2024-11-04  0:18 ` [PULL 35/67] target/ppc: use locally stored msr and avoid indirect access Nicholas Piggin
2024-11-04  0:18 ` [PULL 36/67] target/ppc: optimize hreg_compute_pmu_hflags_value Nicholas Piggin
2024-11-04  0:18 ` [PULL 37/67] " Nicholas Piggin
2024-11-04  0:18 ` [PULL 38/67] target/ppc: optimize p9 exception handling routines Nicholas Piggin
2024-11-04  0:18 ` [PULL 39/67] target/ppc: optimize p8 " Nicholas Piggin
2024-11-04  0:18 ` [PULL 40/67] target/ppc: optimize p7 " Nicholas Piggin
2024-11-04  0:18 ` [PULL 41/67] target/ppc: simplify var usage in ppc_next_unmasked_interrupt Nicholas Piggin
2024-11-04  0:18 ` [PULL 42/67] target/ppc: combine multiple ail checks into one Nicholas Piggin
2024-11-04  0:18 ` [PULL 43/67] target/ppc: reduce duplicate code between init_proc_POWER{9, 10} Nicholas Piggin
2024-11-04  0:18 ` [PULL 44/67] spapr: nested: Add support for DPDES SPR in GSB for TCG L0 Nicholas Piggin
2024-11-04  0:18 ` [PULL 45/67] spapr: nested: Add Power11 capability support for Nested PAPR guests in " Nicholas Piggin
2024-11-04  0:18 ` [PULL 46/67] hw/ppc: Implement -dtb support for PowerNV Nicholas Piggin
2024-11-04  0:18 ` [PULL 47/67] ppc/xive: Fix ESB length overflow on 32-bit hosts Nicholas Piggin
2024-11-04  0:18 ` [PULL 48/67] pnv/xive: TIMA patch sets pre-req alignment and formatting changes Nicholas Piggin
2024-11-04  0:18 ` [PULL 49/67] pnv/xive2: Define OGEN field in the TIMA Nicholas Piggin
2024-11-04  0:18 ` [PULL 50/67] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line" Nicholas Piggin
2024-11-04  0:18 ` [PULL 51/67] pnv/xive2: Support for "OS LGS Push" TIMA operation Nicholas Piggin
2024-11-04  0:18 ` [PULL 52/67] ppc/xive2: Dump more NVP state with 'info pic' Nicholas Piggin
2024-11-04  0:18 ` [PULL 53/67] ppc/xive2: Dump the VP-group and crowd tables " Nicholas Piggin
2024-11-04  0:18 ` [PULL 54/67] ppc/xive2: Allow 1-byte write of Target field in TIMA Nicholas Piggin
2024-11-04  0:18 ` [PULL 55/67] ppc/xive2: Support "Pull Thread Context to Register" operation Nicholas Piggin
2024-11-04  0:18 ` [PULL 56/67] ppc/xive2: Change context/ring specific functions to be generic Nicholas Piggin
2024-11-04  0:18 ` [PULL 57/67] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line" Nicholas Piggin
2024-11-04  0:18 ` [PULL 58/67] pnv/xive: Add special handling for pool targets Nicholas Piggin
2024-11-04  0:18 ` [PULL 59/67] pnv/xive: Update PIPR when updating CPPR Nicholas Piggin
2024-11-04  0:18 ` [PULL 60/67] pnv/xive2: TIMA support for 8-byte OS context push for PHYP Nicholas Piggin
2024-11-04  0:18 ` [PULL 61/67] pnv/xive2: TIMA CI ops using alternative offsets or byte lengths Nicholas Piggin
2024-11-04  0:18 ` [PULL 62/67] tests/qtest: Add XIVE tests for the powernv10 machine Nicholas Piggin
2024-11-04  0:18 ` [PULL 63/67] hw/ppc: Consolidate e500 initial mapping creation functions Nicholas Piggin
2024-11-04  0:18 ` [PULL 64/67] hw/ppc: Consolidate ppc440 " Nicholas Piggin
2024-11-04  0:18 ` [PULL 65/67] MAINTAINERS: Remove myself from the PowerNV machines Nicholas Piggin
2024-11-04  0:18 ` [PULL 66/67] MAINTAINERS: Remove myself from XIVE Nicholas Piggin
2024-11-04  0:18 ` [PULL 67/67] MAINTAINERS: Remove myself as reviewer Nicholas Piggin
2024-11-05 14:22 ` [PULL 00/67] ppc-for-9.2-1 queue Peter Maydell

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