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From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-devel@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
	qemu-ppc@nongnu.org, BALATON Zoltan <balaton@eik.bme.hu>,
	"Edgar E . Iglesias" <edgar.iglesias@amd.com>
Subject: [PULL 63/67] hw/ppc: Consolidate e500 initial mapping creation functions
Date: Mon,  4 Nov 2024 10:18:52 +1000	[thread overview]
Message-ID: <20241104001900.682660-64-npiggin@gmail.com> (raw)
In-Reply-To: <20241104001900.682660-1-npiggin@gmail.com>

From: BALATON Zoltan <balaton@eik.bme.hu>

Add booke206_set_tlb() utility function and use it to replace very
similar create_initial_mapping functions in e500 machines.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Tested-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 hw/ppc/e500.c         | 41 +++++++++++++++++++----------------------
 hw/ppc/e500.h         |  2 --
 hw/ppc/ppce500_spin.c | 30 +++++++++---------------------
 include/hw/ppc/ppc.h  |  5 +++++
 4 files changed, 33 insertions(+), 45 deletions(-)

diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index b760c6d6a2..6433348072 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -721,11 +721,21 @@ static int ppce500_prep_device_tree(PPCE500MachineState *machine,
                                     kernel_base, kernel_size, true);
 }
 
-hwaddr booke206_page_size_to_tlb(uint64_t size)
+static hwaddr booke206_page_size_to_tlb(uint64_t size)
 {
     return 63 - clz64(size / KiB);
 }
 
+void booke206_set_tlb(ppcmas_tlb_t *tlb, target_ulong va, hwaddr pa,
+                      hwaddr len)
+{
+    tlb->mas1 = booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT;
+    tlb->mas1 |= MAS1_VALID;
+    tlb->mas2 = va & TARGET_PAGE_MASK;
+    tlb->mas7_3 = pa & TARGET_PAGE_MASK;
+    tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
+}
+
 static int booke206_initial_map_tsize(CPUPPCState *env)
 {
     struct boot_info *bi = env->load_info;
@@ -751,25 +761,6 @@ static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
     return (1ULL << 10 << tsize);
 }
 
-/* Create -kernel TLB entries for BookE. */
-static void mmubooke_create_initial_mapping(CPUPPCState *env)
-{
-    ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
-    hwaddr size;
-    int ps;
-
-    ps = booke206_initial_map_tsize(env);
-    size = (ps << MAS1_TSIZE_SHIFT);
-    tlb->mas1 = MAS1_VALID | size;
-    tlb->mas2 = 0;
-    tlb->mas7_3 = 0;
-    tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
-
-#ifdef CONFIG_KVM
-    env->tlb_dirty = true;
-#endif
-}
-
 static void ppce500_cpu_reset_sec(void *opaque)
 {
     PowerPCCPU *cpu = opaque;
@@ -786,6 +777,8 @@ static void ppce500_cpu_reset(void *opaque)
     CPUState *cs = CPU(cpu);
     CPUPPCState *env = &cpu->env;
     struct boot_info *bi = env->load_info;
+    uint64_t map_size = mmubooke_initial_mapsize(env);
+    ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
 
     cpu_reset(cs);
 
@@ -796,11 +789,15 @@ static void ppce500_cpu_reset(void *opaque)
     env->gpr[4] = 0;
     env->gpr[5] = 0;
     env->gpr[6] = EPAPR_MAGIC;
-    env->gpr[7] = mmubooke_initial_mapsize(env);
+    env->gpr[7] = map_size;
     env->gpr[8] = 0;
     env->gpr[9] = 0;
     env->nip = bi->entry;
-    mmubooke_create_initial_mapping(env);
+    /* create initial mapping */
+    booke206_set_tlb(tlb, 0, 0, map_size);
+#ifdef CONFIG_KVM
+    env->tlb_dirty = true;
+#endif
 }
 
 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index 8c09ef92e4..01db102625 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -41,8 +41,6 @@ struct PPCE500MachineClass {
 
 void ppce500_init(MachineState *machine);
 
-hwaddr booke206_page_size_to_tlb(uint64_t size);
-
 #define TYPE_PPCE500_MACHINE      "ppce500-base-machine"
 OBJECT_DECLARE_TYPE(PPCE500MachineState, PPCE500MachineClass, PPCE500_MACHINE)
 
diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c
index e08739a443..93b16320d4 100644
--- a/hw/ppc/ppce500_spin.c
+++ b/hw/ppc/ppce500_spin.c
@@ -33,6 +33,7 @@
 #include "hw/hw.h"
 #include "hw/sysbus.h"
 #include "sysemu/hw_accel.h"
+#include "hw/ppc/ppc.h"
 #include "e500.h"
 #include "qom/object.h"
 
@@ -70,30 +71,12 @@ static void spin_reset(DeviceState *dev)
     }
 }
 
-static void mmubooke_create_initial_mapping(CPUPPCState *env,
-                                     target_ulong va,
-                                     hwaddr pa,
-                                     hwaddr len)
-{
-    ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1);
-    hwaddr size;
-
-    size = (booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT);
-    tlb->mas1 = MAS1_VALID | size;
-    tlb->mas2 = (va & TARGET_PAGE_MASK) | MAS2_M;
-    tlb->mas7_3 = pa & TARGET_PAGE_MASK;
-    tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
-#ifdef CONFIG_KVM
-    env->tlb_dirty = true;
-#endif
-}
-
 static void spin_kick(CPUState *cs, run_on_cpu_data data)
 {
     CPUPPCState *env = cpu_env(cs);
     SpinInfo *curspin = data.host_ptr;
-    hwaddr map_size = 64 * MiB;
-    hwaddr map_start;
+    hwaddr map_start, map_size = 64 * MiB;
+    ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1);
 
     cpu_synchronize_state(cs);
     stl_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]);
@@ -107,7 +90,12 @@ static void spin_kick(CPUState *cs, run_on_cpu_data data)
     env->gpr[9] = 0;
 
     map_start = ldq_p(&curspin->addr) & ~(map_size - 1);
-    mmubooke_create_initial_mapping(env, 0, map_start, map_size);
+    /* create initial mapping */
+    booke206_set_tlb(tlb, 0, map_start, map_size);
+    tlb->mas2 |= MAS2_M;
+#ifdef CONFIG_KVM
+    env->tlb_dirty = true;
+#endif
 
     cs->halted = 0;
     cs->exception_index = -1;
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index d5d119ea7f..070524b02e 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -116,6 +116,11 @@ enum {
 
 #define PPC_SERIAL_MM_BAUDBASE 399193
 
+#ifndef CONFIG_USER_ONLY
+void booke206_set_tlb(ppcmas_tlb_t *tlb, target_ulong va, hwaddr pa,
+                      hwaddr len);
+#endif
+
 /* ppc_booke.c */
 void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags);
 #endif
-- 
2.45.2



  parent reply	other threads:[~2024-11-04  0:30 UTC|newest]

Thread overview: 74+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-04  0:17 [PULL 00/67] ppc-for-9.2-1 queue Nicholas Piggin
2024-11-04  0:17 ` [PULL 01/67] target/ppc: Set ctx->opcode for decode_insn32() Nicholas Piggin
2024-11-04  0:17 ` [PULL 02/67] target/ppc: Make divd[u] handler method decodetree compatible Nicholas Piggin
2024-11-05 15:33   ` Michael Tokarev
2024-11-05 18:01     ` Ilya Leoshkevich
2024-11-05 18:45       ` Michael Tokarev
2024-11-04  0:17 ` [PULL 03/67] ppc/pnv: Fix LPC serirq routing calculation Nicholas Piggin
2024-11-04  0:17 ` [PULL 04/67] ppc/pnv: Fix LPC POWER8 register sanity check Nicholas Piggin
2024-11-04  0:17 ` [PULL 05/67] target/ppc: Fix mtDPDES targeting SMT siblings Nicholas Piggin
2024-11-04  0:17 ` [PULL 06/67] target/ppc: PMIs are level triggered Nicholas Piggin
2024-11-04  0:17 ` [PULL 07/67] target/ppc: Fix doorbell delivery to threads in powersave Nicholas Piggin
2024-11-04  0:17 ` [PULL 08/67] target/ppc: Fix HFSCR facility checks Nicholas Piggin
2024-11-05 15:50   ` Michael Tokarev
2024-11-08  2:34     ` Nicholas Piggin
2024-11-04  0:17 ` [PULL 09/67] target/ppc: Fix VRMA to not check virtual page class key protection Nicholas Piggin
2024-11-04  0:17 ` [PULL 10/67] ppc/pnv: ADU fix possible buffer overrun with invalid size Nicholas Piggin
2024-11-04  0:18 ` [PULL 11/67] MAINTAINERS: Cover PowerPC SPI model in PowerNV section Nicholas Piggin
2024-11-04  0:18 ` [PULL 12/67] hw/ssi/pnv_spi: Match _xfer_buffer_free() with _xfer_buffer_new() Nicholas Piggin
2024-11-04  0:18 ` [PULL 13/67] hw/ssi/pnv_spi: Return early in transfer() Nicholas Piggin
2024-11-04  0:18 ` [PULL 14/67] hw/ssi/pnv_spi: Fixes Coverity CID 1558831 Nicholas Piggin
2024-11-04  0:18 ` [PULL 15/67] tests/tcg: Replace -mpower8-vector with -mcpu=power8 Nicholas Piggin
2024-11-04  0:18 ` [PULL 16/67] hw/ppc: fix decrementer with BookE timers Nicholas Piggin
2024-11-04  0:18 ` [PULL 17/67] ppc/spapr: remove deprecated machine pseries-2.1 Nicholas Piggin
2024-11-04  0:18 ` [PULL 18/67] ppc/spapr: remove deprecated machine pseries-2.2 Nicholas Piggin
2024-11-04  0:18 ` [PULL 19/67] ppc/spapr: remove deprecated machine pseries-2.3 Nicholas Piggin
2024-11-04  0:18 ` [PULL 20/67] ppc/spapr: remove deprecated machine pseries-2.4 Nicholas Piggin
2024-11-04  0:18 ` [PULL 21/67] ppc/spapr: remove deprecated machine pseries-2.5 Nicholas Piggin
2024-11-04  0:18 ` [PULL 22/67] ppc/spapr: remove deprecated machine pseries-2.6 Nicholas Piggin
2024-11-04  0:18 ` [PULL 23/67] ppc/spapr: remove deprecated machine pseries-2.7 Nicholas Piggin
2024-11-04  0:18 ` [PULL 24/67] ppc/spapr: remove deprecated machine pseries-2.8 Nicholas Piggin
2024-11-04  0:18 ` [PULL 25/67] ppc/spapr: remove deprecated machine pseries-2.9 Nicholas Piggin
2024-11-04  0:18 ` [PULL 26/67] ppc/spapr: remove deprecated machine pseries-2.10 Nicholas Piggin
2024-11-04  0:18 ` [PULL 27/67] ppc/spapr: remove deprecated machine pseries-2.11 Nicholas Piggin
2024-11-04  0:18 ` [PULL 28/67] ppc/spapr: remove deprecated machine pseries-2.12-sxxm Nicholas Piggin
2024-11-04  0:18 ` [PULL 29/67] ppc/spapr: remove deprecated machine pseries-2.12 Nicholas Piggin
2024-11-04  0:18 ` [PULL 30/67] target/ppc: Reduce code duplication across Power9/10 init code Nicholas Piggin
2024-11-04  0:18 ` [PULL 31/67] target/ppc: Introduce 'PowerPCCPUClass::spapr_logical_pvr' Nicholas Piggin
2024-11-04  0:18 ` [PULL 32/67] target/ppc: Fix regression due to Power10 and Power11 having same PCR Nicholas Piggin
2024-11-04  0:18 ` [PULL 33/67] target/ppc: Add Power11 DD2.0 processor Nicholas Piggin
2024-11-04  0:18 ` [PULL 34/67] ppc/pseries: Add Power11 cpu type Nicholas Piggin
2024-11-04  0:18 ` [PULL 35/67] target/ppc: use locally stored msr and avoid indirect access Nicholas Piggin
2024-11-04  0:18 ` [PULL 36/67] target/ppc: optimize hreg_compute_pmu_hflags_value Nicholas Piggin
2024-11-04  0:18 ` [PULL 37/67] " Nicholas Piggin
2024-11-04  0:18 ` [PULL 38/67] target/ppc: optimize p9 exception handling routines Nicholas Piggin
2024-11-04  0:18 ` [PULL 39/67] target/ppc: optimize p8 " Nicholas Piggin
2024-11-04  0:18 ` [PULL 40/67] target/ppc: optimize p7 " Nicholas Piggin
2024-11-04  0:18 ` [PULL 41/67] target/ppc: simplify var usage in ppc_next_unmasked_interrupt Nicholas Piggin
2024-11-04  0:18 ` [PULL 42/67] target/ppc: combine multiple ail checks into one Nicholas Piggin
2024-11-04  0:18 ` [PULL 43/67] target/ppc: reduce duplicate code between init_proc_POWER{9, 10} Nicholas Piggin
2024-11-04  0:18 ` [PULL 44/67] spapr: nested: Add support for DPDES SPR in GSB for TCG L0 Nicholas Piggin
2024-11-04  0:18 ` [PULL 45/67] spapr: nested: Add Power11 capability support for Nested PAPR guests in " Nicholas Piggin
2024-11-04  0:18 ` [PULL 46/67] hw/ppc: Implement -dtb support for PowerNV Nicholas Piggin
2024-11-04  0:18 ` [PULL 47/67] ppc/xive: Fix ESB length overflow on 32-bit hosts Nicholas Piggin
2024-11-04  0:18 ` [PULL 48/67] pnv/xive: TIMA patch sets pre-req alignment and formatting changes Nicholas Piggin
2024-11-04  0:18 ` [PULL 49/67] pnv/xive2: Define OGEN field in the TIMA Nicholas Piggin
2024-11-04  0:18 ` [PULL 50/67] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line" Nicholas Piggin
2024-11-04  0:18 ` [PULL 51/67] pnv/xive2: Support for "OS LGS Push" TIMA operation Nicholas Piggin
2024-11-04  0:18 ` [PULL 52/67] ppc/xive2: Dump more NVP state with 'info pic' Nicholas Piggin
2024-11-04  0:18 ` [PULL 53/67] ppc/xive2: Dump the VP-group and crowd tables " Nicholas Piggin
2024-11-04  0:18 ` [PULL 54/67] ppc/xive2: Allow 1-byte write of Target field in TIMA Nicholas Piggin
2024-11-04  0:18 ` [PULL 55/67] ppc/xive2: Support "Pull Thread Context to Register" operation Nicholas Piggin
2024-11-04  0:18 ` [PULL 56/67] ppc/xive2: Change context/ring specific functions to be generic Nicholas Piggin
2024-11-04  0:18 ` [PULL 57/67] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line" Nicholas Piggin
2024-11-04  0:18 ` [PULL 58/67] pnv/xive: Add special handling for pool targets Nicholas Piggin
2024-11-04  0:18 ` [PULL 59/67] pnv/xive: Update PIPR when updating CPPR Nicholas Piggin
2024-11-04  0:18 ` [PULL 60/67] pnv/xive2: TIMA support for 8-byte OS context push for PHYP Nicholas Piggin
2024-11-04  0:18 ` [PULL 61/67] pnv/xive2: TIMA CI ops using alternative offsets or byte lengths Nicholas Piggin
2024-11-04  0:18 ` [PULL 62/67] tests/qtest: Add XIVE tests for the powernv10 machine Nicholas Piggin
2024-11-04  0:18 ` Nicholas Piggin [this message]
2024-11-04  0:18 ` [PULL 64/67] hw/ppc: Consolidate ppc440 initial mapping creation functions Nicholas Piggin
2024-11-04  0:18 ` [PULL 65/67] MAINTAINERS: Remove myself from the PowerNV machines Nicholas Piggin
2024-11-04  0:18 ` [PULL 66/67] MAINTAINERS: Remove myself from XIVE Nicholas Piggin
2024-11-04  0:18 ` [PULL 67/67] MAINTAINERS: Remove myself as reviewer Nicholas Piggin
2024-11-05 14:22 ` [PULL 00/67] ppc-for-9.2-1 queue Peter Maydell

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