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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Anton Johansson <anjo@rev.ng>, qemu-devel@nongnu.org
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
	"Thomas Huth" <thuth@redhat.com>,
	"Jason Wang" <jasowang@redhat.com>,
	devel@lists.libvirt.org, qemu-ppc@nongnu.org,
	"Alistair Francis" <alistair@alistair23.me>,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	qemu-arm@nongnu.org, "Peter Maydell" <peter.maydell@linaro.org>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Edgar E . Iglesias" <edgar.iglesias@amd.com>
Subject: [RFC PATCH v2 05/16] hw/timer/xilinx_timer: Allow down to 8-bit memory access
Date: Thu,  7 Nov 2024 01:22:11 +0000	[thread overview]
Message-ID: <20241107012223.94337-6-philmd@linaro.org> (raw)
In-Reply-To: <20241107012223.94337-1-philmd@linaro.org>

Allow down to 8-bit access, per the datasheet (reference added
in previous commit):

 "Timer Counter registers are accessed as one of the following types:
  • Byte (8 bits)
  • Half word (2 bytes)
  • Word (4 bytes)"

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
---
RFC: This breaks the UART qtest, instead of having TX register
receiving 'T' = 0x54, it receives 0x54000000, converted to '\0'
char. It works if we use SWI instead of SBI (storing 32-bit).
---
 hw/timer/xilinx_timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
index 383fc8b3c8..c117bff225 100644
--- a/hw/timer/xilinx_timer.c
+++ b/hw/timer/xilinx_timer.c
@@ -198,7 +198,7 @@ static const MemoryRegionOps timer_ops = {
         .max_access_size = 4,
     },
     .valid = {
-        .min_access_size = 4,
+        .min_access_size = 1,
         .max_access_size = 4
     }
 };
-- 
2.45.2



  parent reply	other threads:[~2024-11-07  1:23 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-07  1:22 [PATCH v2 00/16] hw/microblaze: Allow running cross-endian vCPUs Philippe Mathieu-Daudé
2024-11-07  1:22 ` [PATCH v2 01/16] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit Philippe Mathieu-Daudé
2024-11-07  1:22 ` [PATCH v2 02/16] hw/microblaze: Propagate CPU endianness to microblaze_load_kernel() Philippe Mathieu-Daudé
2024-11-07 10:06   ` Richard Henderson
2024-11-07  1:22 ` [PATCH v2 03/16] hw/intc/xilinx_intc: Make device endianness configurable Philippe Mathieu-Daudé
2024-11-07 10:12   ` Richard Henderson
2024-11-07  1:22 ` [RFC PATCH v2 04/16] hw/net/xilinx_ethlite: Simplify by having configurable endianness Philippe Mathieu-Daudé
2024-11-07 10:16   ` Richard Henderson
2024-11-07  1:22 ` Philippe Mathieu-Daudé [this message]
2024-11-07  1:22 ` [PATCH v2 06/16] hw/timer/xilinx_timer: Make device endianness configurable Philippe Mathieu-Daudé
2024-11-07 10:18   ` Richard Henderson
2024-11-07  1:22 ` [PATCH v2 07/16] hw/char/xilinx_uartlite: " Philippe Mathieu-Daudé
2024-11-07 10:27   ` Richard Henderson
2024-11-08 15:06     ` Philippe Mathieu-Daudé
2024-11-07  1:22 ` [PATCH v2 08/16] hw/ssi/xilinx_spi: " Philippe Mathieu-Daudé
2024-11-07 11:01   ` Richard Henderson
2024-11-08 15:07     ` Philippe Mathieu-Daudé
2024-11-07  1:22 ` [PATCH v2 09/16] hw/ssi/xilinx_spips: " Philippe Mathieu-Daudé
2024-11-07 11:02   ` Richard Henderson
2024-11-07  1:22 ` [PATCH v2 10/16] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2024-11-07  1:22 ` [PATCH v2 11/16] target/microblaze: Set MO_TE once in do_load() / do_store() Philippe Mathieu-Daudé
2024-11-07  1:22 ` [PATCH v2 12/16] target/microblaze: Introduce mo_endian() helper Philippe Mathieu-Daudé
2024-11-07  1:22 ` [PATCH v2 13/16] target/microblaze: Consider endianness while translating code Philippe Mathieu-Daudé
2024-11-07  1:22 ` [PATCH v2 14/16] hw/microblaze: Support various endianness for s3adsp1800 machines Philippe Mathieu-Daudé
2024-11-07  1:22 ` [PATCH v2 15/16] tests/functional: Explicit endianness of microblaze assets Philippe Mathieu-Daudé
2024-11-07  1:22 ` [PATCH v2 16/16] tests/functional: Add microblaze cross-endianness tests Philippe Mathieu-Daudé

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