From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org, Anton Johansson <anjo@rev.ng>
Cc: "Jason Wang" <jasowang@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
devel@lists.libvirt.org,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Thomas Huth" <thuth@redhat.com>,
qemu-arm@nongnu.org, qemu-ppc@nongnu.org,
"Peter Maydell" <peter.maydell@linaro.org>,
"Alistair Francis" <alistair@alistair23.me>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Alistair Francis" <alistair.francis@wdc.com>
Subject: [PATCH v3 11/17] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx
Date: Fri, 8 Nov 2024 15:43:11 +0000 [thread overview]
Message-ID: <20241108154317.12129-12-philmd@linaro.org> (raw)
In-Reply-To: <20241108154317.12129-1-philmd@linaro.org>
Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/microblaze); \
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/microblaze/translate.c | 36 +++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 4beaf69e76..4c25b1e438 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -779,13 +779,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg)
static bool trans_lhu(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
}
static bool trans_lhur(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
}
static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
@@ -797,26 +797,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_lhui(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_load(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
}
static bool trans_lw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
}
static bool trans_lwr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
}
static bool trans_lwea(DisasContext *dc, arg_typea *arg)
@@ -828,14 +828,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_lwi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_load(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
}
static bool trans_lwx(DisasContext *dc, arg_typea *arg)
@@ -845,7 +845,7 @@ static bool trans_lwx(DisasContext *dc, arg_typea *arg)
/* lwx does not throw unaligned access errors, so force alignment */
tcg_gen_andi_tl(addr, addr, ~3);
- tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TEUL);
+ tcg_gen_qemu_ld_i32(cpu_res_val, addr, dc->mem_index, MO_TE | MO_UL);
tcg_gen_mov_tl(cpu_res_addr, addr);
if (arg->rd) {
@@ -929,13 +929,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg)
static bool trans_sh(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
}
static bool trans_shr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, true);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
}
static bool trans_shea(DisasContext *dc, arg_typea *arg)
@@ -947,26 +947,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUW, MMU_NOMMU_IDX, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_shi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_store(dc, arg->rd, addr, MO_TEUW, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
}
static bool trans_sw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
}
static bool trans_swr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, true);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
}
static bool trans_swea(DisasContext *dc, arg_typea *arg)
@@ -978,14 +978,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TEUL, MMU_NOMMU_IDX, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_swi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_store(dc, arg->rd, addr, MO_TEUL, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
}
static bool trans_swx(DisasContext *dc, arg_typea *arg)
@@ -1014,7 +1014,7 @@ static bool trans_swx(DisasContext *dc, arg_typea *arg)
tcg_gen_atomic_cmpxchg_i32(tval, cpu_res_addr, cpu_res_val,
reg_for_write(dc, arg->rd),
- dc->mem_index, MO_TEUL);
+ dc->mem_index, MO_TE | MO_UL);
tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_fail);
--
2.45.2
next prev parent reply other threads:[~2024-11-08 15:48 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-08 15:43 [PATCH v3 00/17] hw/microblaze: Allow running cross-endian vCPUs Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 01/17] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 02/17] hw/microblaze: Propagate CPU endianness to microblaze_load_kernel() Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 03/17] hw/intc/xilinx_intc: Make device endianness configurable Philippe Mathieu-Daudé
2024-11-08 15:43 ` [RFC PATCH v3 04/17] hw/net/xilinx_ethlite: Simplify by having configurable endianness Philippe Mathieu-Daudé
2024-11-08 16:05 ` Paolo Bonzini
2024-11-11 12:02 ` Philippe Mathieu-Daudé
2024-11-08 15:43 ` [RFC PATCH v3 05/17] hw/timer/xilinx_timer: Allow down to 8-bit memory access Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 06/17] hw/timer/xilinx_timer: Make device endianness configurable Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 07/17] hw/char/xilinx_uartlite: " Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 08/17] hw/ssi/xilinx_spi: " Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 09/17] hw/ssi/xilinx_spips: " Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 10/17] hw/arm/xlnx-zynqmp: Use &error_abort for programming errors Philippe Mathieu-Daudé
2025-02-04 21:34 ` Philippe Mathieu-Daudé
2025-02-05 0:21 ` Anton Johansson via
2024-11-08 15:43 ` Philippe Mathieu-Daudé [this message]
2024-11-08 15:43 ` [PATCH v3 12/17] target/microblaze: Set MO_TE once in do_load() / do_store() Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 13/17] target/microblaze: Introduce mo_endian() helper Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 14/17] target/microblaze: Consider endianness while translating code Philippe Mathieu-Daudé
2024-11-08 15:43 ` [PATCH v3 15/17] hw/microblaze: Support various endianness for s3adsp1800 machines Philippe Mathieu-Daudé
2024-11-11 7:56 ` Thomas Huth
2024-11-11 11:59 ` Philippe Mathieu-Daudé
2024-11-11 12:16 ` Thomas Huth
2024-11-08 15:43 ` [PATCH v3 16/17] tests/functional: Explicit endianness of microblaze assets Philippe Mathieu-Daudé
2024-11-11 7:51 ` Thomas Huth
2024-11-08 15:43 ` [PATCH v3 17/17] tests/functional: Add microblaze cross-endianness tests Philippe Mathieu-Daudé
2024-11-11 7:57 ` Thomas Huth
2024-11-11 11:54 ` Philippe Mathieu-Daudé
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