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[109.42.51.55]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9ee0deeed0sm326761966b.139.2024.11.08.22.42.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2024 22:42:27 -0800 (PST) Date: Sat, 9 Nov 2024 07:42:25 +0100 From: Thomas Huth To: Philippe =?UTF-8?B?TWF0aGlldS1EYXVkw6k=?= Cc: qemu-devel@nongnu.org, Artyom Tarasenko , Stefano Stabellini , Richard Henderson , xen-devel@lists.xenproject.org, Paolo Bonzini , Marcel Apfelbaum , "Edgar E. Iglesias" , Bastian Koppelmann , Anthony PERARD , Eduardo Habkost , Jia Liu , Stafford Horne , Paul Durrant , Mark Cave-Ayland , "Michael S. Tsirkin" Subject: Re: [PATCH 4/5] hw/openrisc: Mark devices as big-endian Message-ID: <20241109074225.76e0e4ad@tpx1> In-Reply-To: <20241106184612.71897-5-philmd@linaro.org> References: <20241106184612.71897-1-philmd@linaro.org> <20241106184612.71897-5-philmd@linaro.org> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.43; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=209.85.218.44; envelope-from=th.huth@gmail.com; helo=mail-ej1-f44.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am Wed, 6 Nov 2024 18:46:11 +0000 schrieb Philippe Mathieu-Daud=C3=A9 : > These devices are only used by the OpenRISC target, which is > only built as big-endian. Therefore the DEVICE_NATIVE_ENDIAN > definition expand to DEVICE_BIG_ENDIAN (besides, the > DEVICE_LITTLE_ENDIAN case isn't tested). Simplify directly > using DEVICE_BIG_ENDIAN. >=20 > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > hw/openrisc/openrisc_sim.c | 2 +- > hw/openrisc/virt.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c > index 9fb63515ef..794c175bdb 100644 > --- a/hw/openrisc/openrisc_sim.c > +++ b/hw/openrisc/openrisc_sim.c > @@ -266,7 +266,7 @@ static void openrisc_sim_serial_init(Or1ksimState *st= ate, hwaddr base, > } > serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, > serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1), > - DEVICE_NATIVE_ENDIAN); > + DEVICE_BIG_ENDIAN); > =20 > /* Add device tree node for serial. */ > nodename =3D g_strdup_printf("/serial@%" HWADDR_PRIx, base); > diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c > index 47d2c9bd3c..ede57fe391 100644 > --- a/hw/openrisc/virt.c > +++ b/hw/openrisc/virt.c > @@ -236,7 +236,7 @@ static void openrisc_virt_serial_init(OR1KVirtState *= state, hwaddr base, > qemu_irq serial_irq =3D get_per_cpu_irq(cpus, num_cpus, irq_pin); > =20 > serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, > - serial_hd(0), DEVICE_NATIVE_ENDIAN); > + serial_hd(0), DEVICE_BIG_ENDIAN); > =20 > /* Add device tree node for serial. */ > nodename =3D g_strdup_printf("/serial@%" HWADDR_PRIx, base); According to https://openrisc.io/or1k.html the openrisc CPU could be implemented as little endian, too ... so would it make sense to use a runtime detected value here instead? Thomas