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[109.42.51.55]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9ee0a18a03sm387313666b.9.2024.11.09.10.40.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Nov 2024 10:40:07 -0800 (PST) Date: Sat, 9 Nov 2024 19:40:05 +0100 From: Thomas Huth To: Richard Henderson Cc: Philippe =?UTF-8?B?TWF0aGlldS1EYXVkw6k=?= , qemu-devel@nongnu.org Subject: Re: [PATCH 4/5] hw/openrisc: Mark devices as big-endian Message-ID: <20241109194005.628e8a53@tpx1> In-Reply-To: References: <20241106184612.71897-1-philmd@linaro.org> <20241106184612.71897-5-philmd@linaro.org> <20241109074225.76e0e4ad@tpx1> <84046f49-a39f-4639-a383-fa3c4a97e17a@linaro.org> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.43; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=209.85.218.45; envelope-from=th.huth@gmail.com; helo=mail-ej1-f45.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am Sat, 9 Nov 2024 10:08:16 -0800 schrieb Richard Henderson : > On 11/9/24 07:58, Philippe Mathieu-Daud=C3=A9 wrote: > > Hi Thomas, > >=20 > > On 9/11/24 06:42, Thomas Huth wrote: =20 > >> Am Wed,=C2=A0 6 Nov 2024 18:46:11 +0000 > >> schrieb Philippe Mathieu-Daud=C3=A9 : > >> =20 > >>> These devices are only used by the OpenRISC target, which is > >>> only built as big-endian. Therefore the DEVICE_NATIVE_ENDIAN > >>> definition expand to DEVICE_BIG_ENDIAN (besides, the > >>> DEVICE_LITTLE_ENDIAN case isn't tested). Simplify directly > >>> using DEVICE_BIG_ENDIAN. > >>> > >>> Signed-off-by: Philippe Mathieu-Daud=C3=A9 > >>> --- > >>> =C2=A0 hw/openrisc/openrisc_sim.c | 2 +- > >>> =C2=A0 hw/openrisc/virt.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 | 2 +- > >>> =C2=A0 2 files changed, 2 insertions(+), 2 deletions(-) =20 > >=20 > > =20 > >>> diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c > >>> index 47d2c9bd3c..ede57fe391 100644 > >>> --- a/hw/openrisc/virt.c > >>> +++ b/hw/openrisc/virt.c > >>> @@ -236,7 +236,7 @@ static void openrisc_virt_serial_init(OR1KVirtSta= te *state, hwaddr=20 > >>> base, > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 qemu_irq serial_irq =3D get_per_cpu_ir= q(cpus, num_cpus, irq_pin); > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 serial_mm_init(get_system_memory(), ba= se, 0, serial_irq, 115200, > >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 serial_hd(0), DEVICE_NATIVE_ENDI= AN); > >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 serial_hd(0), DEVICE_BIG_ENDIAN); > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* Add device tree node for serial. */ > >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 nodename =3D g_strdup_printf("/serial@= %" HWADDR_PRIx, base); =20 > >> > >> According to https://openrisc.io/or1k.html the openrisc CPU could be > >> implemented as little endian, too ... so would it make sense to use > >> a runtime detected value here instead? =20 > >=20 > > While this patch is a code change, it aims to not introduce any > > functional change. We are not building (nor testing) these devices > > in a little endian configuration: > >=20 > > $ git grep -l TARGET_BIG_ENDIAN configs/targets/*softmmu* > > configs/targets/hppa-softmmu.mak > > configs/targets/m68k-softmmu.mak > > configs/targets/microblaze-softmmu.mak > > configs/targets/mips-softmmu.mak > > configs/targets/mips64-softmmu.mak > > configs/targets/or1k-softmmu.mak > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 ^^^^ =20 >=20 > The openrisc little-endian control is in a control register: SR[LEE] (whi= ch we do not=20 > implement at present). >=20 > So any openrisc little-endian support would look like qemu-system-ppc64. = I would not=20 > expect devices to switch endianness at all. Ok, thanks, in that case, I think the patch is fine. FWIW: Reviewed-by: Thomas Huth