From: Zhenzhong Duan <zhenzhong.duan@intel.com>
To: qemu-devel@nongnu.org
Cc: alex.williamson@redhat.com, clg@redhat.com,
eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com,
jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,
joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com,
kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com,
Zhenzhong Duan <zhenzhong.duan@intel.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: [PATCH v5 13/20] intel_iommu: Add support for PASID-based device IOTLB invalidation
Date: Mon, 11 Nov 2024 16:34:50 +0800 [thread overview]
Message-ID: <20241111083457.2090664-14-zhenzhong.duan@intel.com> (raw)
In-Reply-To: <20241111083457.2090664-1-zhenzhong.duan@intel.com>
From: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
---
hw/i386/intel_iommu_internal.h | 11 ++++++++
hw/i386/intel_iommu.c | 50 ++++++++++++++++++++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 5e4e563e62..2c977aa7da 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -385,6 +385,7 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descriptor */
#define VTD_INV_DESC_PIOTLB 0x6 /* PASID-IOTLB Invalidate Desc */
#define VTD_INV_DESC_PC 0x7 /* PASID-cache Invalidate Desc */
+#define VTD_INV_DESC_DEV_PIOTLB 0x8 /* PASID-based-DIOTLB inv_desc*/
#define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descriptor */
/* Masks for Invalidation Wait Descriptor*/
@@ -426,6 +427,16 @@ typedef union VTDInvDesc VTDInvDesc;
/* Masks for Interrupt Entry Invalidate Descriptor */
#define VTD_INV_DESC_IEC_RSVD 0xffff000007fff1e0ULL
+/* Masks for PASID based Device IOTLB Invalidate Descriptor */
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_ADDR(val) ((val) & \
+ 0xfffffffffffff000ULL)
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_SIZE(val) ((val >> 11) & 0x1)
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_GLOBAL(val) ((val) & 0x1)
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_SID(val) (((val) >> 16) & 0xffffULL)
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_PASID(val) ((val >> 32) & 0xfffffULL)
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_VAL0 0xfff000000000f000ULL
+#define VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_VAL1 0x7feULL
+
/* Rsvd field masks for spte */
#define VTD_SPTE_SNP 0x800ULL
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 599d017b18..f80d60c16e 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3075,6 +3075,49 @@ static void do_invalidate_device_tlb(VTDAddressSpace *vtd_dev_as,
memory_region_notify_iommu(&vtd_dev_as->iommu, 0, event);
}
+static bool vtd_process_device_piotlb_desc(IntelIOMMUState *s,
+ VTDInvDesc *inv_desc)
+{
+ uint16_t sid;
+ VTDAddressSpace *vtd_dev_as;
+ bool size;
+ bool global;
+ hwaddr addr;
+ uint32_t pasid;
+ uint64_t mask[4] = {VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_VAL0,
+ VTD_INV_DESC_PASID_DEVICE_IOTLB_RSVD_VAL1,
+ VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE};
+
+ if (!vtd_inv_desc_reserved_check(s, inv_desc, mask, true,
+ __func__, "device piotlb inv")) {
+ return false;
+ }
+
+ global = VTD_INV_DESC_PASID_DEVICE_IOTLB_GLOBAL(inv_desc->hi);
+ size = VTD_INV_DESC_PASID_DEVICE_IOTLB_SIZE(inv_desc->hi);
+ addr = VTD_INV_DESC_PASID_DEVICE_IOTLB_ADDR(inv_desc->hi);
+ sid = VTD_INV_DESC_PASID_DEVICE_IOTLB_SID(inv_desc->lo);
+ if (global) {
+ QLIST_FOREACH(vtd_dev_as, &s->vtd_as_with_notifiers, next) {
+ if ((vtd_dev_as->pasid != PCI_NO_PASID) &&
+ (PCI_BUILD_BDF(pci_bus_num(vtd_dev_as->bus),
+ vtd_dev_as->devfn) == sid)) {
+ do_invalidate_device_tlb(vtd_dev_as, size, addr);
+ }
+ }
+ } else {
+ pasid = VTD_INV_DESC_PASID_DEVICE_IOTLB_PASID(inv_desc->lo);
+ vtd_dev_as = vtd_get_as_by_sid_and_pasid(s, sid, pasid);
+ if (!vtd_dev_as) {
+ return true;
+ }
+
+ do_invalidate_device_tlb(vtd_dev_as, size, addr);
+ }
+
+ return true;
+}
+
static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
VTDInvDesc *inv_desc)
{
@@ -3161,6 +3204,13 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
}
break;
+ case VTD_INV_DESC_DEV_PIOTLB:
+ trace_vtd_inv_desc("device-piotlb", inv_desc.hi, inv_desc.lo);
+ if (!vtd_process_device_piotlb_desc(s, &inv_desc)) {
+ return false;
+ }
+ break;
+
case VTD_INV_DESC_DEVICE:
trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo);
if (!vtd_process_device_iotlb_desc(s, &inv_desc)) {
--
2.34.1
next prev parent reply other threads:[~2024-11-11 8:42 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-11 8:34 [PATCH v5 00/20] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 01/20] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 02/20] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 03/20] intel_iommu: Add a placeholder variable for scalable modern mode Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 04/20] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 05/20] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 06/20] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 07/20] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 08/20] intel_iommu: Check stage-1 translation result with interrupt range Zhenzhong Duan
2024-11-13 6:55 ` CLEMENT MATHIEU--DRIF
2024-11-13 8:49 ` Duan, Zhenzhong
2024-11-14 6:04 ` CLEMENT MATHIEU--DRIF
2024-12-04 2:11 ` Jason Wang
2024-11-11 8:34 ` [PATCH v5 09/20] intel_iommu: Set accessed and dirty bits during stage-1 translation Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 10/20] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 11/20] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 12/20] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-11-11 8:34 ` Zhenzhong Duan [this message]
2024-12-04 3:27 ` [PATCH v5 13/20] intel_iommu: Add support for PASID-based device IOTLB invalidation Jason Wang
2024-11-11 8:34 ` [PATCH v5 14/20] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 15/20] tests/acpi: q35: allow DMAR acpi table changes Zhenzhong Duan
2024-11-20 6:09 ` CLEMENT MATHIEU--DRIF
2024-12-04 3:27 ` Jason Wang
2024-11-11 8:34 ` [PATCH v5 16/20] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2 Zhenzhong Duan
2024-12-04 3:28 ` Jason Wang
2024-11-11 8:34 ` [PATCH v5 17/20] tests/acpi: q35: Update host address width in DMAR Zhenzhong Duan
2024-11-13 7:16 ` CLEMENT MATHIEU--DRIF
2024-11-13 8:50 ` Duan, Zhenzhong
2024-11-11 8:34 ` [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode Zhenzhong Duan
2024-11-19 6:54 ` CLEMENT MATHIEU--DRIF
2024-11-19 7:28 ` Duan, Zhenzhong
2024-11-19 8:59 ` CLEMENT MATHIEU--DRIF
2024-11-19 9:25 ` Duan, Zhenzhong
2024-11-20 6:11 ` CLEMENT MATHIEU--DRIF
2024-12-04 3:34 ` Jason Wang
2024-12-04 6:14 ` CLEMENT MATHIEU--DRIF
2024-12-09 3:13 ` Jason Wang
2024-12-09 6:14 ` CLEMENT MATHIEU--DRIF
2024-12-09 6:24 ` Jason Wang
2024-12-09 6:42 ` CLEMENT MATHIEU--DRIF
2024-12-11 2:22 ` Duan, Zhenzhong
2024-12-11 3:03 ` Jason Wang
2024-12-11 6:08 ` CLEMENT MATHIEU--DRIF
2024-11-11 8:34 ` [PATCH v5 19/20] intel_iommu: Introduce a property to control FS1GP cap bit setting Zhenzhong Duan
2024-11-11 8:34 ` [PATCH v5 20/20] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-12-03 9:00 ` [PATCH v5 00/20] intel_iommu: Enable stage-1 translation for emulated device Duan, Zhenzhong
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