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From: Zhenzhong Duan <zhenzhong.duan@intel.com>
To: qemu-devel@nongnu.org
Cc: alex.williamson@redhat.com, clg@redhat.com,
	eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com,
	jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,
	joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com,
	kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com,
	Zhenzhong Duan <zhenzhong.duan@intel.com>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Eduardo Habkost <eduardo@habkost.net>
Subject: [PATCH v5 03/20] intel_iommu: Add a placeholder variable for scalable modern mode
Date: Mon, 11 Nov 2024 16:34:40 +0800	[thread overview]
Message-ID: <20241111083457.2090664-4-zhenzhong.duan@intel.com> (raw)
In-Reply-To: <20241111083457.2090664-1-zhenzhong.duan@intel.com>

Add an new element scalable_mode in IntelIOMMUState to mark scalable
modern mode, this element will be exposed as an intel_iommu property
finally.

For now, it's only a placehholder and used for address width
compatibility check and block host device passthrough until nesting
is supported.

Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
---
 include/hw/i386/intel_iommu.h |  1 +
 hw/i386/intel_iommu.c         | 23 ++++++++++++++++++-----
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index d372cd396b..3d65bbbd56 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -262,6 +262,7 @@ struct IntelIOMMUState {
 
     bool caching_mode;              /* RO - is cap CM enabled? */
     bool scalable_mode;             /* RO - is Scalable Mode supported? */
+    bool scalable_modern;           /* RO - is modern SM supported? */
     bool snoop_control;             /* RO - is SNP filed supported? */
 
     dma_addr_t root;                /* Current root table pointer */
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 10b8425a6c..1d13916a98 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3918,7 +3918,13 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod,
         return false;
     }
 
-    return true;
+    if (!s->scalable_modern) {
+        /* All checks requested by VTD non-modern mode pass */
+        return true;
+    }
+
+    error_setg(errp, "host device is unsupported in scalable modern mode yet");
+    return false;
 }
 
 static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn,
@@ -4308,14 +4314,21 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
         }
     }
 
-    /* Currently only address widths supported are 39 and 48 bits */
-    if ((s->aw_bits != VTD_HOST_AW_39BIT) &&
-        (s->aw_bits != VTD_HOST_AW_48BIT)) {
-        error_setg(errp, "Supported values for aw-bits are: %d, %d",
+    if (!s->scalable_modern && s->aw_bits != VTD_HOST_AW_39BIT &&
+        s->aw_bits != VTD_HOST_AW_48BIT) {
+        error_setg(errp, "%s mode: supported values for aw-bits are: %d, %d",
+                   s->scalable_mode ? "Scalable" : "Legacy",
                    VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT);
         return false;
     }
 
+    if (s->scalable_modern && s->aw_bits != VTD_HOST_AW_48BIT) {
+        error_setg(errp,
+                   "Scalable modern mode: supported values for aw-bits is: %d",
+                   VTD_HOST_AW_48BIT);
+        return false;
+    }
+
     if (s->scalable_mode && !s->dma_drain) {
         error_setg(errp, "Need to set dma_drain for scalable mode");
         return false;
-- 
2.34.1



  parent reply	other threads:[~2024-11-11  8:39 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-11  8:34 [PATCH v5 00/20] intel_iommu: Enable stage-1 translation for emulated device Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 01/20] intel_iommu: Use the latest fault reasons defined by spec Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 02/20] intel_iommu: Make pasid entry type check accurate Zhenzhong Duan
2024-11-11  8:34 ` Zhenzhong Duan [this message]
2024-11-11  8:34 ` [PATCH v5 04/20] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 05/20] intel_iommu: Rename slpte to pte Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 06/20] intel_iommu: Implement stage-1 translation Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 07/20] intel_iommu: Check if the input address is canonical Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 08/20] intel_iommu: Check stage-1 translation result with interrupt range Zhenzhong Duan
2024-11-13  6:55   ` CLEMENT MATHIEU--DRIF
2024-11-13  8:49     ` Duan, Zhenzhong
2024-11-14  6:04       ` CLEMENT MATHIEU--DRIF
2024-12-04  2:11   ` Jason Wang
2024-11-11  8:34 ` [PATCH v5 09/20] intel_iommu: Set accessed and dirty bits during stage-1 translation Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 10/20] intel_iommu: Flush stage-1 cache in iotlb invalidation Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 11/20] intel_iommu: Process PASID-based " Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 12/20] intel_iommu: Add an internal API to find an address space with PASID Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 13/20] intel_iommu: Add support for PASID-based device IOTLB invalidation Zhenzhong Duan
2024-12-04  3:27   ` Jason Wang
2024-11-11  8:34 ` [PATCH v5 14/20] intel_iommu: piotlb invalidation should notify unmap Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 15/20] tests/acpi: q35: allow DMAR acpi table changes Zhenzhong Duan
2024-11-20  6:09   ` CLEMENT MATHIEU--DRIF
2024-12-04  3:27   ` Jason Wang
2024-11-11  8:34 ` [PATCH v5 16/20] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2 Zhenzhong Duan
2024-12-04  3:28   ` Jason Wang
2024-11-11  8:34 ` [PATCH v5 17/20] tests/acpi: q35: Update host address width in DMAR Zhenzhong Duan
2024-11-13  7:16   ` CLEMENT MATHIEU--DRIF
2024-11-13  8:50     ` Duan, Zhenzhong
2024-11-11  8:34 ` [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for scalable modern mode Zhenzhong Duan
2024-11-19  6:54   ` CLEMENT MATHIEU--DRIF
2024-11-19  7:28     ` Duan, Zhenzhong
2024-11-19  8:59       ` CLEMENT MATHIEU--DRIF
2024-11-19  9:25         ` Duan, Zhenzhong
2024-11-20  6:11           ` CLEMENT MATHIEU--DRIF
2024-12-04  3:34   ` Jason Wang
2024-12-04  6:14     ` CLEMENT MATHIEU--DRIF
2024-12-09  3:13       ` Jason Wang
2024-12-09  6:14         ` CLEMENT MATHIEU--DRIF
2024-12-09  6:24           ` Jason Wang
2024-12-09  6:42             ` CLEMENT MATHIEU--DRIF
2024-12-11  2:22               ` Duan, Zhenzhong
2024-12-11  3:03                 ` Jason Wang
2024-12-11  6:08                   ` CLEMENT MATHIEU--DRIF
2024-11-11  8:34 ` [PATCH v5 19/20] intel_iommu: Introduce a property to control FS1GP cap bit setting Zhenzhong Duan
2024-11-11  8:34 ` [PATCH v5 20/20] tests/qtest: Add intel-iommu test Zhenzhong Duan
2024-12-03  9:00 ` [PATCH v5 00/20] intel_iommu: Enable stage-1 translation for emulated device Duan, Zhenzhong

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