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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Anton Johansson" <anjo@rev.ng>,
	"Jason Wang" <jasowang@redhat.com>,
	qemu-arm@nongnu.org,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	"Thomas Huth" <thuth@redhat.com>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Gustavo Romero" <gustavo.romero@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 05/20] hw/net/xilinx_ethlite: Correct maximum RX buffer size
Date: Tue, 12 Nov 2024 19:10:29 +0100	[thread overview]
Message-ID: <20241112181044.92193-6-philmd@linaro.org> (raw)
In-Reply-To: <20241112181044.92193-1-philmd@linaro.org>

The current max RX bufsize is set to 0x800. This is
invalid, since it contains the MMIO registers region.
Add the correct definition and use it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/net/xilinx_ethlite.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index 0f59811c78..e6f6179fce 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -46,6 +46,8 @@
 #define R_RX_CTRL1    (0x1ffc / 4)
 #define R_MAX         (0x2000 / 4)
 
+#define RX_BUFSZ_MAX  0x07e0
+
 #define GIE_GIE    0x80000000
 
 #define CTRL_I     0x8
@@ -195,7 +197,7 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
         return -1;
     }
 
-    if (size > (R_MAX - R_RX_BUF0 - rxbase) * 4) {
+    if (size > RX_BUFSZ_MAX) {
         trace_ethlite_pkt_size_too_big(size);
         return -1;
     }
-- 
2.45.2



  parent reply	other threads:[~2024-11-12 18:12 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-12 18:10 [PATCH 00/20] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 01/20] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 02/20] hw/net/xilinx_ethlite: Convert some debug logs to trace events Philippe Mathieu-Daudé
2024-11-13 15:11   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 03/20] hw/net/xilinx_ethlite: Remove unuseful debug logs Philippe Mathieu-Daudé
2024-11-13 15:11   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 04/20] hw/net/xilinx_ethlite: Update QOM style Philippe Mathieu-Daudé
2024-11-13 15:12   ` Edgar E. Iglesias
2024-11-12 18:10 ` Philippe Mathieu-Daudé [this message]
2024-11-13 15:15   ` [PATCH 05/20] hw/net/xilinx_ethlite: Correct maximum RX buffer size Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 06/20] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented) Philippe Mathieu-Daudé
2024-11-13 15:16   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 07/20] hw/net/xilinx_ethlite: Rename rxbuf -> port_index Philippe Mathieu-Daudé
2024-11-13 15:20   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 08/20] hw/net/xilinx_ethlite: Add addr_to_port_index() helper Philippe Mathieu-Daudé
2024-11-13 15:23   ` Edgar E. Iglesias
2024-11-14 19:04     ` Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 09/20] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper Philippe Mathieu-Daudé
2024-11-13 15:26   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 10/20] hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper Philippe Mathieu-Daudé
2024-11-13 15:26   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 11/20] hw/net/xilinx_ethlite: Access RX_CTRL register for each port Philippe Mathieu-Daudé
2024-11-13 15:27   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 12/20] hw/net/xilinx_ethlite: Access TX_GIE " Philippe Mathieu-Daudé
2024-11-13 15:28   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 13/20] hw/net/xilinx_ethlite: Access TX_LEN " Philippe Mathieu-Daudé
2024-11-13 15:28   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 14/20] hw/net/xilinx_ethlite: Access TX_CTRL " Philippe Mathieu-Daudé
2024-11-13 15:28   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 15/20] hw/net/xilinx_ethlite: Map RX_CTRL as MMIO Philippe Mathieu-Daudé
2024-11-13 15:29   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 16/20] hw/net/xilinx_ethlite: Map TX_LEN " Philippe Mathieu-Daudé
2024-11-13 15:30   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 17/20] hw/net/xilinx_ethlite: Map TX_GIE " Philippe Mathieu-Daudé
2024-11-13 15:34   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 18/20] hw/net/xilinx_ethlite: Map TX_CTRL " Philippe Mathieu-Daudé
2024-11-13 15:34   ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 19/20] hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region Philippe Mathieu-Daudé
2024-11-13 15:35   ` Edgar E. Iglesias
2024-11-13 18:21   ` Paolo Bonzini
2024-11-13 19:37     ` Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 20/20] hw/net/xilinx_ethlite: Rename 'mmio' MR as 'container' Philippe Mathieu-Daudé
2024-11-13 15:35   ` Edgar E. Iglesias
2024-11-13 15:36 ` [PATCH 00/20] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls Edgar E. Iglesias
2024-11-14 18:55   ` Philippe Mathieu-Daudé

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