From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Anton Johansson" <anjo@rev.ng>,
"Jason Wang" <jasowang@redhat.com>,
qemu-arm@nongnu.org,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Thomas Huth" <thuth@redhat.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Gustavo Romero" <gustavo.romero@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 06/20] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented)
Date: Tue, 12 Nov 2024 19:10:30 +0100 [thread overview]
Message-ID: <20241112181044.92193-7-philmd@linaro.org> (raw)
In-Reply-To: <20241112181044.92193-1-philmd@linaro.org>
Rather than handling the MDIO registers as RAM, map them
as unimplemented I/O within the device MR.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio
00000000810007f4-0000000081001fff (prio 0, i/o): xlnx.xps-ethernetlite @00000000000007f4
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/net/xilinx_ethlite.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index e6f6179fce..76b1e7d826 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethlite.c
@@ -25,13 +25,17 @@
#include "qemu/osdep.h"
#include "qemu/module.h"
#include "qom/object.h"
+#include "qapi/error.h"
#include "exec/tswap.h"
#include "hw/sysbus.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#include "hw/misc/unimp.h"
#include "net/net.h"
#include "trace.h"
+#define A_MDIO_BASE 0x07e4
+
#define R_TX_BUF0 0
#define R_TX_LEN0 (0x07f4 / 4)
#define R_TX_GIE0 (0x07f8 / 4)
@@ -71,6 +75,7 @@ struct XlnxXpsEthLite
unsigned int txbuf;
unsigned int rxbuf;
+ UnimplementedDeviceState mdio;
uint32_t regs[R_MAX];
};
@@ -231,6 +236,14 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
{
XlnxXpsEthLite *s = XILINX_ETHLITE(dev);
+ object_initialize_child(OBJECT(dev), "ethlite.mdio", &s->mdio,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ qdev_prop_set_string(DEVICE(&s->mdio), "name", "ethlite.mdio");
+ qdev_prop_set_uint64(DEVICE(&s->mdio), "size", 4 * 4);
+ sysbus_realize(SYS_BUS_DEVICE(&s->mdio), &error_fatal);
+ memory_region_add_subregion(&s->mmio, A_MDIO_BASE,
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio), 0));
+
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->id,
--
2.45.2
next prev parent reply other threads:[~2024-11-12 18:15 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-12 18:10 [PATCH 00/20] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 01/20] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 02/20] hw/net/xilinx_ethlite: Convert some debug logs to trace events Philippe Mathieu-Daudé
2024-11-13 15:11 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 03/20] hw/net/xilinx_ethlite: Remove unuseful debug logs Philippe Mathieu-Daudé
2024-11-13 15:11 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 04/20] hw/net/xilinx_ethlite: Update QOM style Philippe Mathieu-Daudé
2024-11-13 15:12 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 05/20] hw/net/xilinx_ethlite: Correct maximum RX buffer size Philippe Mathieu-Daudé
2024-11-13 15:15 ` Edgar E. Iglesias
2024-11-12 18:10 ` Philippe Mathieu-Daudé [this message]
2024-11-13 15:16 ` [PATCH 06/20] hw/net/xilinx_ethlite: Map MDIO registers (as unimplemented) Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 07/20] hw/net/xilinx_ethlite: Rename rxbuf -> port_index Philippe Mathieu-Daudé
2024-11-13 15:20 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 08/20] hw/net/xilinx_ethlite: Add addr_to_port_index() helper Philippe Mathieu-Daudé
2024-11-13 15:23 ` Edgar E. Iglesias
2024-11-14 19:04 ` Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 09/20] hw/net/xilinx_ethlite: Introduce txbuf_ptr() helper Philippe Mathieu-Daudé
2024-11-13 15:26 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 10/20] hw/net/xilinx_ethlite: Introduce rxbuf_ptr() helper Philippe Mathieu-Daudé
2024-11-13 15:26 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 11/20] hw/net/xilinx_ethlite: Access RX_CTRL register for each port Philippe Mathieu-Daudé
2024-11-13 15:27 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 12/20] hw/net/xilinx_ethlite: Access TX_GIE " Philippe Mathieu-Daudé
2024-11-13 15:28 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 13/20] hw/net/xilinx_ethlite: Access TX_LEN " Philippe Mathieu-Daudé
2024-11-13 15:28 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 14/20] hw/net/xilinx_ethlite: Access TX_CTRL " Philippe Mathieu-Daudé
2024-11-13 15:28 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 15/20] hw/net/xilinx_ethlite: Map RX_CTRL as MMIO Philippe Mathieu-Daudé
2024-11-13 15:29 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 16/20] hw/net/xilinx_ethlite: Map TX_LEN " Philippe Mathieu-Daudé
2024-11-13 15:30 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 17/20] hw/net/xilinx_ethlite: Map TX_GIE " Philippe Mathieu-Daudé
2024-11-13 15:34 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 18/20] hw/net/xilinx_ethlite: Map TX_CTRL " Philippe Mathieu-Daudé
2024-11-13 15:34 ` Edgar E. Iglesias
2024-11-12 18:10 ` [PATCH 19/20] hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region Philippe Mathieu-Daudé
2024-11-13 15:35 ` Edgar E. Iglesias
2024-11-13 18:21 ` Paolo Bonzini
2024-11-13 19:37 ` Philippe Mathieu-Daudé
2024-11-12 18:10 ` [PATCH 20/20] hw/net/xilinx_ethlite: Rename 'mmio' MR as 'container' Philippe Mathieu-Daudé
2024-11-13 15:35 ` Edgar E. Iglesias
2024-11-13 15:36 ` [PATCH 00/20] hw/net/xilinx_ethlite: Map RAM buffers as RAM and remove tswap() calls Edgar E. Iglesias
2024-11-14 18:55 ` Philippe Mathieu-Daudé
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